CN219085037U - ESD simulation circuit - Google Patents
ESD simulation circuit Download PDFInfo
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- CN219085037U CN219085037U CN202222883536.5U CN202222883536U CN219085037U CN 219085037 U CN219085037 U CN 219085037U CN 202222883536 U CN202222883536 U CN 202222883536U CN 219085037 U CN219085037 U CN 219085037U
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Abstract
The utility model provides an ESD simulation circuit, comprising: the first power supply is adjustable in voltage and grounded in negative electrode; the first discharging circuit comprises a first capacitor and a first resistor which are connected in series, wherein the capacitance value of the first capacitor and the resistance value of the first resistor are adjustable; the first end of the second discharging circuit is connected with the first end of the first discharging circuit, and the second end of the second discharging circuit is grounded; the first end of the load circuit is connected with the first end of the second discharging circuit through the second switch, and the second end of the load circuit is grounded; the first end of the first return circuit is connected with the positive electrode of the first power supply through the first switch, and the second end of the first return circuit is grounded; and the first end of the second return circuit is connected with the first end of the second discharging circuit through the second switch, and the second end of the second return circuit is grounded. The first power supply is used as a high power supply for generating the ESD excitation source, and the voltage value is adjustable, so that the ESD excitation source is not single.
Description
Technical Field
The utility model relates to the technical field of circuits, in particular to an ESD simulation circuit.
Background
ESD (electrostatic discharge) is a major factor causing damage to most electronic components or electronic systems due to excessive electrical stress, and with the rapid development of the automobile industry, the integration level of parts is also increasing. The testing of such very damaging products by electrostatic discharge is also one of the major challenges facing the design of current automotive applications. Particularly, the utility model relates to a highly sensitive high-speed interface, high-speed wiring, device, etc. which is vulnerable to ESD damage, and once the circuit is improperly designed, the circuit is not only easy to cause signal distortion, but also can cause bad consequences such as chip damage, capacitor breakdown, circuit burnout, etc. Often, the ESD protection design is basically shaped in the test stage, and once the test fails, the corrective measures are greatly limited and the corrective cost is high. Therefore, the industry is actively developing ESD simulation capability construction.
In the ESD simulation circuit in the prior art, ESD excitation is generally obtained through external test and is input into the ESD simulation circuit, and ESD is performed through the discharge circuit, so that circuit simulation simulating ESD is realized. And the ESD simulation circuit is based on international standard IEC 61000-4-2 (electromagnetic compatibility (EMC) part 4-2: test and measurement technique-electrostatic discharge immunity experiment).
However, prior art ESD simulation suffers from two drawbacks: 1) The ESD excitation is obtained from the outside of the ESD simulation circuit, which has the disadvantage of being single or not universally applicable; 2) The ESD simulation circuit is built on the basis of international standard IEC 61000-4-2, and only an ESD discharge network with the capacitance value of a capacitor and the resistance value of a resistor in a discharge module of 150pF/330 omega is considered, so that the standard for adapting the ESD simulation circuit is limited.
Disclosure of Invention
The utility model aims to provide an ESD simulation circuit which can realize ESD excitation directly through a self-circuit, and a discharge module is provided with a capacitance with a variable capacitance value and a resistance with a variable resistance value so as to adapt to discharge network requirements of different standards.
In order to achieve the above object, the present utility model provides an ESD simulation circuit comprising:
the first power supply is provided with an anode and a cathode, the cathode is grounded, and the voltage of the first power supply is adjustable;
the first end of the first discharging circuit is connected with the positive electrode of the first power supply through a first switch, the second end of the first discharging circuit is grounded, the first discharging circuit comprises a first capacitor and a first resistor which are connected in series, and the capacitance value of the first capacitor and the resistance value of the first resistor are adjustable;
the first end of the second discharging circuit is connected with the first end of the first discharging circuit, and the second end of the second discharging circuit is grounded;
the first end of the load circuit is connected with the first end of the second discharging circuit through a second switch, and the second end of the load circuit is grounded;
a first return circuit, a first end of which is connected with the positive electrode of the first power supply through the first switch, and a second end of which is grounded;
the first end of the second return circuit is connected with the first end of the second discharging circuit through the second switch, and the second end of the second return circuit is grounded; and
when the first switch and the second switch are all conducted, the positive electrode of the first power supply is communicated with the first end of the first discharging circuit, the first power supply charges the first discharging circuit and the second discharging circuit, the first end of the second discharging circuit is conducted with the first end of the second returning circuit, and when the first switch and the second switch are disconnected, the positive electrode of the first power supply is conducted with the first end of the first returning circuit, the first end of the second discharging circuit is conducted with the first end of the load circuit, and the first discharging circuit and the second discharging circuit discharge the load circuit.
Optionally, in the ESD simulation circuit, the method further includes: and the second power supply is used for controlling the first switch and the second switch to be simultaneously opened or simultaneously closed.
Optionally, in the ESD simulation circuit, the first discharging circuit further includes a first inductor, the first inductor is connected in series with the first resistor and the first capacitor, a first end of the first inductor is connected to the first switch, a second end of the first inductor is connected to the first end of the first resistor, a second end of the first resistor is connected to the first end of the first capacitor, and a second end of the first capacitor is grounded.
Optionally, in the ESD simulation circuit, the second discharging circuit includes a second inductor, a second resistor, and a second capacitor that are sequentially connected in series, a first end of the second inductor is connected to the first end of the first discharging circuit, a second end of the second inductor is connected to the first end of the second resistor, a second end of the second resistor is connected to the first end of the second capacitor, and a second end of the second capacitor is grounded.
Optionally, in the ESD simulation circuit, the first return circuit includes a third resistor, a first end is connected to the first switch, and a second end is grounded.
Optionally, in the ESD simulation circuit, the second return circuit includes a fourth resistor, a first end is connected to the second switch, and a second end is grounded.
Optionally, in the ESD simulation circuit, the load circuit includes a fifth resistor, a first end is connected to the second switch, and a second end is grounded.
Optionally, in the ESD simulation circuit, a value of the fifth resistor is less than 2.1 Ω.
Optionally, in the ESD simulation circuit, the first switch and the second switch are five-port voltage control switches, the first port is a control voltage input node, the second port is an "off" output node, the third port is an "on" output node, and the fourth port and the fifth port are signal control nodes.
Optionally, in the ESD simulation circuit, the voltage value of the first power supply is 2 KV-25 KV.
In the ESD simulation circuit provided by the utility model, the first power supply is used as the power supply for generating the ESD excitation source, and the voltage value is adjustable, so that the ESD excitation source is not single and can be used with other ESD simulation circuits, and the capacitance value of the first capacitor and the resistance value of the first resistor of the first discharge circuit are adjustable, namely, the discharge module has a capacitance with a variable capacitance value and a resistance with a variable resistance value, so that the discharge mode is adjustable, and the discharge of different standards is adapted.
Drawings
FIG. 1 is a schematic diagram of an ESD simulation circuit according to an embodiment of the present utility model;
fig. 2 and 3 are schematic diagrams of simulated currents obtained by using an ESD simulation circuit according to an embodiment of the utility model.
Detailed Description
Specific embodiments of the present utility model will be described in more detail below with reference to the drawings. The advantages and features of the present utility model will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the utility model.
In the following, the terms "first," "second," and the like are used to distinguish between similar elements and are not necessarily used to describe a particular order or chronological order. It is to be understood that such terms so used are interchangeable under appropriate circumstances. Similarly, if a method described herein comprises a series of steps, and the order of the steps presented herein is not necessarily the only order in which the steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method.
Referring to fig. 1, the present utility model provides an ESD simulation circuit, comprising:
the first power supply V0 is provided with an anode and a cathode, the cathode is grounded, and the voltage of the first power supply is adjustable;
the first end of the first discharging circuit is connected with the positive electrode of the first power supply V0 through a first switch K1, the second end of the first discharging circuit is grounded, the first discharging circuit comprises a first capacitor C1 and a first resistor R1 which are connected in series, and the capacitance value of the first capacitor C1 and the resistance value of the first resistor R1 are adjustable;
the first end of the second discharging circuit is connected with the first end of the first discharging circuit, and the second end of the second discharging circuit is grounded;
the first end of the load circuit is connected with the first end of the second discharging circuit through the second switch K2, and the second end of the load circuit is grounded;
the first end of the first return circuit is connected with the positive electrode of the first power supply through the first switch K1, and the second end of the first return circuit is grounded;
the first end of the second return circuit is connected with the first end of the second discharging circuit through the second switch K2, and the second end of the second return circuit is grounded; and
when the first switch K1 and the second switch K2 are both turned on, the positive electrode of the first power supply V0 is connected to the first end of the first discharging circuit, the first power supply V0 charges both the first discharging circuit and the second discharging circuit, and the first end of the second discharging circuit is connected to the first end of the second return circuit. When the first switch K1 and the second switch K2 are both disconnected, the positive electrode of the first power supply V0 is conducted with the first end of the first return circuit, the first end of the second discharging circuit is conducted with the first end of the load circuit, and the first discharging circuit and the second discharging circuit discharge the load circuit.
Further, the ESD simulation circuit further includes: the second power supply V1 is configured to control the first switch K1 and the second switch K2 to be turned on or turned off simultaneously.
Preferably, the first discharging circuit further includes a first inductor L1, the first inductor L1 is connected in series with the first resistor R1 and the first capacitor C1, a first end of the first inductor L1 is connected to the first switch K1, a second end of the first inductor L1 is connected to a first end of the first resistor R1, a second end of the first resistor R1 is connected to a first end of the first capacitor C1, and a second end of the first capacitor C1 is grounded. The second discharging circuit comprises a second inductor L2, a second resistor R2 and a second capacitor C2 which are sequentially connected in series, wherein the first end of the second inductor L2 is connected with the first end of the first discharging circuit, the second end of the second inductor L2 is connected with the first end of the second resistor R2, and the second end of the second resistor R2 is connected with the first end of the second capacitor C2 and is grounded. The first return circuit comprises a third resistor R3, the first terminal of which is connected to the first switch K1 and the second terminal of which is grounded. The second return circuit comprises a fourth resistor R4, the first terminal of which is connected to the second switch K2, and the second terminal of which is grounded. The load circuit comprises a fifth resistor R5, the first end of the fifth resistor R5 is connected with the second switch K2, the second end of the fifth resistor R is grounded, the load of the load circuit is not limited to the resistor, and the load can be any adjustable load. The fifth resistor R5 generates a corresponding standard load for the standard waveform, and the value of the fifth resistor R5 is smaller than 2.1Ω, typically 1Ω. The current probe I1 can test the current of the load circuit, the voltage probe U1 can test the voltage of the load circuit, whether the discharge simulated by the ESD circuit reaches the target or not is judged through the tested current and voltage, the values of the first resistor R1 and the first capacitor C1 are adjustable, and typical values are 150pF/330pF and 330 omega/2000 omega respectively.
The first power supply V0 is preferably a high-voltage power supply, and the voltage of the first power supply V0 may be any value from 2KV to 25KV, or may be any value out of range. The first switch K1 and the second switch K2 are five-port voltage control switches, the first port n1 is a control voltage input node, the second port n2 is an off output node, the third port n3 is an on output node, and the fourth port n4 and the fifth port n5 are control nodes. The second power supply V1 is connected to the fourth port n4 and the fifth port n5 for the first switch K1 and the second switch K2. The first switch K1 and the second switch K2 are controlled to be turned on and off by the second power supply V1. The first power V0 provides a high voltage power, and the second power V1 controls the first switch K1 and the second switch K2 to be simultaneously turned on, at this time, for the first switch K1, the first port n1 to the third port n3 are turned on, and the internal resistances of the first port n1 to the third port n3 are in mΩ level, which is equivalent to that the first port n1 to the third port n3 are through. The internal resistances of the first port n1 to the second port n2 are gΩ levels, which corresponds to the first port n1 to the second port n2 being open. For the second switch K2, at this time, the internal resistances of the first port n1 to the third port n3 are at the gΩ level, which corresponds to the first port n1 to the third port n3 of the second switch K2 being open, and the internal resistances of the first port n1 to the second port n2 of the second switch K2 are at the mΩ level, which corresponds to the first port n1 to the second port n2 being open. At this time, the first power V0 rapidly charges the first capacitor C1 and the second capacitor C2, and since the internal resistances of the first port n1 to the third port n3 of the second switch K2 are gΩ, the first port n1 to the third port n3 are open circuits, the ESD disturbance stimulus provided by the first power V0 cannot be output to the load circuit. Therefore, the process in which both the first switch K1 and the second switch K2 are turned on is a process of charging the capacitor. When the second power supply V1 is turned on to control the first switch K1 and the second switch K2 to be simultaneously turned off, for the first switch K1, the internal resistances of the first port n1 to the third port n3 are gΩ, which is equivalent to the first port n1 to the third port n3 being open. The internal resistances of the first port n1 to the second port n2 are mΩ levels, which corresponds to the first port n1 to the second port n2 being passages. For the second switch K2, at this time, the internal resistances of the first port n1 to the third port n3 are mΩ levels, which corresponds to the first port n1 to the third port n3 being a path, and the internal resistances of the first port n1 to the second port n2 are gΩ levels, which corresponds to the first port n1 to the second port n2 being an open path. At this time, the first power V0 cannot be transmitted to the subsequent stage because the internal resistances of the first to third ports n1 to n3 of the first switch K1 are gΩ and gΩ are open. At this time, the first capacitor C1 and the second capacitor C2 are in a discharging state, and the internal resistances of the first port n1 to the third port n3 of the second switch K2 are M Ω levels, which is equivalent to the first port n1 to the third port n3 being a path, and the ESD disturbance stimulus provided by the first power V0 for charging the first capacitor C1 and the second capacitor C2 is smoothly applied to the load circuit. This process is a process in which the first capacitor C1 and the second capacitor C2 are discharged, i.e., ESD injection is performed to the load circuit. At this time, the first resistor R1, the first capacitor C1 and the first inductor L1 mainly affect the second peak, and the second resistor R2, the second capacitor C2 and the second inductor L2 mainly affect the first peak. According to the utility model, the first switch K1 and the second switch K2 are controlled to be simultaneously opened and closed only by the switch control pulse voltage source, namely the second power supply V1, so that the internal resistance difference between the opening and the closing of the first switch K1 and the second switch K2 is skillfully designed, and the injection and the cut-off of the ESD interference of the circuit are effectively realized. In addition, through adjusting the values of the first resistor R1 and the first capacitor C1 of the ESD discharging module, according to the characteristics of a standard waveform and the scene arrangement of an actual ESD test, parasitic RLC parameters, namely the effects of the second resistor R2, the second capacitor C2 and the second inductor L2, caused by the influence of an electrostatic gun on a ground loop are considered in design, basic parameters of four discharging modules are preliminarily obtained according to the operation of a physical node equation, and a simulation means is introduced and fitting and debugging are carried out according to the basic parameters, so that an equivalent circuit model of the ESD generator suitable for the four discharging modules is designed, and the standard waveform is ideally matched, thereby realizing the wide application of different application scenes of the ESD generator in actual measurement. Referring to fig. 2, fig. 2 is simulation data of an embodiment of the present utility model, wherein an abscissa is time, an ordinate is ns, and an ordinate is discharge current of a load, and an ordinate is ampere. The simulation line 1 is a load current curve when the capacitance value of the first capacitor C1 is 330pF and the resistance value of the first resistor R1 is 330 ohms; the simulation line 2 is a load current curve when the capacitance of the first capacitor C1 is 150pF and the resistance of the first resistor R1 is 330 ohms. Referring to fig. 3, fig. 3 is simulation data of an embodiment of the present utility model, wherein the abscissa is time, the unit is ns, the ordinate is the discharge current of the load, the unit is ampere, the simulation line 1 is a load current curve when the capacitance value of the first capacitor C1 is 330pF, the resistance value of the first resistor R1 is 2000 ohm, and the simulation line 2 is a load current curve when the capacitance value of the first capacitor C1 is 150pF, and the resistance value of the first resistor R1 is 2000 ohm.
In summary, in the ESD simulation circuit provided by the embodiment of the utility model, the first power supply is used as a high-voltage power supply for generating the ESD excitation source, and the voltage value of the first power supply is adjustable, so that the ESD excitation source is not single and can be commonly used with other ESD simulation circuits, and the capacitance value of the first capacitor and the resistance value of the first resistor of the first discharge circuit are adjustable, that is, the discharge module has a capacitance with a variable capacitance value and a resistance with a variable resistance value, so that the discharge mode is adjustable, and the discharge network requirements of different standards are met.
The foregoing is merely a preferred embodiment of the present utility model and is not intended to limit the present utility model in any way. Any person skilled in the art will make any equivalent substitution or modification to the technical solution and technical content disclosed in the utility model without departing from the scope of the technical solution of the utility model, and the technical solution of the utility model is not departing from the scope of the utility model.
Claims (10)
1. An ESD simulation circuit, comprising:
the first power supply is provided with an anode and a cathode, the cathode is grounded, and the voltage of the first power supply is adjustable;
the first end of the first discharging circuit is connected with the positive electrode of the first power supply through a first switch, the second end of the first discharging circuit is grounded, the first discharging circuit comprises a first capacitor and a first resistor which are connected in series, and the capacitance value of the first capacitor and the resistance value of the first resistor are adjustable;
the first end of the second discharging circuit is connected with the first end of the first discharging circuit, and the second end of the second discharging circuit is grounded;
the first end of the load circuit is connected with the first end of the second discharging circuit through a second switch, and the second end of the load circuit is grounded;
a first return circuit, a first end of which is connected with the positive electrode of the first power supply through the first switch, and a second end of which is grounded;
the first end of the second return circuit is connected with the first end of the second discharging circuit through the second switch, and the second end of the second return circuit is grounded; and
when the first switch and the second switch are all conducted, the positive electrode of the first power supply is communicated with the first end of the first discharging circuit, the first power supply charges the first discharging circuit and the second discharging circuit, the first end of the second discharging circuit is conducted with the first end of the second returning circuit, and when the first switch and the second switch are both disconnected, the positive electrode of the first power supply is conducted with the first end of the first returning circuit, the first end of the second discharging circuit is conducted with the first end of the load circuit, and the first discharging circuit and the second discharging circuit discharge the load circuit.
2. The ESD simulation circuit of claim 1, further comprising: and the second power supply is used for controlling the first switch and the second switch to be simultaneously opened or simultaneously closed.
3. The ESD simulation circuit of claim 1, wherein the first discharge circuit further comprises a first inductor coupled in series with both the first resistor and the first capacitor, a first end of the first inductor coupled to the first switch, a second end of the first inductor coupled to the first end of the first resistor, a second end of the first resistor coupled to the first end of the first capacitor, and a second end of the first capacitor coupled to ground.
4. The ESD simulation circuit of claim 1, wherein the second discharge circuit comprises a second inductor, a second resistor, and a second capacitor in series, a first end of the second inductor being connected to the first end of the first discharge circuit, a second end of the second inductor being connected to the first end of the second resistor, a second end of the second resistor being connected to the first end of the second capacitor, and a second end of the second capacitor being grounded.
5. The ESD simulation circuit of claim 1, wherein the first return circuit comprises a third resistor having a first terminal coupled to the first switch and a second terminal coupled to ground.
6. The ESD simulation circuit of claim 1, wherein the second return circuit comprises a fourth resistor having a first terminal coupled to the second switch and a second terminal coupled to ground.
7. The ESD simulation circuit of claim 1, wherein the load circuit comprises a fifth resistor, a first terminal coupled to the second switch, and a second terminal coupled to ground.
8. The ESD simulation circuit of claim 7, wherein the fifth resistance has a value of less than 2.1 Ω.
9. The ESD simulation circuit of claim 1, wherein the first switch and the second switch are each five-port voltage control switches, the first port is a control voltage input node, the second port is an "off" output node, the third port is an "on" output node, and the fourth port and the fifth port are signal control nodes.
10. The ESD simulation circuit of claim 1, wherein the voltage of the first power supply is 2KV to 25KV.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222883536.5U CN219085037U (en) | 2022-10-31 | 2022-10-31 | ESD simulation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222883536.5U CN219085037U (en) | 2022-10-31 | 2022-10-31 | ESD simulation circuit |
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| Publication Number | Publication Date |
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| CN219085037U true CN219085037U (en) | 2023-05-26 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202222883536.5U Active CN219085037U (en) | 2022-10-31 | 2022-10-31 | ESD simulation circuit |
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| CN (1) | CN219085037U (en) |
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- 2022-10-31 CN CN202222883536.5U patent/CN219085037U/en active Active
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