CN219021500U - Identification circuit of medical operation electrode - Google Patents

Abstract

The utility model discloses an identification circuit of a medical operation electrode, which comprises an electrode plug and a host, wherein a single bus memory chip U9 is arranged on the electrode plug, the host comprises a voltage transformation circuit, an optical isolation reading circuit and an optical isolation writing circuit, the voltage transformation circuit outputs an isolation power supply VCC2, the isolation power supply VCC2 is respectively supplied to the optical isolation reading circuit and the optical isolation writing circuit, a data reading port is arranged on the optical isolation reading circuit, the single bus memory chip U9 is electrically connected with the data reading port through the optical isolation reading circuit, a data writing port is arranged on the optical isolation writing circuit, and the single bus memory chip U9 is electrically connected with the data writing port through the optical isolation writing circuit. The beneficial effects of the utility model are as follows: storing data in a single bus memory chip U9 and identifying the electrode type; and accessing the data stored in the single-bus memory chip U9 into the singlechip system through a data writing port for data analysis.

Description

Identification circuit of medical operation electrode

Technical Field

The utility model relates to the technical field related to surgical electrodes, in particular to an identification circuit of a medical surgical electrode.

Background

Bipolar surgical electrodes are surgical instruments used for electrosurgical treatment of patients with bipolar high frequency power sources, which, through appropriate control of high frequency power, produce surgical effects such as vaporisation cutting or coagulation of focal tissue. A high frequency surgical system can be provided with a plurality of electrodes and instruments of different types for surgical purposes.

Each dedicated electrode and instrument has different performance, such as adaptive mode limitation, maximum limiting power, etc., and if a human input setup operation is performed, the probability of error is high. The surgical electrodes and instruments are typically electronically identified by the hf surgical system. Namely, after the electrode is inserted into the high-frequency power source, the system can identify the model of the electrode and simultaneously set the optimized working parameters, the limiting parameters and the like of the electrode of the model.

The prior art adopts the following identification methods:

the capacitor identification method comprises the following steps: the method employs one or two capacitors to identify the electrodes. The capacitance of each capacitor represents the model of the electrode, and the capacitance corresponding to each model is different from other models in proper capacity, so that the identification circuit can accurately identify and more model identification values are contained in the measurable capacitance value section. The method has the advantages that a circuit for identifying and reading the capacitance is simple, one end of the capacitor is easy to achieve the reference potential with the electrode and the like, but too many models can cause the capacitance to be too large. The use of two capacitors can greatly increase the number of identifiable pins, but the electrodes will thus increase at least one connecting wire and pin. Examples of the use of this method are: "Gyeus PlasmaKinetic System" by Jia Le Medical Inc. (Gyrus Medical Inc.) and G400Work Station (G400 workstation), the former using one capacitor for identification and the latter using two capacitors for identification.

Resistance identification method: the method employs one or more resistors to identify the electrodes. Each section of resistance value area corresponds to one type, or the combination of a plurality of resistors corresponds to the type of the electrode, and the connection method is common to or insulated from the electrode. The method for reading the resistance value is simpler, and if the resistance and the electrode are in common electrode, an electrically isolated reading method is needed.

The Chinese patent application number is: the utility model discloses a CN20110172589. X, the name is "operation electrode discernment and counting device for high frequency electrosurgical equipment", including discernment count main module and radio frequency card, discernment count main module is established in the high frequency electrosurgical equipment box, the radio frequency card is established on the plug that operation electrode connects, discernment count main module includes microprocessor, radio frequency read-write module, clock circuit's signal input/output part is connected with the corresponding IO end on the microprocessor respectively, microprocessor's signal communication transmitting terminal is connected with the control end of corresponding control circuit in the high frequency electrosurgical equipment, radio frequency read-write module's antenna grafting end is connected with the antenna, when operation electrode's plug inserts and establishes on operation electrode socket, the induction working face of radio frequency card is relative with the induction working face of antenna. The utility model can identify the operation electrode, count the use times of the operation electrode, remind medical staff to replace the operation electrode with an overrun in time, and avoid hidden trouble caused by unsafe operation electrode.

The Chinese patent application number is: CN02135013.2 discloses a circuit marking method named as "medical bipolar plasma cutting head", one end of the two-port voltage stabilizing device is connected with the medical plasma cutting external electrode and the cutting head overpass, and the cutting internal electrode is connected by the cutting head connector. The system applies current to the voltage stabilizing device, the voltage of the voltage stabilizing device is tested, and different voltage stabilizing devices mark the model of the cutting head. The utility model has accurate and reliable measurement mark, the measurement accuracy is not affected by the moisture leakage factor, and the utility model can resist the impact of electric pulse.

The following analysis shows the merits of the four methods:

the types of the identifiable capacitor identification method are more, a special capacitor capacity test circuit is needed, and the test circuit can bear the interference of high-frequency current under the actual working condition. The capacitance method can only read the capacitance value, and the system host cannot store new information for the capacitance method.

The resistance method is simple to read and is more used, but when the resistance value is larger, the resistance against high-frequency current interference is reduced, and the system host cannot store new information for the resistance method.

The identification method of the two-port voltage stabilizing device is accurate and reliable, the identification circuit is simple, but the types of the identification are less, and the system host cannot store new information for the identification method.

The radio frequency card identification method has the advantages of non-contact, capability of performing interactive operations such as counting, and the like, and can be read or stored when the radio frequency card is at a certain distance from the socket, so that the radio frequency card can be used as a system to judge whether the electrode is reliably inserted or not and has uncertainty. In addition, the radio frequency card needs high-frequency induction power supply and power taking, and electromagnetic interference of a system can be increased.

Disclosure of Invention

The present utility model is to overcome the disadvantages of the various methods described above, and to provide a medical surgical electrode identification circuit which combines the advantages of the various methods described above and avoids the disadvantages thereof.

In order to achieve the above purpose, the present utility model adopts the following technical scheme:

the utility model provides an identification circuit of medical operation electrode, it includes electrode plug and host computer, be equipped with single bus memory chip U9 on the electrode plug, the host computer includes transformer circuit, light isolation reading circuit and light isolation write circuit, transformer circuit output isolation power VCC2, isolation power VCC2 is supplied with in light isolation reading circuit and light isolation write circuit respectively, be equipped with the data read entry on the light isolation reading circuit, single bus memory chip U9 is connected with the data read entry electricity through light isolation reading circuit, be equipped with the data write entry on the light isolation write circuit, single bus memory chip U9 is connected with the data write entry electricity through light isolation write circuit.

The electrode plug is provided with a single bus memory chip U9, the host comprises a voltage transformation circuit, an optical isolation reading circuit and an optical isolation writing circuit, the voltage transformation circuit outputs an isolation power supply VCC2, the isolation power supply VCC2 is respectively supplied to the optical isolation reading circuit and the optical isolation writing circuit, the optical isolation reading circuit is provided with a data reading port, the single bus memory chip U9 is electrically connected with the data reading port through the optical isolation reading circuit, the optical isolation writing circuit is provided with a data writing port, and the single bus memory chip U9 is electrically connected with the data writing port through the optical isolation writing circuit. The data writing inlet and the data writing inlet are both connected into the singlechip system for data transmission. The read-write optical isolation circuit formed by the optical isolation read circuit and the optical isolation write circuit has the isolation voltage reaching AC7500V and the speed reaching 10MBb, and compared with the magnetic isolation, the optical isolation is not easy to be interfered by electromagnetic interference, so that the isolation voltage, the communication speed and the anti-interference degree of the optical isolation communication circuit are superior to those of the magnetic isolation chip in combination; the high-frequency bipolar electrode for operation is provided with controllable high-frequency energy by a host, and data are stored in a single bus memory chip U9 through an optical isolation write circuit and the electrode type is identified; when the data is read, the data stored in the single bus memory chip U9 is accessed into the singlechip system through the data writing port by the optical isolation reading circuit for data analysis, so that the aim of avoiding the defects of the method can be achieved by combining the advantages of the method.

Preferably, the transformation circuit comprises a self-excitation half-bridge driving chip U1, a high-frequency transformer T1, a resistor R2, a resistor R3, a capacitor C4, a NAND gate U2, a NAND gate U3 and a full-bridge rectification circuit, wherein a PIN1 PIN and a PIN8 PIN on the self-excitation half-bridge driving chip U1 are electrically connected with a power supply VCC1, a PIN2 PIN on the self-excitation half-bridge driving chip U1 is electrically connected with one end of the capacitor C4 through the resistor R1, the other end of the capacitor C4 is electrically connected with a PIN4 PIN on the self-excitation half-bridge driving chip U1, the junction of the capacitor C4 and the PIN4 PIN on the self-excitation half-bridge driving chip U1 is grounded, a PIN3 PIN on the self-excitation half-bridge driving chip U1 is electrically connected with an input end of the NAND gate U2 through the resistor R2, a PIN5 PIN on the self-excitation half-bridge driving chip U1 is electrically connected with one end of the capacitor C4 through the resistor R3, the other end of the PIN3 is electrically connected with two ends of the full-bridge rectification circuit of the NAND gate U2 through the other end of the bridge C1, and the full-bridge rectification circuit is connected with the two ends of the full-bridge rectification circuit is connected with the full-bridge rectification circuit in parallel.

Preferably, the high-frequency transformer T1 includes a primary side and a secondary side, a PIN7 on the self-excited half-bridge driving chip U1 is electrically connected with one end of the primary side of the high-frequency transformer T1 through a resistor R2 and a nand gate U2 in sequence, a PIN5 on the self-excited half-bridge driving chip U1 is electrically connected with the other end of the primary side of the high-frequency transformer T1 through a resistor R3 and a nand gate U3 in sequence, and the secondary side of the high-frequency transformer T1 is electrically connected with the input end of the full-bridge rectifying circuit.

Preferably, the optical isolation reading circuit comprises a high-speed optocoupler U7, a resistor R6, a pull-up resistor R9, a NAND gate U4, a NAND gate U5, a MOS tube Q1 and an OW interface, wherein a PIN2 PIN on the high-speed optocoupler U7 is electrically connected with an isolation power VCC2 through the resistor R6, a PIN3 PIN on the high-speed optocoupler U7 is electrically connected with an output end of the NAND gate U4, an input end of the NAND gate U4 is electrically connected with an output end of the NAND gate U5, an input end of the NAND gate U5 is electrically connected with the OW interface, one end of the pull-up resistor R9 is electrically connected with a drain electrode of the MOS tube Q1 and the OW interface respectively, the other end of the pull-up resistor R9 is electrically connected with the isolation power VCC2, a source electrode of the MOS tube Q1 is grounded, a grid electrode of the MOS tube Q1 is electrically connected with an optical isolation writing circuit, the OW interface is electrically connected with a PIN2 PIN on a single bus memory chip U9, a resistor R4 and an interface are arranged on a data reading inlet, and one end of the MOS tube Q1 is electrically connected with the PIN PIN on the high-speed optocoupler U7 through the high-speed coupler RX 7.

Preferably, the optical isolation write circuit comprises a high-speed optocoupler U8, a NAND gate U6, a resistor R7, a MOS tube Q1 and a pull-down resistor R8, wherein a PIN8 PIN on the high-speed optocoupler U8 is electrically connected with an isolation power supply VCC2, a PIN6 PIN on the high-speed optocoupler U8 is electrically connected with an input end of the NAND gate U6, an output end of the NAND gate U6 is electrically connected with a grid electrode on the MOS tube Q1 through the resistor R7, one end of the pull-down resistor R8 is electrically connected with the grid electrode on the MOS tube Q1, a grounding end is formed after the other end of the pull-down resistor R8 is electrically connected with a source electrode on the MOS tube Q1, the grounding end is electrically connected with a PIN1 PIN on a single bus memory chip U9, a resistor R5 and a TX interface are arranged on the data write port, a PIN3 PIN on the high-speed optocoupler U8 is electrically connected with the TX interface through the resistor R5, and the PIN2 PIN on the high-speed optocoupler U8 is electrically connected with the power supply VCC 1.

Preferably, an ESD protection diode D5 is connected in parallel between the PIN2 on the single-bus memory chip U9 and the PIN1 on the single-bus memory chip U9, for preventing static electricity from destroying the single-bus memory chip U9 during the electrode plugging process.

Preferably, the electrode plug comprises a base and a plug body, one end of the plug body is connected with a circuit board, the single bus memory chip U9 and the ESD protection diode D5 are fixedly connected with the circuit board, one end of the plug body, which is connected with the circuit board, is fixedly connected with one end of the base through injection molding, a power line is fixed at the other end of the base, a second PIN connected with a grounding end and a first PIN connected with an OW interface are fixed at the other end of the plug body, the OW interface is electrically connected with a PIN2 PIN on the single bus memory chip U9 through the first PIN, the grounding end is electrically connected with a PIN1 PIN on the single bus memory chip U9 through the second PIN, and the circuit board is electrically connected with the power line. Pin1 on the single bus memory chip U9 is GND, PIN2 on the single bus memory chip U9 is IO. The single bus memory chip U9 is fixed on the circuit board of plug body one end terminal surface, compares in the mode of directly welding the chip to the electrode inside, welds more easily, and need not apply a large amount of thimble at the electrode plug in-process of moulding plastics and fix single bus memory chip, conveniently mould plastics, improves product reliability, reduction in production cost.

The beneficial effects of the utility model are as follows: in the isolation power supply circuit consisting of the high-frequency transformer T1, the isolation voltage can reach more than AC5000V as the high-frequency transformer T1 can be wound by itself, and the voltage resistance of the isolation power supply part of the circuit can reach more than AC5KV as the general finished isolation power supply module does not exceed more than AC5 KV; the read-write optical isolation circuit formed by the high-speed optical coupler U7 and the high-speed optical coupler U8 has the isolation voltage of AC7500V and the speed of 10MBb, and compared with the magnetic isolation, the optical isolation is not easy to be interfered by electromagnetic interference, so that the isolation voltage, the communication speed and the anti-interference degree of the optical isolation communication circuit are superior to those of the magnetic isolation chip in combination; the single bus memory chip U9 is fixed on the circuit board of plug body terminal surface, compares in the mode of directly welding the chip to the electrode inside, welds more easily, and need not apply a large amount of thimble at the electrode plug in-process of moulding plastics and fix single bus memory chip, conveniently mould plastics, improves product reliability, reduction in production cost.

Drawings

FIG. 1 is a circuit diagram of the present utility model;

FIG. 2 is a schematic view of the structure of an electrode plug;

fig. 3 is a schematic structural view of the plug body.

In the figure: 1. the base, the plug body, the single bus memory chip U9, the power line, the first pin5, the second pin6, the circuit board 7, and the ESD protection diode D5.

Detailed Description

The utility model is further described below with reference to the drawings and detailed description.

In the embodiment shown in fig. 1, an identification circuit for a medical operation electrode includes an electrode plug and a host, the electrode plug is provided with a single bus memory chip U93, the host includes a voltage transformation circuit, an optical isolation reading circuit and an optical isolation writing circuit, the voltage transformation circuit outputs an isolation power VCC2, the isolation power VCC2 is respectively supplied to the optical isolation reading circuit and the optical isolation writing circuit, the optical isolation reading circuit is provided with a data reading port, the single bus memory chip U93 is electrically connected with the data reading port through the optical isolation reading circuit, and the optical isolation writing circuit is provided with a data writing port.

The transformation circuit comprises a self-excitation half-bridge driving chip U1, a high-frequency transformer T1, a resistor R2, a resistor R3, a capacitor C4, a NAND gate U2, a NAND gate U3 and a full-bridge rectification circuit, wherein a PIN1 PIN and a PIN8 PIN on the self-excitation half-bridge driving chip U1 are electrically connected with a power supply VCC1, a PIN2 PIN on the self-excitation half-bridge driving chip U1 is electrically connected with one end of the capacitor C4 through the resistor R1, the other end of the capacitor C4 is electrically connected with a PIN4 PIN on the self-excitation half-bridge driving chip U1, the connection position of the capacitor C4 and the PIN4 PIN on the self-excitation half-bridge driving chip U1 is grounded, a PIN3 PIN on the self-excitation half-bridge driving chip U1 is electrically connected with the input end of the NAND gate U2 through the resistor R2, a PIN5 PIN on the self-excitation half-bridge driving chip U1 is electrically connected with the input end of the NAND gate U3 through the resistor R3, the output end of the NAND gate U2 and the output end of the full-bridge rectification circuit is connected with the other end of the full-bridge rectification circuit through the high-frequency bridge C2, and the full-bridge rectification circuit is connected with the other end of the full-bridge rectification circuit in parallel connection between the two ends of the full-bridge rectification circuit and the full-bridge output end of the full-bridge.

The high-frequency transformer T1 comprises a primary side and a secondary side, a PIN7 PIN on the self-excitation half-bridge driving chip U1 is electrically connected with one end of the primary side of the high-frequency transformer T1 through a resistor R2 and a NAND gate U2 in sequence, a PIN5 PIN on the self-excitation half-bridge driving chip U1 is electrically connected with the other end of the primary side of the high-frequency transformer T1 through a resistor R3 and a NAND gate U3 in sequence, and the secondary side of the high-frequency transformer T1 is electrically connected with the input end of the full-bridge rectifying circuit.

The optical isolation reading circuit comprises a high-speed optocoupler U7, a resistor R6, a pull-up resistor R9, a NAND gate U4, a NAND gate U5, a MOS tube Q1 and an OW interface, wherein a PIN2 PIN on the high-speed optocoupler U7 is electrically connected with an isolation power VCC2 through the resistor R6, a PIN3 PIN on the high-speed optocoupler U7 is electrically connected with an output end of the NAND gate U4, an input end of the NAND gate U4 is connected with an output end of the NAND gate U5, an input end of the NAND gate U5 is electrically connected with the OW interface, one end of the pull-up resistor R9 is electrically connected with a drain electrode of the MOS tube Q1 and the OW interface respectively, the other end of the pull-up resistor R9 is electrically connected with an isolation power VCC2, a source electrode of the MOS tube Q1 is grounded, a grid electrode of the MOS tube Q1 is electrically connected with an optical isolation writing circuit, a PIN6 PIN on the high-speed optocoupler U7 is electrically connected with the single bus memory chip U93, a resistor R4 and an RX interface are arranged on a data reading port, a PIN6 PIN on the high-speed optocoupler U7 is electrically connected with the interface through the resistor R4, and the PIN8 on the high-speed optocoupler U7 is electrically connected with the high-speed coupler U7.

The optical isolation write circuit comprises a high-speed optocoupler U8, a NAND gate U6, a resistor R7, a MOS tube Q1 and a pull-down resistor R8, wherein a PIN8 PIN on the high-speed optocoupler U8 is electrically connected with an isolation power supply VCC2, a PIN6 PIN on the high-speed optocoupler U8 is electrically connected with an input end of the NAND gate U6, an output end of the NAND gate U6 is electrically connected with a grid electrode on the MOS tube Q1 through the resistor R7, one end of the pull-down resistor R8 is electrically connected with the grid electrode on the MOS tube Q1, the other end of the pull-down resistor R8 is electrically connected with a source electrode on the MOS tube Q1 to form a grounding end, the grounding end is electrically connected with a PIN1 PIN on a single bus memory chip U93, a resistor R5 and a TX interface are arranged on a data write-in port, and a PIN3 PIN on the high-speed optocoupler U8 is electrically connected with the power supply VCC1 through the resistor R5 and the TX interface.

An ESD protection diode D55 is connected in parallel between PIN2 on the single bus memory chip U93 and PIN1 on the single bus memory chip U93.

As shown in fig. 2 and 3, the electrode plug includes a base 1 and a plug body 2, one end of the plug body 2 is connected with a circuit board 7, a single bus memory chip U93 and an ESD protection diode D55 are both fixedly connected with the circuit board 7, one end of the plug body 2 connected with the circuit board 7 is fixedly connected with one end of the base 1 through injection molding, the other end of the base 1 is fixedly connected with a power cord 4, the other end of the plug body 2 is fixedly connected with a second PIN6 connected with a grounding end and two first PINs 5 connected with an OW interface, the OW interface is electrically connected with a PIN2 PIN on the single bus memory chip U93 through the first PIN5, the grounding end is electrically connected with a PIN1 PIN on the single bus memory chip U93 through the second PIN6, and the circuit board 7 is electrically connected with the power cord 4.

The specific principle of the circuit is as follows: the single bus memory chip U9 is used for storing data, and the ESD protection diode D5 is an ESD protection diode and is used for preventing the U9 from being destroyed by static electricity in the electrode plugging process; the self-excitation half-bridge driving chip U1 can generate two paths of complementary PWM signals on the PIN5 and the PIN7, the frequency of the PWM signals is determined by R1 and C4, one example model of the self-excitation half-bridge driving chip U1 can be IR2153S, the PIN1 is VCC, the PIN2 is RT, the PIN3 is CT, the PIN4 is COM, the PIN5 is LO, the PIN6 is VS, the PIN7 is HO, and the PIN8 is VB; after the PWM signal generated by the self-excitation half-bridge driving chip U1 is amplified by the power of the NAND gate U2 and the power of the NAND gate U3, the generated high-frequency current is connected to the primary side of the transformer T1; after the primary side of the high-frequency transformer T1 is input with high-frequency current, alternating current induction current is generated on the secondary side of the high-frequency transformer T1, then the alternating current induction current is changed into direct current after passing through a full-bridge rectifying circuit formed by D1, D2, D3 and D4, and then an isolated power supply VCC2 can be obtained after filtering by capacitors C1 and C2, wherein the VCC2 is used for supplying power to U4, U6, U7 and U8; the PIN6 PIN of the high-speed optical coupler U7 forms a data read-in port through the R4, the PIN3 PIN of the high-speed optical coupler U8 forms a data write-in port through the R5, and the two form a data read-in interface which can be connected into the singlechip system for complete data reading. An example model of the high-speed optocoupler U7 and the high-speed optocoupler U8 is ACNT-H61L, the isolation voltage can reach AC7500V, and the communication speed can reach 10MBb.

In the data writing process, after the data to be written is transmitted to the TX interface, the data is isolated and inverted by the high-speed optocoupler U8, and then the data is connected to the NAND gate U6, wherein the NAND gate U6 acts as the inversion and the power amplification of the data. The signal output by the NAND gate U6 is connected to the grid electrode of the MOS tube Q1 through the R7, and at the moment, the MOS tube Q1 can be controlled to be turned on and off, so that the data are written into the single bus memory chip U9 through an OW interface in cooperation with the pull-up resistor R9.

In the data reading process, after receiving the data reading signal, the single bus memory chip U9 can actively pull down or pull up the OW bus to transfer data to the RX interface, and finally is connected into the singlechip system, and the specific process is as follows: the OW bus is pulled up or pulled down by the single bus memory chip U9, the signal enters a PIN3 PIN of the high-speed optocoupler U7 through twice inverting amplification of the NAND gate U4 and the NAND gate U5, and finally reaches an RX interface through a PIN6 PIN of the high-speed optocoupler U7 through R4 through isolation amplification of the high-speed optocoupler U7, and finally is accessed into the singlechip system for data analysis.

Claims (7)

1. The utility model provides a medical operation electrode's identification circuit, its characterized in that includes electrode plug and host computer, be equipped with single bus memory chip U9 (3) on the electrode plug, the host computer includes transformer circuit, optical isolation reading circuit and optical isolation write circuit, transformer circuit output isolation power VCC2, isolation power VCC2 is supplied with in optical isolation reading circuit and optical isolation write circuit respectively, be equipped with the data read-in mouth on the optical isolation reading circuit, single bus memory chip U9 (3) are connected with the data read-in mouth electricity through optical isolation reading circuit, be equipped with the data write-in mouth on the optical isolation write circuit.

2. The identification circuit of a medical operation electrode according to claim 1, wherein the transformation circuit comprises a self-excitation half-bridge driving chip U1, a high-frequency transformer T1, a resistor R2, a resistor R3, a capacitor C4, a NAND gate U2, a NAND gate U3 and a full-bridge rectifying circuit, a PIN1 PIN and a PIN8 PIN on the self-excitation half-bridge driving chip U1 are electrically connected with a power VCC1, a PIN2 PIN on the self-excitation half-bridge driving chip U1 is electrically connected with one end of the capacitor C4 through the resistor R1, the other end of the capacitor C4 is electrically connected with a PIN4 PIN on the self-excitation half-bridge driving chip U1, the junction of the PIN3 PIN on the self-excitation half-bridge driving chip U1 and the resistor R1 is grounded, a PIN7 PIN on the self-excitation half-bridge driving chip U1 is electrically connected with an input end of the NAND gate U2 through the resistor R2, the other end of the self-excitation half-bridge driving chip U1 is electrically connected with an output end of the full-bridge rectifying circuit through the PIN3 PIN C2, and the full-bridge rectifying circuit is connected with the other end of the full-bridge rectifying circuit through the other end of the bridge C2, and the full-bridge rectifying circuit is connected with the other end of the full-bridge output end of the full-bridge C2 through the input end of the bridge C2.

3. The medical operation electrode identification circuit according to claim 2, wherein the high-frequency transformer T1 comprises a primary side and a secondary side, PIN7 on the self-excited half-bridge driving chip U1 is electrically connected with one end of the primary side of the high-frequency transformer T1 through a resistor R2 and a nand gate U2 in sequence, PIN5 on the self-excited half-bridge driving chip U1 is electrically connected with the other end of the primary side of the high-frequency transformer T1 through a resistor R3 and a nand gate U3 in sequence, and the secondary side of the high-frequency transformer T1 is electrically connected with the input end of the full-bridge rectifying circuit.

4. The medical operation electrode identification circuit according to claim 1, wherein the optical isolation reading circuit comprises a high-speed optical coupler U7, a resistor R6, a pull-up resistor R9, a NAND gate U4, a NAND gate U5, a MOS tube Q1 and an OW interface, a PIN2 PIN on the high-speed optical coupler U7 is electrically connected with an isolation power VCC2 through the resistor R6, a PIN3 PIN on the high-speed optical coupler U7 is electrically connected with an output end of the NAND gate U4, an input end of the NAND gate U4 is connected with an output end of the NAND gate U5, an input end of the NAND gate U5 is electrically connected with the OW interface, one end of the pull-up resistor R9 is electrically connected with a drain electrode of the MOS tube Q1 and the OW interface respectively, the other end of the pull-up resistor R9 is electrically connected with an isolation power supply 2, a source electrode of the MOS tube Q1 is grounded, a grid electrode of the MOS tube Q1 is electrically connected with an optical isolation writing circuit, the OW interface is electrically connected with an output end of the single bus memory chip U9 (3), the PIN PIN is electrically connected with the MOS tube Q1 through the drain electrode, the high-speed optical coupler U7 is electrically connected with the MOS tube Q1, and the PIN7 is electrically connected with the high-speed optical coupler U7 through the MOS tube Q1.

5. The medical operation electrode identification circuit according to claim 4, wherein the optical isolation write circuit comprises a high-speed optocoupler U8, a NAND gate U6, a resistor R7, a MOS tube Q1 and a pull-down resistor R8, a PIN8 PIN on the high-speed optocoupler U8 is electrically connected with an isolation power supply VCC2, a PIN6 PIN on the high-speed optocoupler U8 is electrically connected with an input end of the NAND gate U6, an output end of the NAND gate U6 is electrically connected with a grid electrode on the MOS tube Q1 through the resistor R7, one end of the pull-down resistor R8 is electrically connected with a grid electrode on the MOS tube Q1, the other end of the pull-down resistor R8 is electrically connected with a source electrode on the MOS tube Q1 to form a grounding end, the grounding end is electrically connected with a PIN1 PIN on a single bus memory chip U9 (3), a resistor R5 and a TX interface are arranged on the data write-in port, the PIN3 PIN on the high-speed optocoupler U8 is electrically connected with the TX interface through the resistor R5, and the PIN8 is electrically connected with the MOS tube Q1.

6. The medical-use surgical-electrode identification circuit according to claim 5, wherein an ESD protection diode D5 (8) is connected in parallel between PIN2 on the single-bus memory chip U9 (3) and PIN1 on the single-bus memory chip U9 (3).

7. The medical operation electrode identification circuit according to claim 5 or 6, wherein the electrode plug comprises a base (1) and a plug body (2), one end of the plug body (2) is connected with a circuit board (7), the single bus memory chip U9 (3) and the ESD protection diode D5 (8) are fixedly connected with the circuit board (7), one end of the plug body (2) connected with the circuit board (7) and one end of the base (1) are fixedly connected into a whole through injection molding, the other end of the base (1) is fixedly provided with a power wire (4), the other end of the plug body (2) is fixedly provided with a PIN two (6) connected with a grounding end and a PIN one (5) connected with an OW interface, the OW interface is electrically connected with a PIN2 PIN on the single bus memory chip U9 (3) through the PIN one PIN two (5), the grounding end is electrically connected with a PIN1 PIN on the single bus memory chip U9 (3) through the PIN two (6), and the circuit board (7) is electrically connected with the power wire (4).

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