CN218974522U - Chip grading test device and chip grading test system - Google Patents

Abstract

The application discloses chip grading test device and chip grading test system for divide the grade of good product for the chip, chip grading test device includes major structure, switching structure and a plurality of test board, and switching structure sets up on major structure, and switching structure includes keysets, a plurality of chip interface and a plurality of test board interface, and the chip interface sets up in the one side that the keysets is close to major structure, and the test board interface sets up the one side that the keysets deviates from major structure; the plurality of test boards are arranged on the test board in parallel and are connected with the plurality of test board interfaces in one-to-one correspondence, and the plurality of chip interfaces are respectively connected with a plurality of chips to be tested; the testing board is provided with a plurality of pins and a plurality of jumper caps, and the jumper caps are used for shorting the pins so as to adapt to chips to be tested with different specifications, and the pins are arranged on the side edge of the testing board in parallel. Through the design, the detection speed is improved, and the service life of the test board is prevented from being reduced.

Description

Chip grading test device and chip grading test system

Technical Field

The application relates to the field of chip grading test, in particular to a chip grading test device and a chip grading test system.

Background

The chip, also called microcircuit or integrated circuit, refers to a silicon chip containing integrated circuit, its volume is very small, and it is an important component of electronic equipment such as computer. Because the chip has a fine structure, a complex manufacturing process and a complicated flow, potential defects are inevitably left in the production process, so that the manufactured chip cannot meet the standard requirement, and faults can occur due to various reasons at any time. Therefore, the chip is subjected to the testing of the good grade before leaving the factory, and the testing is used as the basis of the selling price of the chip.

In order to make the test board test more different chips, the industry sets a plurality of pins on the test board and shorts the different pins with the jumper cap to change the voltage of the test board to adapt to different chips. Therefore, when different chips are replaced for testing, only the pins of the jumper cap short circuit need to be replaced, and as the current test boards are arranged in parallel, and the pins are arranged on the opposite surfaces of the adjacent test boards, the convenience is brought to workers in replacing the pins of the jumper cap short circuit.

Disclosure of Invention

The purpose of this application is to provide a chip hierarchical testing arrangement and chip hierarchical test system, improves detection speed, avoids the life of test board to reduce.

The application discloses chip grading test device is used for grading chips, and comprises a main body structure, an adapter structure and a plurality of test boards, wherein the adapter structure is arranged on the main body structure and comprises an adapter plate, a plurality of chip interfaces and a plurality of test board interfaces, the chip interfaces are arranged on one surface, close to the main body structure, of the adapter plate, and the test board interfaces are arranged on one surface, deviating from the main body structure, of the adapter plate; the plurality of test boards are arranged on the test board in parallel and are connected with the plurality of test board interfaces in one-to-one correspondence, and the plurality of chip interfaces are respectively connected with a plurality of chips to be tested; the testing board is provided with a plurality of pins and a plurality of jumper caps, the jumper caps are used for shorting the pins so as to adapt to chips to be tested of various different specifications, and the pins are arranged on the side edge of the testing board in parallel.

Optionally, the chip grading test device further includes a carrying structure, the carrying structure is located between the main structure and the adapting structure, and is used for placing a plurality of chips to be tested, and the carrying structure is movably connected with the main structure, and is used for controlling on-off between the chips to be tested and the chip interfaces.

Optionally, the chip interface is a thimble interface, and when the bearing structure moves towards the direction of the switching structure to enable the thimble interface to be in contact with the chip to be tested, the thimble interface is communicated with the chip to be tested.

Optionally, the bearing structure further comprises at least one positioning hole, and the positioning hole is arranged at the edge of the tray; the switching structure further comprises at least one positioning column, wherein the positioning column is arranged on one side, facing the bearing structure, of the switching plate, and the positioning column and the positioning hole are correspondingly arranged.

Optionally, the bearing structure includes a tray and a plurality of chip mounting grooves, and a plurality of the chip mounting grooves all set up the tray is close to the one side of switching structure, a plurality of wait to test the chip and set up respectively in a plurality of the chip mounting groove.

Optionally, a limiting structure is arranged on the positioning column, the limiting structure surrounds the outer surface of the positioning column, the orthographic projection area of the limiting structure is larger than that of the positioning hole, and the distance between the limiting structure and the adapter plate is equal to the length of the inner thimble of the thimble interface.

Optionally, the chip grading test device comprises 14 test boards, and the distance between two adjacent test boards is 25cm.

Optionally, one of the test boards is connected to 8 chips to be tested simultaneously.

Optionally, the chip interface includes a chip base, the chip base includes a base main body and a cover body, the cover body covers the base main body, and the chip to be tested is arranged between the base main body and the cover body.

The application also discloses a chip grading test system, which comprises a computer end and the chip grading test device, wherein the computer end is electrically connected with a test board of the chip grading test device.

For the stitch is the scheme that is located the adjacent one side of two adjacent test boards, this application is through changing the position of stitch, will be located the stitch of the relative one side of two adjacent test boards originally, has changed to the side of test board, and when changing different specifications test chip that awaits measuring like this, it is more convenient to insert and get the jumper wire cap, need not take off whole test board from the test board interface, improves detection speed, avoids the life reduction of test board.

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained from these drawings without inventive faculty for a person skilled in the art. In the drawings:

FIG. 1 is a schematic diagram of a chip scale test system according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a chip scale test apparatus according to a first embodiment of the present application;

FIG. 3 is an enlarged schematic view of the test plate of FIG. 2;

fig. 4 is a schematic diagram of a chip interface on a interposer according to a first embodiment of the present application;

FIG. 5 is a schematic view of a load bearing structure of a first embodiment of the present application;

FIG. 6 is a schematic illustration of the cooperation of a load bearing structure and a transfer structure of a first embodiment of the present application;

fig. 7 is a schematic diagram of a chip mount according to a second embodiment of the present application.

10, a chip grading test system; 20. a computer terminal; 30. a chip to be tested; 100. chip grading test device; 110. a main body structure; 120. a switching structure; 121. an adapter plate; 122. positioning columns; 123. a limit structure; 130. a chip interface; 131. a thimble interface; 140. a test board interface; 200. a test board; 210. a stitch; 220. a jumper cap; 300. a load bearing structure; 310. a tray; 311. positioning holes; 320. a chip mounting groove; 400. a chip base; 410. a base body; 420. and a cover body.

Detailed Description

It is to be understood that the terminology used herein, the specific structural and functional details disclosed, 5 are merely representative of the embodiments, but that the present application may be embodied in many different forms

Alternative forms of implementation should not be construed as limited to only the embodiments set forth herein.

In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating relative importance or implicitly indicating the number of technical features indicated

Amount of the components. Thus, unless otherwise indicated, features defining "first", "second" may include one or more of such features either explicitly or implicitly, or by explicitly or implicitly; the meaning of "plurality" is two or

More than two. The terms "comprises," "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that one or more additional features, integers, steps, operations, elements, components, and-

Or a combination thereof.

In addition, directions indicated by "center", "lateral", "upper", "lower", "left", "right", 5 "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like

The terms of position or positional relationship are described based on the orientation or relative positional relationship shown in the drawings, and are merely for convenience of simplifying the description of the present application, and do not indicate that the apparatus or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present application.

0 furthermore, unless expressly specified and limited otherwise, the terms "mounted," "connected," and "connected" are used interchangeably,

"connected" is to be understood broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; either directly or indirectly through intermediaries, or in communication with each other. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.

The present application is described in detail below with reference to the attached drawings and alternative embodiments.

Fig. 1 is a schematic diagram of a chip grading test system according to an embodiment of the present application, as shown in fig. 1, the present application discloses a chip grading test system 10 for grading good products of chips, where the chip grading test system 10 includes a computer terminal 20 and a chip grading test device 100 as a basis for factory pricing, the computer terminal 20 is electrically connected with a test board 200 of the chip grading test device 100, provides power for the test board 200, and uploads a chip testing structure to the computer terminal 20.

The application also discloses a chip grading test device 100, the chip grading test device 100 is used in the chip grading test system 10, and for the chip grading test device 100, the application provides the following design:

example 1:

fig. 2 is a schematic diagram of a chip grading test device according to an embodiment of the present application, as shown in fig. 2, the present application further discloses a chip grading test device 100 for grading chips, where the chip grading test device 100 includes a main body structure 110, a switching structure 120, and a plurality of test boards 200.

The adapting structure 120 is disposed on the main body structure 110, and the adapting structure 120 includes an adapting board 121, a plurality of chip interfaces 130, and a plurality of test board interfaces 140, where the chip interfaces 130 are disposed on a surface of the adapting board 121 near the main body structure 110, and the test board interfaces 140 are disposed on a surface of the adapting board 121 facing away from the main body structure 110; the plurality of test boards 200 are arranged on the test board 200 in parallel, are connected with the plurality of test board interfaces 140 in a one-to-one correspondence manner, and the plurality of chip interfaces 130 are respectively connected with a plurality of chips 30 to be tested.

As shown in fig. 3, the test board 200 is rectangular, where a plurality of pins 210 and a plurality of jumper caps 220 are disposed on the test board 200, and the jumper caps 220 are used for shorting the pins 210 to adapt to the chips 30 to be tested with different specifications, and different voltages can be output due to different voltages corresponding to different chips and different pins 210 being connected by the jumper caps 220, so as to adapt to different chips, and improve the adaptability of the test board 200.

The plurality of pins 210 are disposed in parallel on the sides of the test board 200, that is, the pins 210 are not disposed on the sides of two adjacent test boards 200, and the pins 210 may be disposed on any one of the other three sides of the test board 200, the upper side board, or the left and right sides.

The chip grading test device 100 of the present application includes 14 test boards 200, and one test board 200 is simultaneously connected with 8 chips 30 to be tested, for example, to explain, so that the chip grading test device 100 of the present application can test 112 chips 30 to be tested at a time, and of course, more test boards 200 can be provided to meet the requirement of batch detection.

And, the distance between two adjacent test boards 200 is 25cm, the structure of the whole chip grading test device 100 is more compact, and the volume of the chip grading test device 100 is reduced.

When testing chips 30 with different specifications, the jumper cap 220 needs to be pulled out from the original pins 210 and inserted into the corresponding other pins 210, and the original pins 210 are located on the adjacent surfaces of the two adjacent test boards 200, so that the whole test board 200 needs to be removed from the test board interface 140 on the adapter board 121, and the jumper cap 220 can be inserted and removed.

Compared with the scheme, the stitch 210 originally positioned on the opposite side of the two adjacent test boards 200 is changed to the side edge of the test board 200 by changing the position of the stitch 210, so that the jumper cap 220 is more convenient to insert and take when the chips 30 to be tested with different specifications are replaced, the whole test board 200 is not required to be taken down from the test board interface 140, the detection speed is improved, and the service life of the test board 200 is prevented from being reduced.

Moreover, the chip grading test device 100 further includes a carrying structure 300, where the carrying structure 300 is located between the main structure 110 and the adapting structure 120, and is used for placing a plurality of chips 30 to be tested, and the carrying structure 300 is movably connected with the main structure 110, and is used for controlling on-off between the chips 30 to be tested and the chip interface 130.

That is, the chip 30 to be tested can be placed on the carrying structure 300, and the carrying structure 300 can move up and down and left and right, so that the connection and disconnection between the chip 30 to be tested and the chip interface 130 can be realized. Thus, the chips 30 to be tested are not required to be connected with the chip interface 130 one by one, so that the detection speed is improved.

As shown in fig. 4 and 6, the chip interface 130 is a pin interface 131, when the carrier structure 300 moves toward the direction of the adapting structure 120 to make the pin interface 131 contact with the chip 30 to be tested, the pin interface 131 is communicated with the chip 30 to be tested, and when the carrier structure 300 moves away from the direction of the adapting structure 120, the pin interface 131 is disconnected from the chip 30 to be tested.

Through thimble interface 131, the connection and disconnection between chip to be tested 30 and chip interface 130 is more convenient and quick.

As shown in fig. 5, since the present application can test 112 chips 30 to be tested simultaneously, in order to ensure that each chip can be aligned and connected successfully with the chip interface 130, the present application further makes the following design, specifically:

the carrier structure 300 includes a tray 310 and a plurality of chip mounting slots 320, wherein the plurality of chip mounting slots 320 are disposed on a side of the tray 310, which is close to the adapting structure 120, and the plurality of chips 30 to be tested are disposed in the plurality of chip mounting slots 320 respectively.

Therefore, when the chips 30 to be tested are subjected to the hierarchical test, the chips 30 to be tested are only required to be placed into the chip mounting grooves 320 one by one, and the situation that the chips 30 to be tested and the tray 310 cannot be connected in a normal alignment mode due to the fact that the chips 30 to be tested and the chip interfaces 130 cannot be displaced in the moving process of the bearing structure 300 can be prevented.

In combination with fig. 4-6, in order to ensure that the accurate transfer device of the bearing device performs alignment, the present application further designs that a positioning hole 311 is provided at the edge of the tray 310, and a positioning column 122 is further provided on the transfer plate 121, where the positioning column 122 is disposed on a side of the transfer plate 121 facing the bearing structure 300, and the positioning column 122 is disposed corresponding to the positioning hole 311. Thus, when the carrying structure 300 moves toward the direction of the adapting structure 120, the positioning posts 122 pass through the positioning holes 311, so as to position both the tray 310 and the adapting plate 121.

Further, in order to prevent the problem that the thimble interface 131 is bent due to the transition upward movement of the bearing structure 300, the present application further increases the limiting structure 123, specifically, the limiting structure 123 is disposed around the outer surface of the positioning post 122, the orthographic projection area of the limiting structure 123 is greater than the orthographic projection area of the positioning hole 311, and the distance between the limiting structure 123 and the adapter plate 121 is equal to the length of the thimble in the thimble interface 131.

When the carrying structure 300 moves toward the transferring structure 120, the positioning posts 122 pass through the positioning holes 311, and the carrying structure 300 abuts against the limiting structure 123, so as to prevent the carrying structure 300 from moving further toward the transferring structure 120.

Example 2:

fig. 7 is a schematic diagram of a chip mount according to a second embodiment of the present application, as shown in fig. 7, unlike the first embodiment, the chip interface 130 of the present embodiment is provided with a chip mount 400 for fixing a chip 30 to be tested, and specifically, the chip mount 400 includes a mount main body 410 and a cover 420, the cover 420 covers the mount main body 410, and the chip 30 to be tested is disposed between the mount main body 410 and the cover 420.

Compared with the first embodiment, the chip 30 to be tested is directly arranged between the base main body 410 and the cover 420 for fixing; the instability of connection between the ejector pin interface 131 and the chip 30 to be tested is avoided, the chip interface 130 of the chip 30 to be tested is not easily disconnected in the process of testing the chip 30 to be tested, and the reliability of the test result is improved. And thus the carrier structure 300 can be omitted, reducing the volume of the chip scale test apparatus 100.

It should be noted that, the inventive concept of the present application may form a very large number of embodiments, but the application documents have limited space and cannot be listed one by one, so that on the premise of no conflict, the above-described embodiments or technical features may be arbitrarily combined to form new embodiments, and after the embodiments or technical features are combined, the original technical effects will be enhanced.

The foregoing is a further detailed description of the present application in connection with specific alternative embodiments, and it is not intended that the practice of the present application be limited to such descriptions. It should be understood that those skilled in the art to which the present application pertains may make several simple deductions or substitutions without departing from the spirit of the present application, and all such deductions or substitutions should be considered to be within the scope of the present application.

Claims (10)

1. The chip grading test device is used for grading chips and is characterized by comprising a main body structure, an adapter structure and a plurality of test boards, wherein the adapter structure is arranged on the main body structure and comprises an adapter plate, a plurality of chip interfaces and a plurality of test board interfaces, the chip interfaces are arranged on one surface of the adapter plate, which is close to the main body structure, and the test board interfaces are arranged on one surface of the adapter plate, which is away from the main body structure;

the plurality of test boards are arranged on the test board in parallel and are connected with the plurality of test board interfaces in one-to-one correspondence, and the plurality of chip interfaces are respectively connected with a plurality of chips to be tested;

the testing board is provided with a plurality of pins and a plurality of jumper caps, the jumper caps are used for shorting the pins so as to adapt to chips to be tested of various different specifications, and the pins are arranged on the side edge of the testing board in parallel.

2. The chip grading test device according to claim 1, further comprising a carrying structure, wherein the carrying structure is located between the main body structure and the switching structure, and is used for placing a plurality of chips to be tested, and the carrying structure is movably connected with the main body structure, and is used for controlling on-off between the chips to be tested and the chip interface.

3. The chip classification testing apparatus according to claim 2, wherein the chip interface is of a type of a thimble interface, and the thimble interface communicates with the chip to be tested when the carrying structure moves toward the direction of the switching structure to bring the thimble interface into contact with the chip to be tested.

4. The chip classification testing device according to claim 3, wherein the carrying structure comprises a tray and a plurality of chip mounting grooves, the plurality of chip mounting grooves are all formed in one side of the tray close to the switching structure, and the plurality of chips to be tested are respectively arranged in the plurality of chip mounting grooves.

5. The chip scale test device of claim 4, wherein the carrier structure further comprises at least one locating hole disposed at an edge of the tray;

the switching structure further comprises at least one positioning column, wherein the positioning column is arranged on one side, facing the bearing structure, of the switching plate, and the positioning column and the positioning hole are correspondingly arranged.

6. The chip grading test device according to claim 5, wherein the positioning column is provided with a limiting structure, the limiting structure is arranged around the outer surface of the positioning column, the orthographic projection area of the limiting structure is larger than the orthographic projection area of the positioning hole, and the distance between the limiting structure and the adapter plate is equal to the length of the inner thimble of the thimble interface.

7. The chip scale test apparatus according to claim 1, wherein the chip scale test apparatus comprises 14 of the test boards, and a distance between two adjacent test boards is 25cm.

8. The chip scale test apparatus according to claim 1, wherein one of said test boards connects 8 of said chips under test simultaneously.

9. The chip scale test apparatus of claim 1, wherein the chip interface comprises a chip mount comprising a mount body and a cover that is covered on the mount body, the chip to be tested being disposed between the mount body and the cover.

10. A chip grading test system, characterized in that the chip grading test system comprises a computer terminal and a chip grading test device according to any of claims 1-9, the computer terminal being electrically connected to a test board of the chip grading test device.

Images