CN218866345U - Safety controller - Google Patents

Abstract

The application discloses a safety controller which is of a two-out-of-two structure; the two-out-of-two structure comprises two mutually independent control modules; each control module comprises a main processor, a coprocessor, a first Ethernet chip, a second Ethernet chip and a third Ethernet chip; the main processor comprises an integrated MAC, a PCIe interface, a LIO interface, a first RGMII interface and a second RGMII interface; the main processor is connected with the coprocessor through a PCIe interface and a LIO interface respectively; the integrated MAC of the main processor is connected with the first Ethernet chip through the first RGMII interface; the coprocessor is connected with the second Ethernet chip through a parallel interface; the integrated MAC is connected with the third Ethernet chip through the second RGMII interface so as to realize the conversion between the RGMII interface and the FIBER interface.

Description

Safety controller

Technical Field

The present application relates to the field of train control technologies, and more particularly, to a safety controller.

Background

Modern trams are generally equipped with a tram vehicle-mounted controller, and a man-machine interface is combined to assist a driver to control the tram. In addition, various track products are also configured with a master controller. However, the communication scheme of these controllers is still the LVDS communication scheme.

Disclosure of Invention

The application provides a safety controller, and this safety controller can arrange the fiber optic module in pairs, realizes gigabit ethernet optical fiber communication, replaces traditional LVDS communication scheme completely, has higher speed, stronger reliability, has solved imported LVDS buffer chip and has not corresponding domestic substituted problem.

The application provides a safety controller, which is of a two-out-of-two structure; the two-out-of-two structure comprises two mutually independent control modules;

each control module comprises a main processor, a coprocessor, a first Ethernet chip, a second Ethernet chip and a third Ethernet chip; the main processor comprises an integrated MAC, a PCIe interface, a LIO interface, a first RGMII interface and a second RGMII interface; the main processor is connected with the coprocessor through a PCIe interface and a LIO interface respectively;

the integrated MAC of the main processor is connected with the first Ethernet chip through the first RGMII interface; the coprocessor is connected with the second Ethernet chip through a parallel interface;

and the integrated MAC is connected with the third Ethernet chip through the second RGMII interface so as to realize the conversion between the RGMII interface and the FIBER interface.

In an exemplary embodiment, each control module further comprises an MLVDS bus module;

the MLVDS bus module is connected with the coprocessor.

In an exemplary embodiment, each control module further includes a Cfast memory card; the main processor further comprises a SATA interface;

and the main processor is connected with the Cfast storage card through a SATA interface.

In an exemplary embodiment, each control module further comprises an RTC chip; the main processor further comprises an I2C interface;

the main processor is connected with the RTC chip through an I2C interface;

the RTC chip is configured to provide a real-time clock to the main processor.

In an exemplary embodiment, each control module further comprises an NVSRAM chip; the main processor also comprises an SPI interface;

and the main processor is connected with the NVSRAM chip through the SPI.

In one exemplary embodiment, the main processor is a Loongson processor model 2K1000 i;

the coprocessor is a processor of the Beijing micro Qili company with the model number of P1P 060;

the second Ethernet chip is an Ethernet chip with the model of CBM1001A-Q of Bai Mi Corp;

the third Ethernet chip is an Ethernet PHY chip with model YT8521SH-CA, which is a Yutai vehicle passband optical port.

In an exemplary embodiment, the NVSRAM chip is a model MC90N04M0V33AH-IA NVSRAM chip of Shanghai Bowei logic semiconductor technology, inc.

In an exemplary embodiment, the RTC chip is a big common carrier built-in crystal type model INS5902B RTC chip.

In an exemplary embodiment, each control module further comprises a power module; the power supply module comprises a main processor power supply module and a coprocessor power supply module;

the main processor power supply module is arranged for converting an externally input 24V voltage into a voltage of a first voltage value set so as to meet the power supply requirement of each part of the main processor;

the coprocessor power supply module is arranged to convert an externally input 24V voltage into a voltage of a second voltage value set so as to meet the power supply requirement of each part of the coprocessor.

In an exemplary embodiment, each control module further comprises a reset module;

the reset module is used for carrying out under-voltage reset monitoring on all logic power supplies of the power supply module and monitoring the operation of the main processor so as to carry out forced reset on the safety controller after the voltage of any logic power supply is abnormal or the program of the main processor runs away.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application. Other advantages of the present application can be realized and attained by the instrumentalities and combinations particularly pointed out in the specification and the drawings.

Drawings

The accompanying drawings are included to provide an understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the examples serve to explain the principles of the disclosure and not to limit the disclosure.

Fig. 1 is a schematic diagram of a safety controller according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a logic structure of another safety controller according to an embodiment of the present application;

FIG. 3 is a schematic diagram of power distribution to another safety controller according to an embodiment of the present application;

FIG. 4 is a schematic diagram of the reset logic of another safety controller according to an embodiment of the present application;

FIG. 5 is a logic diagram of communication between existing track production lines according to an embodiment of the present application;

FIG. 6 is a logic block diagram illustrating communication between gigabit Ethernet systems of another security controller in accordance with an embodiment of the present application;

FIG. 7 is a diagram illustrating FIBER and RGMII conversion of another safety controller according to an embodiment of the present application;

FIG. 8 is a logic block diagram of a CBM1001A-Q Ethernet interface of another security controller according to an embodiment of the present application.

Detailed Description

Fig. 1 is a schematic diagram of a safety controller according to an embodiment of the present application, and as shown in fig. 1, the safety controller has a two-out-of-two structure; the two-out-of-two structure comprises two mutually independent control modules;

each control module comprises a main processor, a coprocessor, a first Ethernet chip, a second Ethernet chip and a third Ethernet chip; the main processor comprises an integrated MAC (Media access control), a PCIe (peripheral component interconnect express) Interface (PCIe Interface is a high-speed serial computer expansion bus standard), an LIO (Local input output) Interface, a first RGMII Interface (RGMII Interface: reduced Gigabit Media Independent Interface, a communication Interface between Ethernet MAC and PHY) and a second RGMII Interface; the main processor is connected with the coprocessor through a PCIe interface and a LIO interface respectively;

the integrated MAC of the main processor is connected with the first Ethernet chip through the first RGMII interface; the coprocessor is connected with the second Ethernet chip through a parallel interface;

the integrated MAC is connected with the third Ethernet chip through the second RGMII interface so as to realize the conversion between the RGMII interface and the FIBER interface.

In an exemplary embodiment, the first ethernet chip may be an ethernet chip of model YT 8511. The second ethernet chip may be a MAC + PHY chip of type CBM 1001A.

In an exemplary embodiment, each control module further comprises an MLVDS bus module;

the MLVDS bus module is connected with the coprocessor.

In an exemplary embodiment, each control module further includes a Cfast memory card; the main processor further comprises a SATA interface;

and the main processor is connected with the Cfast storage card through a SATA interface.

In an exemplary embodiment, each control module further comprises an RTC chip; the main processor further comprises an I2C interface;

the main processor is connected with the RTC chip through an I2C interface;

the RTC chip is configured to provide a real-time clock to the main processor.

In an exemplary embodiment, each control module further comprises an NVSRAM chip; the main processor also comprises an SPI interface;

and the main processor is connected with the NVSRAM chip through the SPI.

In one exemplary embodiment, the main processor is a Loongson processor model 2K1000 i;

the coprocessor is a processor of the Beijing micro Qili company with the model number of P1P 060;

the second Ethernet chip is an Ethernet chip with a core of Bai micro company and the model of CBM 1001A-Q;

the third Ethernet chip is an Ethernet PHY chip with model YT8521SH-CA, which is a Yutai vehicle passband optical port.

In an exemplary embodiment, the NVSRAM chip is a model MC90N04M0V33AH-IA NVSRAM chip of Shanghai Bowei logic semiconductor technology, inc.

In an exemplary embodiment, the RTC chip is a built-in crystal type model INS5902B RTC chip from Dakoku corporation.

In an exemplary embodiment, each control module further comprises a power module; the power supply module comprises a main processor power supply module and a coprocessor power supply module;

the main processor power supply module is arranged for converting an externally input 24V voltage into a voltage of a first voltage value set so as to meet the power supply requirement of each part of the main processor;

the coprocessor power supply module is arranged to convert an externally input 24V voltage into a voltage of a second voltage value set so as to meet the power supply requirement of each part of the coprocessor.

In an exemplary embodiment, each control module further comprises a reset module;

the reset module is configured to perform under-voltage reset monitoring on all logic power supplies of the power supply module and monitor the operation of the main processor, so as to perform forced reset on the system after the voltage of any logic power supply is abnormal or the program of the main processor is run away.

Fig. 2 is a schematic diagram of a logic structure of another safety controller according to an embodiment of the present application, where the safety controller is an autonomous controllable safety controller with a "two-out-of-two" architecture implemented by nationwide production components, and can be used as a main controller module of each track product through expansion of hardware resources and interfaces and adaptive development of platform application software.

The safety controller adopts a two-out-of-two architecture on the aspect of hardware design. The two-out-of-two architecture means that the module comprises two symmetrical channels (corresponding to the two control modules), and the output of the safety data needs to be judged by voting of the two channels and can be output in a consistent way; the input of the safety data needs to be judged through comparison of the two channels, and the safety data can be used in a consistent mode. Both channels are designed based on a CPU (corresponding to the above-mentioned main processor) + FPGA (Field Programmable Gate Array) (corresponding to the above-mentioned coprocessor) architecture, wherein the CPU chip adopts 2K1000I of loongson corporation as a main processor for processing various logic operations and controls (mainly controlling ethernet Interface, LIO Interface with FPGA, etc. Peripheral interfaces), the CPU includes dual cores, with a main frequency up to 800MHz, a peak operating speed of 8 gfops, supports 64-bit DDR3-1066 memories, and has 2 channels of pci 2.0, 2 channels of RGMII (Reduced Gigabit Media Interface, a communication Interface between ethernet MAC and PHY), gigabit Interface, SPI (Serial Peripheral Interface ), 12 channels of UART, UART o, 2 channels of I2C (Interface-Integrated bus, integrated Circuit), 2 channels of LIO, 4 channels of CAN 2.0, SATA, etc., and is suitable for GPIO, USB applications, and also has 4 channels of GPIO, and is suitable for many applications in addition, and is suitable for many transportation industries, such as GPIO, serial Peripheral Interface, GPIO, serial Interface, GPIO, serial Interface, and USB, GPIO, USB, and USB Interface, and also suitable for many applications; the FPGA chip adopts P1P060 of Beijing micro-Qili company P (flying horse) series as a coprocessor and is used for processing various communication interfaces, IO interfaces, storage and bus protocols (the communication interfaces and the IO interfaces need the FPGA to realize conversion logic and are used as logic processing interfaces between a CPU and peripheral equipment, the storage means that data sent or received by the communication interfaces needs to be cached in the FPGA, the bus protocol means that the specific realization of the LVDS communication protocol needs to be completed by the FPGA), the FPGA adopts a 40nm CMOS process, the logic capacity is close to 60K equivalent LUT4, a brand new LUT 6 architecture and a 32-path full clock network are used, the running speed can reach 700MHz, in addition, a high-speed Serdes interface, a hard core DDR2/3 controller and a hard core PCIe interface which can reach 6.5Gbps and 1333Mbps and a 36 × 18 DSP processor are integrated according to the application requirements of a high-speed large-capacity market, and the mainstream application of the rail transit industry can be sufficiently met.

The safety controller has the main functions as follows:

a safety watchdog driver (including a watchdog pulse signal output by a General-purpose input/output (GPIO) to realize a watchdog feeding function): when the CPUs of the two channels work normally, dynamic pulse signals are output to the safety watchdog, the safety watchdog is in an 'ON' state, and the communication interface outputs the dynamic pulse signals; if the dynamic pulse signal is stopped due to any CPU fault, the safety watchdog is in an OFF state, the communication interface stops outputting and leads to a safety side;

two channels in the two-out-of-two architecture realize data communication and synchronization between the two channels through an isolation capacitive coupling CA-IS3720HS, and the highest support rate IS as follows: 200Mbps;

2-way ethernet interfaces are integrated per channel: wherein, 1 route outside (referring to the outside of CPU or FPGA, belonging to the inside of controller) MAC + PHY chip CBM1001A is connected to FPGA through parallel interface to realize, speed: 10M/100M configurable; 1 routing external PHY (Physical Layer) chip YT8511 is connected to the integrated MAC of the CPU via an RGMII Interface (i.e., reduced Gigabit Media Independent Interface), and the rate: 10M/100M/1000M configurable;

each channel integrates 1-channel gigabit ethernet RGMII < - > FIBER (RGMII < - > FIBER means the interconversion between RGMII interface and FIBER interface, FIBER interface means FIBER interface, specifically Serdes (SERializer/DESerializer)) differential interface signal interface capable of being directly connected with FIBER module in matching manner): the CPU integrated MAC is connected with an external PHY chip YT8521 through an RGMII interface, is converted into a high-speed kilomega differential Serdes signal to be output, realizes RGMII < - > FIBER interface conversion, and is led out to a photoelectric conversion module, so that photoelectric signal conversion is realized, and the aim of high-speed and reliable signal transmission is fulfilled;

each channel supports 4-channel serial high-speed MLVDS (Multi-Drop LVDS, multi-point LVDS) bus communication, TPT9H221L1-SO1R-S is selected for realization, and the highest rate support is as follows: 200Mbps (megabit per second), a complete system can be constructed by communicating with other modules through the MLVDS bus;

each channel is integrated with a built-in crystal type high-precision RTC (Real Time Clock), the Real Time Clock is realized by adopting an RTC chip INS5902B of a large common carrier company, the resolution reaches 62.5ms, an I2C interface is connected to a CPU (central processing unit) to provide a Time reference for a system, and the RTC is provided with a replaceable battery and keeps Time running after power failure;

each channel supports large-capacity storage and supports a MicroSD card, the capacity is not less than 8GB, and a 4-bit SDIO bus is connected with a standard SDIO interface of a CPU and used for storing large-data-volume information; the system supports a CFast card, has the capacity not less than 8GB, is connected with a standard SATA interface of a CPU by an SATA bus and is used for storing large-data-volume information;

each channel supports the functions of quick power failure and nonvolatile storage of fault information and key information, and is realized by adopting an MC90N04M0V33AH-IA NvSRAM chip with the capacity of 4Mbits.

The power supply system is designed as follows:

the power supply system is an important component of the system as a source of system energy. The input power supply of the application adopts the DC24V +/-10% of the industrial standard, and the logic power supply on the module has various types and specific needs: 24V, 5V, 3.3V, 2.5V, 1.5V, 1.2V, 1.15V, 1.1V, 0.9V, 0.75V and the like. In order to guarantee reliability and safety, and in consideration of the actual conditions that domestic CPU and FPGA chips have large power consumption and power chip has small power density, a power supply system is divided reasonably, the power supply system of each channel is divided into a CPU related circuit power supply and an FPGA related circuit power supply, a 24V main power supply has protection such as undervoltage, overvoltage, overcurrent and overheating, the module is not damaged under the condition that an input power supply is abnormal, and undervoltage monitoring is carried out on all other logic power supplies.

Fig. 3 is a power distribution diagram.

The specific implementation scheme is as follows:

the power supply is 24V input, and is respectively input to the CPU and the FPGA main power module SYA18303FCA through a SY6885BQDC power protection circuit and then is subjected to voltage reduction to be respective 5V main power supplies.

The CPU 5V main power supply supplies power to the USB interface after being controlled by a load switch SY6281AAAC current-limiting protection; the RTC part of the CPU is supplied with power after the voltage is divided into 2.5V by a resistor; 5V to 1.15V is realized through SY8816DFC, and power is supplied to a CPU core power supply; a 0.75V reference power supply and a terminal matching power supply of DDR3 are realized through SY6355 DBC; other low-voltage power supply conversion is realized through SY98003 AQNC: 1.1V, 1.5V and 3.3V, wherein 1.1V divides 2, 1 supplies power for the RSM field of CPU, 1 PCIE/SATA, PLL that give CPU supplies power, 1.5V supplies power for the DDR3 IO power and DDR3 chip of CPU, 3.3V also divides 2, 1 supplies power for the RSM field IO power of CPU, 1 supplies power for the SOC field IO power of CPU.

The FPGA 5V main power supply realizes low-voltage power supply conversion through SY98003 AQNC: 0.9V, 1.2V, 2.5V and 3.3V.0.9V is used for supplying power for an FPGA kernel and Serdes/PCIe; 1.2V for Serdes/PCIe power; 2.5V for Serdes/PCIe power; 3.3V is used for JTAG/PLL/ADC/IO power supply.

The power-on time sequence of each power supply of the CPU is designed as follows:

5V→2.5V→1.1V_RSM→3.3V_RSM→3.3V_CPU→1.5V→0.75V→1.1V_P→1.15V。

the power-on time sequence design of each power supply of the FPGA comprises the following steps:

5V→0.9V→3.3V→1.2V→2.5V。

the reset logic is designed as follows:

the reset logic is used for providing an initial operation condition for the module, and ensuring that the module is in a known state under an abnormal condition is the key for ensuring the normal operation of the module. This application has strengthened reset system for guaranteeing reliability and security, has carried out the undervoltage control that resets to all logic power to realize soft watchdog through FPGA, monitor CPU's operation, guarantee to force the system to reset after any logic voltage is unusual or the CPU procedure runs away, ensure the safety of system.

Fig. 4 is a reset logic diagram.

The specific implementation scheme is as follows:

the SGM706 monitoring chip realizes the functions of manual reset and 24V undervoltage monitoring, the monitoring of all other onboard logic power supplies is realized through PG output signals of respective power supply chips, various reset signals are realized through logic combination of a logic AND chip SGM7SZ08, and the system reset can be triggered when any voltage drops out of a threshold value.

The voltage monitoring result and the manual reset signal of the relevant part of the CPU generate a \ CPU _ PWRMON reset signal after being subjected to AND logic, the voltage monitoring result and the \ FPGA _ CFGDONE signal of the relevant part of the FPGA generate a \ FPGA _ MON reset signal after being subjected to AND logic, the \ CPU _ PWRMON reset signal and the \ FPGA _ MON reset signal generate a \ CPU _ FPGA _ MON reset signal after being subjected to AND logic, and the signals are directly used as global logic reset signals of the FPGA and used for resetting the internal overall logic of the FPGA; after the logic output of the CPU _ FPGA _ MON reset signal and the logic output of the soft watchdog in the FPGA, the FPGA _ WD signal generates a CPU _ SYS _ RST reset signal for the reset input of a CPU system; in addition, the relative power supply monitoring result of the RSM domain of the CPU generates a \ CPU _ RSMRST signal after passing through AND logic, and the signal is used for resetting the logic part of the RSM domain of the CPU.

The high speed, mass storage memory is designed as follows:

high-speed, large-capacity data storage is realized by the CFast card device. The CFast card adopts GLS91CA008G1-I-BN600 of green core company, has the capacity of 8GB (the capacity can be expanded to 169B, 32GB or higher capacity according to the requirement), an SATA interface and high speed (supporting 1.5Gbps, 3Gbps or 6 Gbps), is matched with the SATA interface of the Loongson CPU for use, adopts a special CFast card connector, and can be very conveniently inserted and taken out.

The high-speed and high-reliability communication interface is designed as follows:

the DS15BA101 LVDS buffer is mainly used in a main controller product of a rail ground device at present, and is used for buffering LVDS in inter-train communication, increasing driving capability, and changing differential level.

In order to realize high-speed (200 Mbps) and strong anti-interference communication, an LVDS signal-to-optical fiber transmission mode is adopted for communication between main controllers of existing track products, an FPGA outputs a differential LVDS signal, the DS15BA101 passing through TI is used as an LVDS buffer, the LVDS differential signal with the differential voltage amplitude of 800mV is output, an electrical interface of an optical fiber module AFBR-5710ALZ of Fuji kang foxconn company is accessed, the LVDS electrical signal is converted into an optical signal, the optical signal is accessed to an LC interface of an optical fiber module of another system from the LC interface through optical fibers, the optical signal is converted into an electrical signal, the electrical signal is output to the LVDS buffer from the LVDS electrical interface and then to the FPGA, and the whole communication link is realized.

Fig. 5 is a logic diagram of communication between master controllers of an existing track product.

Because there is not at present the domestic brand model LVDS buffer that corresponds to the alternative, this application has proposed and has adopted the gigabit Ethernet optical fiber communication mode to replace the solution of current LVDS optical fiber communication mode, and this technical scheme technology is mature, and has higher rate (1000 Mbps), can satisfy the demand completely.

Fig. 6 is a logic diagram of communication between gigabit ethernet systems.

An Ethernet PHY chip YT8521SH-CA with an optical port of Yutai Tong (MotorComm) is selected to realize the function of an inter-system communication circuit, and the chip can realize the function of FIBER < - > RGMII.

FIG. 7 is a diagram of FIBER < - > RGMII.

The CPU is used as MAC, and is in communication connection with the YT8521 PHY chip through an RGMII interface, the YT8521 is connected with the optical fiber module through a SerDes interface, and then is in communication connection with the optical fiber module of another system through optical fibers, so that the function of communication between systems is realized, the communication speed reaches 1000Mbps, the electrical isolation between the systems is realized, and the high-speed and high-reliability optical fiber module has the characteristics of high speed and high reliability.

The fiber optic transceiver may be implemented using IGSFP-M-SX-LC-850-0.55-DDM available from Toyobo, a domestic brand, or GTLS-8512-02-DIU available from Shanghai optical corporation.

The gigabit Ethernet optical fiber communication scheme not only fundamentally realizes autonomous control, but also technically completely replaces the existing imported LVDS bus scheme, and the debugging result of a prototype developed by the application shows that when the scheme is used for the synchronization among master controllers, the synchronization precision of the IEEE1588 protocol is adopted to meet the requirement of 10us precision specification, and the scheme is slightly superior to the existing LVDS bus synchronization scheme.

The extended ethernet interface is designed as follows:

the security controller integrates two Ethernet interfaces per channel, implemented using YT8511 Ethernet PHY and CBM1001A Ethernet MAC + PHY, YT8511 is configurable to 1000M or 100M rate mode, CBM1001A is configurable only up to 100M rate mode.

And the YT8511 network port is connected to the CPU by using an independent RGMII interface, and the configuration of the network port PHY chip is realized by an SMI interface MDC/MDIO. Because the number of RGMII interfaces of the CPU is limited in general, the CPU selected by the application only comprises 2 RGMII interfaces, and sometimes the requirement of practical application cannot be met.

Based on this, this application has proposed the ethernet interface circuit who adopts the core to herbori little company CBM1001A-Q chip to realize, this chip belongs to MAC + PHY chip, through 8bits or 16bits parallel interface connection to FPGA, CPU controls CBM1001A-Q through FPGA, so, can use FPGA cooperation CBM1001A-Q chip to expand the net gape quantity according to the demand, greatly improved the application flexibility.

The reset of the CBM1001A-Q network port MAC + PHY chip is realized by FPGA IO output, thereby realizing the function of actively resetting the MAC + PHY chip by the FPGA.

FIG. 8 is a logic block diagram of a CBM1001A-Q Ethernet interface.

The fast, non-volatile memory design is as follows:

the traditional EEPROM and Flash as memory chips have obvious defects:

the writing speed is slow, and the requirements of high-speed writing of storage fault information and key data in a real-time processing system cannot be met;

the writing frequency is limited, and the requirement of high-frequency data storage cannot be met;

under the condition of sudden power failure, the real-time storage of fault information and key data cannot be ensured.

In such a case, a nonvolatile RAM having a power-down protection function and capable of high-speed reading and writing and having a sufficient number of reading and writing times must be used.

The NVRAM is one of the NVRAMs, the NVRAMs commonly used in the current market comprise the NVRAMs, FRAM, BBSRAM and MRAM, wherein the NVSRAM is high in read-write speed and can read and write infinitely, the NVRAMs are superior to the FRAM in speed, the power consumption and the anti-interference performance are superior to the MRAM, the power consumption and the speed are equivalent to those of the BBSRAM, a battery does not need to be configured, foreign FRAM chips are mostly adopted in the past, the cost is high, and the purchasability is poor. The factory index of NVRAM can be made at home, an NVSRAM chip MC90N04M0V33AH-IA of Shanghai Bowei logic semiconductor technology Limited is selected, the chip is an SPI interface, 2.85V-3.6V voltage is supplied, 133MHz clock frequency is supported, the capacity reaches 4Mbits, each storage unit in the memory is provided with 1 nonvolatile storage unit, and two working modes are provided: an SRAM mode in which various read and write operations are performed like a static random access memory; in the non-volatile mode, data is stored from the SRAM into the non-volatile cell (STORE operation) or from the non-volatile cell into the SRAM (RECALL operation), and after power up, if at least one write operation occurs, the STORE operation will be automatically initiated when the supply voltage drops below a threshold when power is lost. After power-on, when the input voltage exceeds the threshold voltage, RECALL operation is automatically initiated. In addition, the STORE operation and the RECALL operation can be actively initiated through the SPI interface.

The MC90N04M0V33AH-IA is very suitable for the application that the data needs to be repeatedly stored at a high speed or a high frequency, and the data needs to be retained after power failure, and can also be applied to a rapid configuration system, thereby being beneficial to rapid start and rapid recovery of the system. The method has great advantages in speed and power consumption, can well replace imported FRAM chips, reduces product cost and improves material availability.

The high-resolution RTC circuit is realized by adopting a built-in crystal type RTC chip INS5902B of a general communication company, the resolution reaches 62.5ms, and the IIC interface is connected to a CPU (central processing unit) to provide a real-time clock function, so that the requirement of a high-resolution application scene can be met. The RTC backup battery is provided by an ER14250 battery of 1200 mAh/3.6V. The battery can maintain 1200 x 1000/0.7=1714286h, calculated as the typical backup current consumption of INS5902B, 0.7uA, for about 71428 days, about 195 years.

The embodiment of the application has the following advantages:

1) Completely autonomous and controllable: the application adopts nationwide production devices to realize a safety controller with a two-out-of-two architecture, and truly realizes complete autonomous control;

2) With high-speed mass storage: the method adopts the mode that the high-speed SATA interface of the CPU expands the CFast card, can provide higher storage speed than the traditional MicroSD card and CF card, and has equivalent capacity;

3) The RGMII conversion is realized by externally expanding an Ethernet PHY chip YT8521 through an RGMII interface of a CPU, the gigabit Ethernet optical FIBER communication can be realized by matching an optical FIBER module, a high-speed and reliable communication channel is provided, the traditional LVDS communication scheme can be completely replaced, the high-speed and reliable communication channel has higher speed and reliability, and the problem that an imported LVDS buffer chip does not have corresponding domestic replacement is solved;

4) With ethernet controller interface: by means of the FPGA external expansion Ethernet MAC + PHY chip CBM1001A, expansion of an Ethernet interface is flexibly achieved, the problem that a CPU is limited by an RGMII interface is solved, and a solution is provided for multi-port expansion application;

5) Fast, non-volatile storage media with failure information and critical information: the completely autonomous NVSRAM chip is used as a storage medium, so that the nonvolatile NVSRAM has the characteristics of non-volatility and unlimited fast reading and reading times;

6) High-precision RTC with built-in crystal: the method is realized by adopting an RTC chip INS5902B of a large common carrier company, the resolution reaches 62.5ms, an I2C interface is connected to a CPU to provide a time reference for a system, and the RTC is provided with a replaceable battery and keeps running in time after power failure.

The present application describes embodiments, but the description is illustrative rather than limiting and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or instead of any other feature or element in any other embodiment, unless expressly limited otherwise.

Any features shown and/or discussed in this application may be implemented separately or in any suitable combination.

Further, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other sequences of steps are possible as will be appreciated by those of ordinary skill in the art.

It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, or suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.

Claims (10)

1. A safety controller is characterized in that,

the safety controller is of a two-out-of-two structure; the two-out-of-two structure comprises two mutually independent control modules;

each control module comprises a main processor, a coprocessor, a first Ethernet chip, a second Ethernet chip and a third Ethernet chip; the main processor comprises an integrated MAC, a PCIe interface, a LIO interface, a first RGMII interface and a second RGMII interface; the main processor is connected with the coprocessor through a PCIe interface and a LIO interface respectively;

the integrated MAC of the main processor is connected with the first Ethernet chip through the first RGMII interface; the coprocessor is connected with the second Ethernet chip through a parallel interface;

and the integrated MAC is connected with the third Ethernet chip through the second RGMII interface so as to realize the conversion between the RGMII interface and the FIBER interface.

2. The security controller of claim 1, wherein each control module further comprises an MLVDS bus module;

the MLVDS bus module is connected with the coprocessor.

3. The security controller of claim 1, wherein each control module further comprises a Cfast memory card; the main processor further comprises a SATA interface;

and the main processor is connected with the Cfast storage card through a SATA interface.

4. The security controller of claim 1, wherein each control module further comprises an RTC chip; the main processor further comprises an I2C interface;

the main processor is connected with the RTC chip through an I2C interface;

the RTC chip is configured to provide a real-time clock to the main processor.

5. The security controller of claim 1, wherein each control module further comprises an NVSRAM chip; the main processor also comprises an SPI interface;

and the main processor is connected with the NVSRAM chip through the SPI.

6. The safety controller of claim 1,

the main processor is a processor of Loongson company, the model of which is 2K1000 i;

the coprocessor is a processor of the Beijing micro Qili company with the model number of P1P 060;

the second Ethernet chip is an Ethernet chip with a core of Bai micro company and the model of CBM 1001A-Q;

the third Ethernet chip is an Ethernet PHY chip with model YT8521SH-CA, which is a Yutai vehicle passband optical port.

7. The safety controller of claim 5,

the NVSRAM chip is an NVSRAM chip of Shanghai Bowei logic semiconductor technology, inc. with the model number of MC90N04M0V33 AH-IA.

8. The safety controller of claim 4,

the RTC chip is a built-in crystal type RTC chip of a large common carrier company, and the model of the built-in crystal type RTC chip is INS 5902B.

9. The safety controller of claim 1, wherein each control module further comprises a power module; the power supply module comprises a main processor power supply module and a coprocessor power supply module;

the main processor power supply module is arranged for converting an externally input 24V voltage into a voltage of a first voltage value set so as to meet the power supply requirement of each part of the main processor;

the coprocessor power supply module is arranged to convert an externally input 24V voltage into a voltage of a second voltage value set so as to meet the power supply requirement of each part of the coprocessor.

10. The safety controller of claim 9, wherein each control module further comprises a reset module;

the reset module is configured to perform under-voltage reset monitoring on all logic power supplies of the power supply module and monitor the operation of the main processor, so as to forcibly reset the safety controller after the voltage of any logic power supply is abnormal or the program of the main processor is run away.

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