CN218850746U

CN218850746U - Trigger circuit applied to FID and FID pulse generation circuit

Info

Publication number: CN218850746U
Application number: CN202223023025.2U
Authority: CN
Inventors: 温凯俊; 项卫光
Original assignee: Wuhan Pulse Core Electronic Technology Co ltd
Current assignee: Wuhan Pulse Core Electronic Technology Co ltd
Priority date: 2022-11-11
Filing date: 2022-11-11
Publication date: 2023-04-11
Anticipated expiration: 2032-11-11

Abstract

The utility model discloses a be applied to FID's trigger circuit and FID pulse and produce circuit, including main through-flow circuit and trigger circuit, connect FID and through-flow diode in the main through-flow circuit, parallelly connected voltage stabilizing capacitor on the branch road of FID and through-flow diode polyphone. The trigger circuit comprises an RC trigger circuit and an ABJT-based cascade circuit, the RC trigger circuit is used for triggering a first-stage ABJT in the cascade circuit, the ABJT is conducted step by step subsequently to enable capacitors charged in parallel to be in series discharge, and nanosecond-level kV-level high-voltage pulses are generated on a last-stage load; the high-voltage pulse acts on two ends of the FID, so that the voltages at the two ends of the FID are overshot, the FID generates a rapid ionization effect, and then the parallel voltage-stabilizing capacitor discharges the FID, so that the FID is switched on in a sub-nanosecond transient state and flows a large current. The utility model discloses well do not use magnetic saturation transformer and magnetic switch, avoided the unstable influence of magnetic saturation device, can increase substantially FID's the stability of triggering, guarantee that FID accurate triggering under the conventional withstand voltage condition opens.

Description

Trigger circuit applied to FID and FID pulse generation circuit

Technical Field

The utility model belongs to the pulse power circuit field, more specifically relates to a trigger circuit and FID pulse generation circuit who is applied to FID (Fast Ionization Dynistor).

Background

The pulse power technology is widely applied to the fields of national defense, scientific research, industry, medical treatment, environmental protection and the like, and the pulse power technology is deeply researched in Russian, american, japanese and other countries in recent decades. Part of the pulse power technology is developed due to the need of national defense, and the application of the pulse power technology in national defense and military comprises the following steps: rail guns, electromagnetic stealth technology, ground penetrating radar, impact radar, electromagnetic countermeasure, and the like. After the cold war is finished, the pulse power technology has continuous large-area innovative development in the aspects of environmental protection, biology, medical treatment, new materials, industry and the like.

The pulse power technology has extreme characteristic requirements on a pulse power system, and a fast pulse technology with a steep rising front and a narrow pulse width is required. The pulse power switch is the bottleneck of the whole system, and the development of an ideal switch is always the subject of the development of a compact fast leading edge pulse power system. Pulsed power switches mainly include gaseous switches and solid state switches. The power semiconductor device has remarkable progress in power capability, working speed and the like, and gradually becomes the development direction of the pulse power switch due to the advantages of small volume, long service life, high reliability and the like.

Among these, the fast ionization device FID is a semiconductor device specifically proposed and designed for pulsed power applications. The FID device is an open circuit type semiconductor switch proposed by russian related researchers, and has only two electrodes: an anode and a cathode. The working principle is as follows, firstly, applying a positive stable voltage on two ends of an FID device, enabling the FID to be in a critical avalanche state, then discharging by using a capacitor connected in parallel on two ends of the FID device, enabling the voltage on two ends of the FID device to be overshot, when the voltage on two ends of the FID device exceeds 2-3 times of critical avalanche breakdown voltage, enabling an electric field inside the FID device to far exceed the critical avalanche breakdown electric field, injecting cathode holes into the overshooting electric field, causing violent impact ionization, generating a large number of electron hole pairs, enabling the electric field to be sharply reduced due to the generation of the electron hole pairs, diffusing the electron hole pairs to two sides to form an impact ionization wave phenomenon of the electric field, and enabling the FID to be triggered to be turned on within nanosecond and sub-nanosecond time, then discharging the FID by a voltage stabilizing capacitor, enabling the device to flow large current, generating voltage pulses with nanosecond and sub-nanosecond leading edges on a load, and enabling the maximum rising rate to reach kV/ns.

FIG. 1 shows a conventional FID pulse generation circuit of the prior art, which uses the pulse generation circuit of DSRD as a trigger circuit, wherein a magnetic saturation transformer and a primary capacitor C are arranged in the trigger circuit part ₁ The U1 is used for charging and discharging the capacitor C ₂ And voltage-stabilizing capacitor C ₀ Charged by U0. When the trigger is started, the triode Q is firstly triggered to be conducted, so that the primary capacitor C1 is led to be along C ₁ -Q-Tr-L-C ₁ And discharging is performed. At this time, the primary capacitor C is driven by the magnetic saturation transformer Tr ₁ Current transformation output and flowing through Tr and to trigger capacitor C _s And charging, wherein the charging loop at the moment is Tr-Cs-DSRD, and the DSRD is conducted. When pair trigger capacitor C _s After charging to a certain degree, the transformer Tr is saturated, and at the moment, the trigger capacitor C _s Discharging with a discharge loop of C _s -Tr-DSRD, when the DSRD is conducted with reverse current, so that the DSRD is turned off in nanosecond time, and the current loop is converted to Cs-Tr-C ₂ FID, the two ends of the FID device are subjected to high-voltage electric pulses of ns and kV, so that the FID is conducted in nanosecond and subnanosecond time, wherein LS avoids triggering a capacitor C _s And a discharge capacitor C ₂ When the series discharge is carried out, the load branch circuit is circulated, and the function of isolating discharge current is realized. When FID is conducted, LS just saturates, and the voltage-stabilizing capacitor C ₀ The FID starts to be discharged, and a large current flows. The conventional FID pulse generation circuit in FIG. 1 employs a magnetic saturation transformer and a magnetic switch, and has a certain effect on the circuitLoud and not conducive to integration.

As shown in FIG. 1, the conventional FID trigger on/off circuit is a pulse generating circuit of a Drift Step Recovery Diode (DSRD) as a trigger circuit, wherein a magnetic saturation transformer is disposed in a trigger circuit part, and a primary capacitor C ₁ After discharging, the discharge passes through a magnetic saturation transformer to trigger a capacitor C _s During charging, after the transformer is saturated magnetically, the trigger capacitor C triggers _s Along the transformer loop and the discharge capacitor C ₂ In series to discharge the FID, a magnetic switch is provided in the discharge loop portion, which magnetic switch prevents triggering of the capacitor C _s And a discharge capacitor C ₂ And the current flows through the load branch circuit when the series discharge is performed. In the practical application process, the magnetic switch and the magnetic saturation transformer have the defects of large volume, difficulty in integration, difficulty in control and the like, so that the integration of the pulse circuit is ensured while the volume of the pulse circuit based on the FID is reduced, the triggering stability of the FID is improved, and the magnetic switch is prevented from being used as an effective method.

Disclosure of Invention

To prior art's defect, the utility model aims to provide a be applied to trigger circuit of quick ionization device FID aims at solving the bulky, difficult integrated and the unstable problem of operation that conventional FID pulse generation circuit caused because of the magnetic switch.

The utility model provides a trigger circuit applied to FID, which comprises a first trigger module and a second trigger module, wherein the input end of the second trigger module is connected to the output end of the first trigger module, and the output end of the second trigger module is used for connecting an external main current circuit; the second trigger module is a cascade circuit comprising a plurality of levels ABJT; the first trigger module is used for triggering a first-stage ABJT in the cascade circuit, and the ABJT is conducted step by step subsequently, so that capacitors charged in parallel in the cascade circuit are serially connected and discharged, and nanosecond-level kV-level high-voltage pulses are generated on a last-stage load.

Still further, the first triggering module includes: and the capacitor C10 and the resistor R10 are sequentially connected in series between the 0-15V square wave voltage trigger small signal end and the ground, and the series connection end of the capacitor C10 and the resistor R10 is used as the output end of the first trigger module.

Furthermore, the cascade circuit of multiple stages of ABJT comprises a first stage circuit, a second stage circuit … … and an nth stage circuit; the input end of the first-stage circuit is used as the input end of the second trigger module, the output end of the nth-stage circuit is used as the output end of the second trigger module, the input end of the second-stage circuit is connected to the output end of the first-stage circuit, and the input end of the … … nth-stage circuit is connected to the output end of the (n-1) th-stage circuit.

Wherein, first stage circuit includes: ABJT1, a pulse load resistor Rs1, a pulse discharge capacitor C11 and a current limiting resistor Rx1; the control end of the ABJT1 is used as the input end of the first-stage circuit, the input end of the ABJT1 is connected to the anode of an external direct-current voltage source DC1 through a current-limiting resistor Rx1, the output end of the ABJT1 is grounded, and a pulse discharge capacitor C11 and a pulse load resistor Rs1 are sequentially connected between the input end of the ABJT1 and the ground in series; the serial connection end of the pulse discharge capacitor C11 and the pulse load resistor Rs1 is used as the output end of the first-stage circuit;

the second stage circuit includes: ABJT2, a pulse load resistor Rs2, a pulse discharge capacitor C12 and a current limiting resistor Rx2; the control end and the output end of the ABJT2 in the second-stage circuit are used as the input end of the second-stage circuit, the input end of the ABJT2 is connected to the anode of an external direct-current voltage source DC1 through a current-limiting resistor Rx2, and a pulse discharge capacitor C12 and a pulse load resistor Rs2 are sequentially connected between the input end of the ABJT2 and the ground in series; the serial connection end of the pulse discharge capacitor C12 and the pulse load resistor Rs2 is used as the output end of the second-stage circuit;

the nth stage circuit includes: ABJTn, a pulse load resistor RL, a pulse discharge capacitor C1n and a current limiting resistor Rxn; the control end and the output end of the ABJTn in the nth-stage circuit are both used as the input end of the nth-stage circuit, the input end of the ABJTn is connected to the positive electrode of the direct-current voltage source DC1 through a current-limiting resistor Rxn, one end of a pulse discharge capacitor C1n is connected to the input end of the ABJTn, the other end of the pulse discharge capacitor C1n is connected to one end of a load resistor RL, and the other end of the load resistor RL, which is used as the output end of the nth-stage circuit, is also used as the output end of the second trigger circuit.

The utility model also provides a FID pulse generation circuit, including trigger circuit and mainstream circulation circuit, trigger circuit includes first trigger module and second trigger module, and the input of second trigger module is connected to the output of first trigger module, and the output of second trigger module is connected mainstream circulation circuit; the second trigger module is a cascade circuit comprising a plurality of levels ABJT; the first trigger module is used for triggering a first-stage ABJT in the cascade circuit, and then the ABJT is conducted step by step, so that capacitors charged in parallel in the cascade circuit are serially connected and discharged, and nanosecond-level kV-level high-voltage pulses are generated on a last-stage load; the high-voltage pulse is applied to two ends of an FID in a main current circuit, so that voltages at two ends of the FID are over-regulated, the FID generates a rapid ionization effect, and then a voltage stabilizing capacitor is connected in parallel to discharge the FID, so that the FID is switched on in a sub-nanosecond transient state and a large current flows.

Still further, the first triggering module includes: and the capacitor C10 and the resistor R10 are sequentially connected between the 0-15V square wave voltage trigger small signal end and the ground in series, and the serial connection end of the capacitor C10 and the resistor R10 is used as the output end of the first trigger module.

the second stage circuit includes: ABJT2, a pulse load resistor Rs2, a pulse discharge capacitor C12 and a current limiting resistor Rx2; the control end and the output end of the ABJT2 in the second-stage circuit are both used as the input end of the second-stage circuit, the input end of the ABJT2 is connected to the anode of an external direct-current voltage source DC1 through a current-limiting resistor Rx2, and a pulse discharge capacitor C12 and a pulse load resistor Rs2 are sequentially connected between the input end of the ABJT2 and the ground in series; the serial connection end of the pulse discharge capacitor C12 and the pulse load resistor Rs2 is used as the output end of the second-stage circuit;

Still further, the main flow circuit includes: the device comprises a rapid ionization device FID, a pulse load resistor Rsn, a through-current diode D1, a current-limiting resistor Rf and a voltage-stabilizing capacitor C21; the anode of the rapid ionization device FID is connected with one end of the current-limiting resistor Rf, the other end of the current-limiting resistor Rf is connected with the anode of the high-voltage power supply DC2, and the cathode of the rapid ionization device FID is grounded through the pulse load resistor Rsn; the negative electrode of the high-voltage power supply DC2 is grounded; one end of the voltage-stabilizing capacitor C21 is connected to the anode of the rapid ionization device FID, and the other end of the voltage-stabilizing capacitor C21 is grounded; the anode of the through-flow diode D1 is connected to the cathode of the fast ionization device FID, and the cathode of the through-flow diode D1 is grounded.

Through the utility model discloses above technical scheme conceived, compare with prior art, the utility model discloses in by the trigger circuit based on ABJT's cascade circuit as the FID pulse produces the circuit, thereby can provide the required trigger voltage pulse value of FID of different specifications through the progression of dynamic adjustment cascade circuit, this trigger circuit is controlled by small-signal RC trigger circuit. In the whole cascade circuit, capacitors C (1-n) at all levels are firstly charged in parallel and then are conducted step by ABJT, and then series discharge is carried out, so that ns and kV high-voltage electric pulses are generated on a pulse load resistor Rsn, voltages at two ends of an FID device are over-regulated, the FID device is conducted in nanoseconds and subnanoseconds, and a voltage stabilizing capacitor C discharges through the FID and a through-flow diode D1 and flows through large current. The whole FID pulse generating circuit avoids the use of a magnetic saturation transformer and a magnetic switch, thereby eliminating the unstable influence of the magnetic saturation transformer and the magnetic switch and solving the demagnetization problem of the FID trigger circuit. Furthermore, the ABJT based cascaded circuit is small enough in overall size to make the FID pulse generating circuit advantageous for integration.

Drawings

FIG. 1 is a prior art conventional FID pulse generation circuit diagram;

FIG. 2 is a schematic block diagram of an FID pulse generation circuit provided by the present invention;

fig. 3 is a specific circuit diagram of the FID pulse generating circuit provided by the present invention.

The physical meanings of the symbols in fig. 1 are as follows: direct voltage sources U1, U0; current limiting resistors R1, R2; primary capacitance C ₁ (ii) a An integrated inductor L; a magnetic saturation transformer Tr; charging capacitor C _s (ii) a A drift step recovery diode DSRD; fast ionization device FID; discharge capacitor C ₂ (ii) a Voltage-stabilizing capacitor C ₀ (ii) a A magnetic switch LS; a load resistor R0.

The physical meanings of the symbols in fig. 3 are respectively: direct voltage sources DC1, DC2; current limiting resistors Rx (1 to n), rf; pulse load resistance Rs (1-n); a small signal capacitor C10; a small signal resistor R10; avalanche transistors ABJT (1 to n); a pulse discharge capacitor C1 (1-n); a load resistance RL; a fast ionization device FID; a current-passing diode D1; and a voltage stabilizing capacitor C21.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

The utility model provides a be applied to quick ionization device FID's trigger circuit and FID pulse generation circuit, can solve that conventional FID pulse generation circuit causes bulky, difficult integration and operation unstability scheduling problem because of the magnetic switch, the utility model discloses used the cascaded circuit based on ABJT (Avalanche Bipolar Junction Transistor, avalanche Transistor) as FID's trigger circuit, the fine FID trigger circuit that has solved of this circuit removes magnetized problem.

Specifically, the utility model discloses to be applied to FID's trigger circuit as the trigger circuit end based on the cascade circuit of ABJT, the cascade circuit based on ABJT can produce ns, the high-voltage pulse characteristic of kV level, the conventional FID trigger circuit of substitution that can be fine. Cascade circuit based on ABJT compares with conventional FID trigger circuit as FID trigger circuit, the utility model discloses can avoid the unstable influence of magnetic saturation device, improve FID's trigger stability, and do not have the FID pulse generation circuit behind the magnetic switch and do benefit to miniaturized integration.

The avalanche transistor ABJT is used as a novel ultra-high-speed and fast-leading-edge semiconductor pulse power device applied to ns-level and ps-level pulse power systems, and integrates the following important advantages: ABJT has a very fast rise time, which can provide very high switching speeds, and can produce high peak power pulses with rising edges on the order of sub-ns and even ps. ABJT is an ideal semiconductor switching device for use in ultra-high-speed pulse power systems, and is often used as a switching device for generating ultra-high-speed, high-power, narrow pulses. In addition, the cascade circuit based on the ABJT does not need to trigger and turn on the ABJT repeatedly on each stage, only needs to trigger the ABJT on the first stage, and the follow-up ABJT can break down and turn on the overvoltage of the cascade circuit due to the voltage overshoot of the two ends of the collector electrode and the emitter electrode. Because the overall size of the ABJT device is small, the cascade circuit formed by the ABJT is good in integration, easy to trigger and control and free from the influence of a magnetic saturation device, the trigger stability can be improved by using the ABJT device as a trigger circuit of the FID, and the overall size of the circuit is reduced.

The utility model provides a FID pulse produces circuit includes main through-flow circuit and trigger circuit, has connect quick ionization device FID and through-flow diode in the main through-flow circuit, connects voltage stabilizing capacitor in parallel on the branch road of quick ionization device FID and through-flow diode polyphone. The trigger circuit mainly comprises a small-signal RC trigger circuit and a cascade circuit based on avalanche transistors ABJT, wherein the small-signal RC trigger circuit is used for triggering first-stage ABJT in the cascade circuit, the ABJT is conducted step by step subsequently, so that capacitors charged in parallel in the cascade circuit are serially connected and discharged, and nanosecond-level kV-level high-voltage pulses are generated on a last-stage load.

The high-voltage pulse is applied to two ends of an FID in a main current circuit, so that voltages at two ends of the FID are over-regulated, the FID generates a rapid ionization effect, and then a voltage stabilizing capacitor is connected in parallel to discharge the FID, so that the FID is switched on in a sub-nanosecond transient state and a large current flows. Compared with the conventional FID trigger circuit, the trigger circuit does not use a magnetic saturation transformer and a magnetic switch, avoids the unstable influence of a magnetic saturation device, can greatly improve the trigger stability of the FID, and is favorable for the integrated utilization of the FID pulse generation circuit.

The utility model discloses in, the cascade circuit based on ABJT is as the trigger circuit of FID pulse generation circuit, thereby can provide the required trigger voltage pulse value of FID of different specifications through the progression of dynamic adjustment cascade circuit, and this trigger circuit is controlled by small-signal RC trigger circuit. In the whole cascade circuit, capacitors C (1-n) at all levels are firstly charged in parallel and then are conducted step by ABJT, and then series discharge is carried out, so that ns and kV high-voltage electric pulses are generated on a pulse load resistor Rsn, voltages at two ends of an FID device are over-regulated, the FID device is conducted in nanoseconds and subnanoseconds, and a voltage stabilizing capacitor C discharges through the FID and a through-flow diode D1 and flows through large current. The whole FID pulse generating circuit avoids the use of a magnetic saturation transformer and a magnetic switch, thereby eliminating the unstable influence of the magnetic saturation transformer and the magnetic switch and solving the problem of demagnetization of the FID trigger circuit. Furthermore, the ABJT based cascaded circuit is small enough in overall size to make the FID pulse generating circuit advantageous for integration.

In order to further explain the present invention, the present invention provides a trigger circuit and an FID pulse generating circuit for FID, which are described in detail below with reference to the accompanying drawings and the detailed description.

As shown in fig. 2, the FID pulse generating circuit includes a trigger circuit 1 and a main flow circuit 2, the trigger circuit 1 includes a first trigger module 11 and a second trigger module 12, an input end of the second trigger module 12 is connected to an output end of the first trigger module 11, and an output end of the second trigger module 12 is used for connecting the external main flow circuit 2; the second trigger module 12 is a cascaded circuit including multiple stages of ABJT; the first trigger module 11 is configured to trigger a first stage ABJT in the cascade circuit, where the ABJT is then turned on stage by stage, so that capacitors charged in parallel in the cascade circuit are serially connected to discharge, and a nanosecond-level kV-level high-voltage pulse is generated on a last-stage load.

As shown in fig. 3, the first trigger module 11 is an RC trigger circuit, and specifically includes a series connection of C10 and R10, and a series connection end of the capacitor C10 and the resistor R10 is used as an output end of the first trigger module 11.

The cascade circuit of multiple stages of ABJTs in the second trigger module 12 includes n ABJTs (sequentially denoted as ABJT1, ABJT2 … … ABJTn), (n-1) pulse load resistors (sequentially denoted as Rs1, rs2 … … Rs (n-1)), n pulse discharge capacitors (sequentially denoted as C11, C12 … … C1 n), and n current limiting resistors (sequentially denoted as Rx1, rx2 … … Rxn);

wherein, ABJT1, pulse load resistance Rs1, pulse discharge capacitance C11 and current limiting resistance Rx1 form the first stage circuit in the cascade circuit; in the first-stage circuit, a control end of an ABJT1 is connected to a serial connection end of a capacitor C10 and a resistor R10, an input end of the ABJT1 is connected to the anode of a direct-current voltage source DC1 through a current-limiting resistor Rx1, an output end of the ABJT1 is grounded, and a pulse discharge capacitor C11 and a pulse load resistor Rs1 are sequentially connected between the input end of the ABJT1 and the ground in series; the serial connection end of the pulse discharge capacitor C11 and the pulse load resistor Rs1 is used as the output end of the first-stage circuit;

a second-stage circuit in the cascade circuit is formed by ABJT2, a pulse load resistor Rs2, a pulse discharge capacitor C12 and a current-limiting resistor Rx2; in the second-stage circuit, the control end and the output end of the ABJT2 are both connected to the serial connection end of a pulse discharge capacitor C12 and a pulse load resistor Rs2, the input end of the ABJT2 is connected to the positive electrode of a direct-current voltage source DC1 through a current-limiting resistor Rx2, and the pulse discharge capacitor C12 and the pulse load resistor Rs2 are sequentially connected between the input end of the ABJT2 and the ground in series; the serial connection end of the pulse discharge capacitor C12 and the pulse load resistor Rs2 is used as the output end of the second-stage circuit;

……

an nth stage circuit in the cascade circuit is formed by ABJTn, a load resistor RL, a pulse discharge capacitor C1n and a current limiting resistor Rxn; the control end and the output end of the ABJTn in the nth-stage circuit are both connected to the serial connection end of the pulse discharge capacitor C1n and the pulse load resistor RL, the input end of the ABJTn is connected to the positive electrode of the direct-current voltage source DC1 through the current-limiting resistor Rxn, one end of the pulse discharge capacitor C1n is connected to the input end of the ABJTn, the other end of the pulse discharge capacitor C1n is connected to one end of the load resistor RL, and the other end of the load resistor RL serving as the output end of the nth-stage circuit is also the output end of the second trigger circuit 12.

The main current circuit 2 comprises a rapid ionization device FID, a pulse load resistor Rsn, a current diode D1, a current limiting resistor Rf and a voltage stabilizing capacitor C21, a high-voltage power supply DC2 is connected after the current limiting resistor Rf is connected in series with the anode of the rapid ionization device FID, the voltage stabilizing capacitor C21 is connected in parallel with the anode of the rapid ionization device FID and then grounded, the pulse load resistor Rsn is connected in parallel with the current diode D1 and grounded, and the rapid ionization device FID is connected in series with parallel modules of Rsn and D1.

The main through-flow circuit DC2 firstly charges the voltage stabilizing capacitor C21 through the current limiting resistor Rf, after the pulse load resistor Rsn flows through the current pulse at the trigger circuit end, an ultrafast ultrahigh negative pressure is generated at the cathode of the FID in the main through-flow circuit, the negative pressure increases the voltage difference at two ends of the FID, the FID generates a rapid ionization wave effect in a critical avalanche state, the FID is conducted in nanosecond and subnanosecond states, the voltage stabilizing capacitor C21 discharges, and the discharging loop is C21-FID-D1.

In the charging process, the pulse discharge capacitor C1 (1-n) is charged by the trigger circuit end through the current limiting resistor Rx (1-n) by the DC1, so that the ABJT (1-n) works in the critical avalanche region, and the voltage stabilizing capacitor C21 is charged by the main current circuit through the current limiting resistor Rf by the DC2, so that the FID works in the critical avalanche region.

In the working process of the trigger circuit, firstly, a voltage pulse of 0-15V is input at the end (namely the left end and the opposite position of a C10 capacitor) of a small-signal RC trigger circuit of 0-15V, the voltage pulse drives ABJT1 avalanche to be opened, so that the capacitor C11 discharges through a C11-ABJT1-Rs1-C11 loop, current flows through a pulse load resistor Rs1 to generate an ultrafast negative voltage at an ABJT2 collector, and the negative voltage increases the voltage difference at two ends of the ABJT2, so that the ABJT2 is in overvoltage breakdown conduction in a critical avalanche state. The conduction of ABJT2 causes C12 to discharge in series with C11, and the conduction loop becomes C12-ABJT2-C11-ABJT1-Rs2. Similarly, the current in the discharge loop flows through the pulse load resistor Rs2 to generate an ultrafast negative voltage at the collector of ABJT3, which increases the voltage difference across ABJT3 to turn on ABJT3 in the critical avalanche state. In the same way, the ABJT (1 to n) in the whole cascade circuit is turned on step by step until the ABJTn is turned on, and finally the discharge loop is in series discharge by the discharge capacitors C1 (1 to n), the ABJT (1 to n), the Rsn and the load resistor RL.

When the voltage stabilizing capacitor C21 in the main through-flow circuit is charged completely, and the trigger circuit is switched on and discharged, the pulse load resistor Rsn passes through large current, so that an ultrafast ultrahigh negative pressure is generated at the cathode of the FID in the main through-flow circuit, the negative pressure increases the voltage difference between two ends of the FID, the FID generates a rapid ionization wave effect in a critical avalanche state, the FID is switched on in nanosecond and subnanosecond states, the voltage stabilizing capacitor C21 is discharged, and the discharge circuit is C21-FID-D1.

The utility model provides a be applied to trigger circuit of quick ionization device FID, to be based on the cascade circuit of ABJT and regard as the trigger circuit of FID pulse production circuit, cancelled magnetic saturation transformer and the magnetic switch setting of using in the conventional FID pulse production circuit, avoided the unstable influence that magnetic saturation transformer and magnetic switch brought, guaranteed that FID's stable trigger is opened, solved the demagnetization problem of FID pulse production circuit. And the miniaturization characteristic of the cascade circuit based on ABJT improves the integration characteristic of the FID pulse generation circuit.

It will be understood by those skilled in the art that the foregoing is merely exemplary of the present invention, and is not intended to limit the invention to the particular forms disclosed, and all changes, equivalents and modifications that fall within the spirit and scope of the invention are intended to be embraced thereby.

Claims

1. The trigger circuit applied to the FID is characterized by comprising a first trigger module and a second trigger module, wherein the input end of the second trigger module is connected to the output end of the first trigger module, and the output end of the second trigger module is used for being connected with an external main flow circuit;

the second trigger module is a cascade circuit comprising multiple levels of ABJT;

the first trigger module is used for triggering a first-stage ABJT in the cascade circuit, and the ABJT is conducted step by step subsequently, so that capacitors charged in parallel in the cascade circuit are discharged in series, and nanosecond-level kV-level high-voltage pulses are generated on a last-stage load.

2. The trigger circuit of claim 1, wherein the first trigger module comprises: and the capacitor C10 and the resistor R10 are sequentially connected between the 0-15V square wave voltage trigger small signal end and the ground in series, and the serial connection end of the capacitor C10 and the resistor R10 is used as the output end of the first trigger module.

3. The flip-flop circuit of claim 1 or 2, wherein said cascaded circuit of multiple stages of ABJT comprises a first stage circuit, a second stage circuit … …, and an nth stage circuit;

the input end of the first-stage circuit is used as the input end of the second trigger module, the output end of the nth-stage circuit is used as the output end of the second trigger module, the input end of the second-stage circuit is connected to the output end of the first-stage circuit, and the input end of the … … nth-stage circuit is connected to the output end of the (n-1) th-stage circuit.

4. The trigger circuit of claim 3, wherein the first stage circuit comprises: ABJT1, a pulse load resistor Rs1, a pulse discharge capacitor C11 and a current limiting resistor Rx1; the control end of the ABJT1 is used as the input end of the first-stage circuit, the input end of the ABJT1 is connected to the anode of an external direct-current voltage source DC1 through a current-limiting resistor Rx1, the output end of the ABJT1 is grounded, and a pulse discharge capacitor C11 and a pulse load resistor Rs1 are sequentially connected between the input end of the ABJT1 and the ground in series; the serial connection end of the pulse discharge capacitor C11 and the pulse load resistor Rs1 is used as the output end of the first-stage circuit;

5. An FID pulse generation circuit is characterized by comprising a trigger circuit and a main flow circuit, wherein the trigger circuit comprises a first trigger module and a second trigger module, the input end of the second trigger module is connected to the output end of the first trigger module, and the output end of the second trigger module is connected with the main flow circuit;

the second trigger module is a cascade circuit comprising a plurality of levels of ABJT;

the first trigger module is used for triggering a first-stage ABJT in the cascade circuit, and the ABJT is conducted step by step subsequently, so that capacitors charged in parallel in the cascade circuit are discharged in series, and nanosecond-level kV-level high-voltage pulses are generated on a last-stage load;

the high-voltage pulse is applied to two ends of an FID in a main current circuit, so that voltages at two ends of the FID are overshot, the FID generates a rapid ionization effect, and then a voltage stabilizing capacitor is connected in parallel to discharge the FID, so that the FID is switched on in a sub-nanosecond transient state and flows a large current.

6. The FID pulse generation circuit of claim 5, wherein the first trigger module comprises: the first trigger module includes: and the capacitor C10 and the resistor R10 are sequentially connected in series between the 0-15V square wave voltage trigger small signal end and the ground, and the series connection end of the capacitor C10 and the resistor R10 is used as the output end of the first trigger module.

7. The FID pulse generation circuit of claim 5 or 6, wherein the cascaded circuit of multiple stages of ABJT comprises a first stage circuit, a second stage circuit … …, and an nth stage circuit;

8. The FID pulse generation circuit of claim 7, wherein the first stage circuit comprises: ABJT1, a pulse load resistor Rs1, a pulse discharge capacitor C11 and a current limiting resistor Rx1; the control end of the ABJT1 is used as the input end of the first-stage circuit, the input end of the ABJT1 is connected to the anode of an external direct-current voltage source DC1 through a current-limiting resistor Rx1, the output end of the ABJT1 is grounded, and a pulse discharge capacitor C11 and a pulse load resistor Rs1 are sequentially connected between the input end of the ABJT1 and the ground in series; the serial connection end of the pulse discharge capacitor C11 and the pulse load resistor Rs1 is used as the output end of the first-stage circuit;

the nth stage circuit includes: ABJTn, a pulse load resistor RL, a pulse discharge capacitor C1n and a current limiting resistor Rxn; the control end and the output end of the ABJTn in the nth stage circuit are both used as the input end of the nth stage circuit, the input end of the ABJTn is connected to the positive electrode of the direct-current voltage source DC1 through a current-limiting resistor Rxn, one end of a pulse discharge capacitor C1n is connected to the input end of the ABJTn, the other end of the pulse discharge capacitor C1n is connected to one end of a load resistor RL, and the other end of the load resistor RL is used as the output end of the nth stage circuit and is also used as the output end of the second trigger circuit.

9. The FID pulse generation circuit of claim 5, wherein the main flow circuit comprises: the device comprises a rapid ionization device FID, a pulse load resistor Rsn, a through-current diode D1, a current-limiting resistor Rf and a voltage-stabilizing capacitor C21;

the anode of the rapid ionization device FID is connected with one end of the current-limiting resistor Rf, the other end of the current-limiting resistor Rf is connected with the anode of the high-voltage power supply DC2, and the cathode of the rapid ionization device FID is grounded through the pulse load resistor Rsn; the negative electrode of the high-voltage power supply DC2 is grounded;

one end of the voltage-stabilizing capacitor C21 is connected to the anode of the rapid ionization device FID, and the other end of the voltage-stabilizing capacitor C21 is grounded;

the anode of the through-flow diode D1 is connected to the cathode of the fast ionization device FID, and the cathode of the through-flow diode D1 is grounded.