CN218850381U - Overcurrent hardware protection device for asynchronous motor control system - Google Patents
Overcurrent hardware protection device for asynchronous motor control system Download PDFInfo
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- CN218850381U CN218850381U CN202320154288.2U CN202320154288U CN218850381U CN 218850381 U CN218850381 U CN 218850381U CN 202320154288 U CN202320154288 U CN 202320154288U CN 218850381 U CN218850381 U CN 218850381U
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Abstract
The utility model discloses an asynchronous machine control system overcurrent protection device. The current sampling circuit, the current positive and negative overcurrent judging circuit, the overcurrent signal gathering circuit, the RS latch circuit and the PWM locking circuit of the protection device are sequentially connected, the PWM locking circuit is connected with an external DSP (digital signal processor), the electrifying delay circuit is connected with the RS latch circuit, and the current sampling circuit is connected with the asynchronous motor. The utility model discloses the device can realize in asynchronous machine control, realizes reliable, quick hardware protection effect to asynchronous machine control system when overflowing the trouble.
Description
Technical Field
The utility model relates to a hardware protection device, concretely relates to asynchronous machine control system overflows hardware protection device.
Background
For an asynchronous motor control system, due to sudden change or misoperation of an operation working condition, the current of the system can exceed the maximum current which can be borne by an inverter or a motor, and the inverter and the motor can be irreversibly damaged by overlarge current, so that the service life of the asynchronous motor control system is seriously influenced, and even the inverter can be damaged. To avoid this, an overcurrent protection device needs to be installed in the system. Overcurrent protection is a protection mode in which a protection device is activated when a current exceeds a predetermined maximum value. When the current flowing through the motor exceeds a certain preset value of hardware, the protection device is started, and then the PWM pulse is blocked by the hardware, so that the system is stopped.
SUMMERY OF THE UTILITY MODEL
To the problem that exists among the background art, the utility model provides an asynchronous machine control system overflows hardware protection device to realize reliable, quick overcurrent protection function.
The utility model adopts the technical scheme as follows:
the overcurrent hardware protection device comprises a current sampling circuit for receiving and outputting a current signal of an asynchronous motor.
The overcurrent hardware protection device comprises a current positive and negative overcurrent judgment circuit for judging positive and negative overcurrent of a current signal output by the current sampling circuit.
The over-current hardware protection device comprises an over-current signal collecting circuit used for collecting current signals output by the current positive and negative over-current judging circuit.
The overcurrent hardware protection device comprises an RS latch circuit for latching the current signal output by the overcurrent signal summarizing circuit.
The over-current hardware protection device comprises a power-on delay circuit used for providing an output signal for the RS latch.
The overcurrent hardware protection device comprises a PWM locking circuit for locking the PWM signal of the external DSP processor.
The current sampling circuit, the current positive and negative overcurrent judging circuit, the overcurrent signal gathering circuit, the RS latch circuit and the PWM locking circuit are sequentially connected, the PWM locking circuit is connected with an external DSP (digital signal processor), the power-on delay circuit is connected with the RS latch circuit, and the current sampling circuit is connected with the asynchronous motor.
The current sampling circuit comprises three-phase samplers of an asynchronous motor, namely an A-phase sampler, a B-phase sampler and a C-phase sampler, each phase sampler comprises a current sensor, a first resistor, a first capacitor and a first operational amplifier, the asynchronous motor is respectively connected with the input end of the current sensor of the three-phase sampler, the output end of the current sensor of each phase sampler is sequentially connected to the same-direction input end of the first operational amplifier through the respective first resistor, the first capacitor is connected between the first resistor and the same-direction input end of the first operational amplifier, the reverse input end of the first operational amplifier is connected with the output end of the first operational amplifier, and the first operational amplifier is connected with a +/-5 VAVCC analog signal power supply; and current sensors of the three-phase sampler are connected with a current positive and negative overcurrent judgment circuit.
The current sensors of the three-phase sampler respectively collect three-phase current signals of the asynchronous motor, namely A-phase current I A Phase B current I B And C phase current I C Then transmitted to a current positive and negative overcurrent judgment circuit; the current sensors of the three-phase sampler are respectively an A-phase current sensor, a B-phase current sensor and a C-phase current sensor. The current sampling circuit respectively converts three-phase current signals into three-phase voltage signals of-3V to 3V, when one phase or a plurality of phase voltage signals exceed a preset voltage limit value, one or a plurality of first operational amplifiers connected with current sensors outputting the voltage signals exceeding the preset voltage limit value output first low-level signals, and the output first low-level signals replace respective one-phase current signals and are transmitted to the current positive and negative direction overcurrent judging circuit.
The current positive and negative overcurrent judgment circuit comprises a second resistor, a third resistor, a fourth resistor, a fifth resistor, a second capacitor, a third capacitor and six comparators, wherein one end of the second resistor is connected with a +/-5 VAVCC analog signal power supply, the other end of the second resistor is grounded after passing through the third resistor and the second capacitor respectively, and the second resistor is connected to the first comparator, the third comparator and the fifth comparator respectively; one end of a fifth resistor is connected with a +/-5 VAVCC analog signal power supply, the other end of the fifth resistor is grounded after passing through a fourth resistor and a third capacitor respectively, and the fifth resistor is connected to a second comparator, a fourth comparator and a sixth comparator respectively; the output ends of three first operational amplifiers of a three-phase sampler of the current sampling circuit are respectively connected with a first comparator, a second comparator, a third comparator, a fourth comparator, a fifth comparator and a sixth comparator; the output ends of the six comparators are connected with the over-current signal collecting circuit.
The current sampling circuit samples the A-phase current I A After being transmitted to the first comparator and the second comparator, the A-phase positive over-current signal Ia + and the A-phase negative over-current signal Ia-are respectively output; the current sampling circuit samples the B-phase current I B After being transmitted to the second comparator and the third comparator, the output signals respectively output a B-phase positive over-current signal Ib + and a B-phase negative over-current signal Ib < - >; the current sampling circuit samples the C phase current I C To a first comparator andthe second comparator respectively outputs a C-phase positive over-current signal Ic + and a C-phase negative over-current signal Ic < - >; the current positive and negative over-current judgment circuit transmits an A-phase positive over-current signal Ia +, an A-phase negative over-current signal Ia-, a B-phase positive over-current signal Ib +, a B-phase negative over-current signal Ib-, a C-phase positive over-current signal Ic + and a C-phase negative over-current signal Ic-to the over-current signal summarizing circuit; when the positive direction overcurrent signal or the negative direction overcurrent signal of one phase or a plurality of phases exceeds the preset current limit value, the overcurrent fault is represented, one or a plurality of comparators outputting the positive direction overcurrent signal or the negative direction overcurrent signal exceeding the preset current limit value output second low level signals, and the output second low level signals replace the respective positive direction overcurrent signal or the negative direction overcurrent signal of one phase and are transmitted to the overcurrent signal summarizing circuit.
Each comparator comprises a second operational amplifier, a sixth resistor and a third capacitor, the second operational amplifier is connected with a +/-5 VAVCC analog signal power supply, the sixth resistor is connected between the AVCC analog signal power supply and the output end of the second operational amplifier, and the output end of the second operational amplifier is connected with the third capacitor and then grounded; a second resistor of the current positive and negative direction overcurrent judging circuit is respectively connected to the homodromous input ends of second operational amplifiers of the first comparator, the third comparator and the fifth comparator, and a fifth resistor is respectively connected to the inverting input ends of the second operational amplifiers of the second comparator, the third comparator and the fifth comparator; the reverse input end of the second operational amplifier of the first comparator and the same-direction input end of the second operational amplifier of the second comparator are both connected with the output end of the first operational amplifier of the A-phase collector of the current sampling circuit, the reverse input end of the second operational amplifier of the third comparator and the same-direction input end of the second operational amplifier of the fourth comparator are both connected with the output end of the first operational amplifier of the B-phase collector of the current sampling circuit, and the reverse input end of the second operational amplifier of the fifth comparator and the same-direction input end of the second operational amplifier of the sixth comparator are both connected with the output end of the first operational amplifier of the C-phase collector of the current sampling circuit; the output ends of the second operational amplifiers of the six comparators are connected with the over-current signal summarizing circuit. And the output ends of the second operational amplifiers of the six comparators respectively transmit respective output signals to the over-current signal summarizing circuit.
When the current sampling circuit outputs one or more first low-level signals and then transmits the signals to the respective comparators, the one or more comparators receiving the first low-level signals directly transmit the first low-level signals to the overcurrent signal summarizing circuit. When receiving the first low level signal, the comparator does not generate a positive or negative overcurrent signal, but directly outputs the first low level signal.
The over-current signal summarizing circuit comprises five AND gates, each AND gate is connected with a +/-5 VAVCC analog signal power supply, the output end of the first AND gate is connected with the first input end of a fourth AND gate, the output end of the second AND gate is connected with the second input end of the fourth AND gate, the output end of the fourth AND gate is connected with the first input end of the fifth AND gate, and the output end of the third AND gate is connected with the second input end of the fifth AND gate; the output ends of second operational amplifiers of a first comparator and a second comparator of the current positive-negative over-current judging circuit are respectively connected with the first input end and the second input end of the first AND gate, the output ends of second operational amplifiers of a third comparator and a fourth comparator are respectively connected with the first input end and the second input end of the second AND gate, and the output ends of second operational amplifiers of the fourth comparator and a fifth comparator are respectively connected with the first input end and the second input end of the third AND gate; and the output end of the fifth AND gate is connected with the RS latch circuit.
The overcurrent signal collecting circuit collects the signals transmitted by the current positive and negative overcurrent judging circuit, outputs an overcurrent collecting OCPA signal and transmits the overcurrent collecting OCPA signal to the RS latch circuit; when the first low-level signal and/or the second low-level signal do not exist in the signals transmitted by the current positive and negative over-current judging circuit, the over-current summary OCPA signal output by the over-current signal summarizing circuit is a normal OCPA signal; when the first low level signal and/or the second low level signal exist in the signals transmitted by the current positive and negative direction overcurrent judging circuit, the overcurrent summary OCPA signal output by the overcurrent signal summarizing circuit is a fault OCPA signal.
The RS latch circuit comprises a first NAND gate and a second NAND gate, the first NAND gate and the second NAND gate are both connected with a +/-5 VAVCC analog signal power supply, a first input end of the first NAND gate is connected with an upper delay circuit, a second input end of the first NAND gate is connected with an output end of the second NAND gate, an output end of the first NAND gate is respectively connected with a first input end of the second NAND gate and a PWM locking circuit, and a second input end of the second NAND gate is connected with an output end of a fifth AND gate of an over-current signal collecting circuit.
The RS latch circuit latches the normal OCPA signal or the fault OCPA signal; the first NAND gate receives a high-level AA signal transmitted by the power-on delay circuit, the second NAND gate receives a normal OCPA signal or a fault OCPA signal output by the over-current signal collecting circuit, and the output end of the first NAND gate outputs an OCP signal and then transmits the OCP signal to the PWM locking circuit. When the overcurrent hardware protection circuit is powered on, a section of low-level signal appears at the AA signal end, and when no overcurrent fault occurs, the OCPA signal end is at a high level. At this time, the OCP signal outputs high level; through the action of the delay circuit, the AA signal end is changed into high level, and at the moment, the OCP signal maintains a high level state; when overcurrent faults occur, the signal end of the OCPA is at a low level, and the OCP signal outputs the low level; when the overcurrent fault disappears, the signal end of the OCPA is changed into high level, and the signal end of the OCP still maintains the low level state at the moment, which represents the occurrence of the overcurrent fault.
The PWM blocking circuit receives an OCP signal transmitted by the RS latch circuit and six paths of PWM signals transmitted by an external DSP processor, namely a PWM1 signal, a PWM2 signal, a PWM3 signal, a PWM4 signal, a PWM5 signal and a PWM6 signal, and outputs a PWM1_ N signal, a PWM2_ N signal, a PWM3_ N signal, a PWM4_ N signal, a PWM5_ N signal and a PWM6_ N signal and transmits the signals to the asynchronous motor. The signal output by the PWM locking circuit is applied to an inverter circuit in a control system of the asynchronous motor to control the inverter circuit.
The power-on delay circuit comprises a 55 timer TLC555, a diode, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a fourth capacitor, a fifth capacitor, a sixth capacitor and a triode, wherein a DISCH end of the 55 timer TLC555 is respectively connected with one end of the seventh resistor and one end of the ninth resistor, the other end of the seventh resistor is sequentially connected with a CONT end of the 55 timer TLC555 after passing through the fourth capacitor and the fifth capacitor, a TRIG end and a THRES end of the 55 timer TLC555 are respectively connected between the seventh resistor and the fourth capacitor, a THRES end of the 55 timer TLC555 is sequentially connected between the ninth resistor and the tenth resistor through the diode and the eighth resistor, a VDD end and a RESET end of the 55 timer TLC555 are respectively connected between the ninth resistor and the tenth resistor, an OUT end of the 55 timer TLC555 is respectively connected with one end of the eleventh resistor and a B base electrode of the triode, an emitter E end of the 55 timer TLC555 is connected with the other end of the triode, an eleventh resistor is connected between the ninth resistor and the tenth resistor, a collector of the ninth resistor and a collecting electrode of the sixth resistor, and a collecting electrode of the triode are respectively connected with a GND resistor, and a collecting electrode of the VAC 5; and a first input end of a first NAND gate of the RS latch circuit is connected between a triode of the power-on delay circuit and the sixth capacitor. And the power-on delay circuit outputs the high-level AA signal to the first input end of the first NAND gate of the RS latch circuit from between the triode and the sixth capacitor.
The utility model has the advantages that:
the utility model discloses the device can realize in asynchronous machine control, realizes reliable, quick hardware protection effect to asynchronous machine control system when overflowing the trouble.
Drawings
FIG. 1 is a block diagram of an overcurrent hardware protection device of an asynchronous motor control system;
FIG. 2 is a current sampling circuit diagram;
FIG. 3 is a circuit diagram of the current positive and negative overcurrent determination;
FIG. 4 is a circuit diagram of an over-current signal summary circuit;
FIG. 5 is a circuit diagram of a power-up delay circuit;
fig. 6 is a circuit diagram of an RS latch.
Detailed Description
The invention is described in further detail below with reference to the figures and specific embodiments.
As shown in fig. 1, the overcurrent hardware protection device of the invention comprises a current sampling circuit for receiving and outputting a current signal of an asynchronous motor; the current positive and negative overcurrent judgment circuit is used for judging positive and negative overcurrent of a current signal output by the current sampling circuit; the overcurrent signal collecting circuit is used for collecting current signals output by the current positive and negative overcurrent judging circuit; the RS latch circuit is used for latching the current signals output by the overcurrent signal summarizing circuit; comprises a power-on delay circuit for providing an output signal for the RS latch; the PWM locking circuit comprises a PWM locking circuit for locking a PWM signal of an external DSP processor; the current sampling circuit, the current positive and negative direction overcurrent judging circuit, the overcurrent signal collecting circuit, the RS latch circuit and the PWM locking circuit are sequentially connected, the PWM locking circuit is connected with an external DSP processor, the electrifying delay circuit is connected with the RS latch circuit, and the current sampling circuit is connected with the asynchronous motor.
The current sampling circuit comprises three-phase samplers of an asynchronous motor, namely an A-phase sampler, a B-phase sampler and a C-phase sampler, each phase sampler comprises a current sensor, a first resistor, a first capacitor and a first operational amplifier, the asynchronous motor is respectively connected with the input end of the current sensor of the three-phase sampler, the output end of the current sensor of each phase sampler is sequentially connected to the same-direction input end of the first operational amplifier through the respective first resistor, the first capacitor is connected between the first resistor and the same-direction input end of the first operational amplifier, the reverse input end of the first operational amplifier is connected with the output end of the first operational amplifier, and the first operational amplifier is connected with a +/-5 VAVCC analog signal power supply; and the current sensors of the three-phase sampler are connected with a current positive and negative overcurrent judging circuit.
The current sensors of the three-phase sampler respectively collect three-phase current signals of the asynchronous motor, namely A-phase current I A Phase B current I B And C phase current I C Then transmitted to a current positive and negative overcurrent judgment circuit; the current sensors of the three-phase sampler are respectively an A-phase current sensor, a B-phase current sensor and a C-phase current sensor. The current sampling circuit respectively converts three-phase current signals into three-phase voltage signals of-3V to 3V, and when one phase or several phase voltage signals exceed a preset voltage limit value, one or several current sensors outputting the voltage signals exceeding the preset voltage limit value are connected with a first current sensorThe operational amplifier outputs a first low level signal, and the output first low level signal replaces respective one-phase current signal and is transmitted to the current positive and negative direction overcurrent judging circuit.
The current positive and negative direction overcurrent judgment circuit comprises a second resistor, a third resistor, a fourth resistor, a fifth resistor, a second capacitor, a third capacitor and six comparators, wherein one end of the second resistor is connected with a +/-5 VAVCC analog signal power supply, the other end of the second resistor is grounded after passing through the third resistor and the second capacitor respectively, and the second resistor is connected to the first comparator, the third comparator and the fifth comparator respectively; one end of a fifth resistor is connected with a +/-5 VAVCC analog signal power supply, the other end of the fifth resistor is grounded after passing through a fourth resistor and a third capacitor respectively, and the fifth resistor is connected to a second comparator, a fourth comparator and a sixth comparator respectively; the output ends of three first operational amplifiers of a three-phase sampler of the current sampling circuit are respectively connected with a first comparator, a second comparator, a third comparator, a fourth comparator, a fifth comparator and a sixth comparator; the output ends of the six comparators are connected with the over-current signal collecting circuit.
The current sampling circuit samples the A-phase current I A After being transmitted to the first comparator and the second comparator, the A-phase positive over-current signal Ia + and the A-phase negative over-current signal Ia-are respectively output; the current sampling circuit samples the B-phase current I B After being transmitted to the second comparator and the third comparator, the output signals respectively output a B-phase positive over-current signal Ib + and a B-phase negative over-current signal Ib < - >; the current sampling circuit samples the C phase current I C After being transmitted to the first comparator and the second comparator, the output signals respectively output a C-phase positive over-current signal Ic + and a C-phase negative over-current signal Ic-; the current positive and negative over-current judgment circuit transmits an A-phase positive over-current signal Ia +, an A-phase negative over-current signal Ia-, a B-phase positive over-current signal Ib +, a B-phase negative over-current signal Ib-, a C-phase positive over-current signal Ic + and a C-phase negative over-current signal Ic-to the over-current signal summarizing circuit; when the positive or negative overcurrent signal of one or more phases exceeds the preset current limit value, representing that overcurrent fault occurs, one or more comparators outputting the positive or negative overcurrent signal exceeding the preset current limit value output a second low-level signal, and output a second low-level signalThe flat signals replace respective one-phase positive or negative over-current signals and are transmitted to the over-current signal summing circuit.
Each comparator comprises a second operational amplifier, a sixth resistor and a third capacitor, the second operational amplifier is connected with a +/-5 VAVCC analog signal power supply, the sixth resistor is connected between the AVCC analog signal power supply and the output end of the second operational amplifier, and the output end of the second operational amplifier is connected with the third capacitor and then grounded; a second resistor of the current positive and negative direction overcurrent judging circuit is respectively connected to the homodromous input ends of second operational amplifiers of the first comparator, the third comparator and the fifth comparator, and a fifth resistor is respectively connected to the inverting input ends of the second operational amplifiers of the second comparator, the third comparator and the fifth comparator; the reverse input end of the second operational amplifier of the first comparator and the same-direction input end of the second operational amplifier of the second comparator are both connected with the output end of the first operational amplifier of the A-phase collector of the current sampling circuit, the reverse input end of the second operational amplifier of the third comparator and the same-direction input end of the second operational amplifier of the fourth comparator are both connected with the output end of the first operational amplifier of the B-phase collector of the current sampling circuit, and the reverse input end of the second operational amplifier of the fifth comparator and the same-direction input end of the second operational amplifier of the sixth comparator are both connected with the output end of the first operational amplifier of the C-phase collector of the current sampling circuit; and the output ends of the second operational amplifiers of the six comparators are connected with the over-current signal summarizing circuit. And the output ends of the second operational amplifiers of the six comparators respectively transmit respective output signals to the over-current signal summarizing circuit.
When the current sampling circuit outputs one or more first low-level signals and then transmits the signals to the respective comparators, the one or more comparators receiving the first low-level signals directly transmit the first low-level signals to the overcurrent signal summarizing circuit. The comparator does not generate a positive or negative overcurrent signal when receiving the first low-level signal, but directly outputs the first low-level signal.
The over-current signal collecting circuit comprises five AND gates, each AND gate is connected with a +/-5 VAVCC analog signal power supply, the output end of the first AND gate is connected with the first input end of a fourth AND gate, the output end of the second AND gate is connected with the second input end of the fourth AND gate, the output end of the fourth AND gate is connected with the first input end of a fifth AND gate, and the output end of the third AND gate is connected with the second input end of the fifth AND gate; the output ends of second operational amplifiers of a first comparator and a second comparator of the current positive-negative direction overcurrent judging circuit are respectively connected with the first input end and the second input end of the first AND gate, the output ends of second operational amplifiers of a third comparator and a fourth comparator are respectively connected with the first input end and the second input end of the second AND gate, and the output ends of second operational amplifiers of the fourth comparator and a fifth comparator are respectively connected with the first input end and the second input end of the third AND gate; and the output end of the fifth AND gate is connected with the RS latch circuit.
The overcurrent signal collecting circuit collects the signals transmitted by the current positive and negative overcurrent judging circuit, outputs an overcurrent collecting OCPA signal and transmits the overcurrent collecting OCPA signal to the RS latch circuit; when the first low-level signal and/or the second low-level signal do not exist in the signals transmitted by the current positive-negative over-current judging circuit, the over-current summary OCPA signal output by the over-current signal summarizing circuit is a normal OCPA signal; when the first low level signal and/or the second low level signal exist in the signals transmitted by the current positive and negative overcurrent judging circuit, the overcurrent summary OCPA signal output by the overcurrent signal summarizing circuit is a fault OCPA signal.
The RS latch circuit comprises a first NAND gate and a second NAND gate, the first NAND gate and the second NAND gate are both connected with a +/-5 VAVCC analog signal power supply, a first input end of the first NAND gate is connected with an upper delay circuit, a second input end of the first NAND gate is connected with an output end of the second NAND gate, an output end of the first NAND gate is respectively connected with a first input end of the second NAND gate and a PWM locking circuit, and a second input end of the second NAND gate is connected with an output end of a fifth AND gate of an overcurrent signal collecting circuit.
The RS latch circuit latches the normal OCPA signal or the fault OCPA signal; the first NAND gate receives a high-level AA signal transmitted by the power-on delay circuit, the second NAND gate receives a normal OCPA signal or a fault OCPA signal output by the over-current signal collecting circuit, and the output end of the first NAND gate outputs an OCP signal and then transmits the OCP signal to the PWM locking circuit. When the overcurrent hardware protection circuit is electrified, a section of low-level signal appears at the AA signal end, and when overcurrent faults do not occur, the OCPA signal end is at a high level. At this time, the OCP signal outputs high level; through the action of the delay circuit, the AA signal end is changed into high level, and at the moment, the OCP signal maintains the high level state; when overcurrent faults occur, the signal end of the OCPA is at a low level, and the OCP signal outputs the low level; when the overcurrent fault disappears, the signal end of the OCPA is changed into high level, and the signal end of the OCP still maintains the low level state at the moment, which represents the occurrence of the overcurrent fault.
The PWM blocking circuit receives an OCP signal transmitted by the RS latch circuit and six paths of PWM signals transmitted by an external DSP processor, namely a PWM1 signal, a PWM2 signal, a PWM3 signal, a PWM4 signal, a PWM5 signal and a PWM6 signal, and outputs a PWM1_ N signal, a PWM2_ N signal, a PWM3_ N signal, a PWM4_ N signal, a PWM5_ N signal and a PWM6_ N signal and transmits the signals to the asynchronous motor. The signal output by the PWM locking circuit is applied to an inverter circuit in a control system of the asynchronous motor to control the inverter circuit.
The power-on delay circuit comprises a 55 timer TLC555, a diode, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a fourth capacitor, a fifth capacitor, a sixth capacitor and a triode, wherein the DISCH end of the 55 timer TLC555 is respectively connected with one end of the seventh resistor and one end of the ninth resistor, the other end of the seventh resistor is sequentially connected with the CONT end of the 55 timer TLC555 after passing through the fourth capacitor and the fifth capacitor, the TRIG end and the THRES end of the 55 timer TLC555 are respectively connected between the seventh resistor and the fourth capacitor, the THRES end of the 55 timer TLC555 is sequentially connected between the ninth resistor and the tenth resistor through the diode and the eighth resistor, the VDD end and the RESET end of the 55 timer TLC555 are respectively connected between the ninth resistor and the tenth resistor, the OUT end of the 55 timer TLC555 is respectively connected with one end of the eleventh resistor and the B base of the triode, the GND end of the 55 timer TLC is connected between the E emitter of the ninth resistor and the tenth resistor, the other end of the eleventh resistor is respectively connected between the ninth resistor and the tenth VCC of the triode, and the collector of the eleventh resistor are respectively connected with a power supply voltage source, and a collector of the eleventh resistor, and a collector of the tenth resistor of the eleventh resistor are respectively connected with a collector of the triode; and a first input end of a first NAND gate of the RS latch circuit is connected between a triode of the power-on delay circuit and the sixth capacitor. And the power-on delay circuit outputs the high-level AA signal to the first input end of the first NAND gate of the RS latch circuit from between the triode and the sixth capacitor.
The utility model discloses the device is at first through as shown in fig. 2 current sampling circuit, realizes the real-time sampling of motor three phase current, and the electric current that the sampling obtained shows respectively as I A 、I B And I C . Then the three-phase current (I) obtained by sampling A 、I B And I C ) And then the current is sent to a current positive and negative overcurrent judgment circuit, as shown in fig. 3, so as to generate positive overcurrent signals and negative overcurrent signals of three-phase current, wherein 6 overcurrent signals are respectively represented as Ia +, ia-, ib +, ib-, ic + and Ic-. Then, the 6 overcurrent signals are sent to an overcurrent signal summarizing circuit, as shown in fig. 4, so that the summarizing of the three-phase positive and negative overcurrent signals is further realized, when an overcurrent signal occurs in any phase, an overcurrent summarizing signal with a low level is immediately triggered and generated to represent that an overcurrent fault occurs, and the generated overcurrent summarizing signal ratio is represented as an OCPA signal. And then, after the overcurrent protection device is powered on, the power-on delay circuit delays and outputs a high-level signal, wherein the signal is represented as an AA signal, and the power-on delay circuit is shown in fig. 5. Then, the RS latch circuit latches the over-current summary signal OCPA, and as long as the OCPA signal is in a low level, the output end of the RS latch always outputs the low level. The signal AA generated by the power-on delay circuit is the other input signal to the RS latch. The RS latch circuit is shown in fig. 6. And finally, the output signal (OCP) of the RS latch is in AND operation with the 6 paths of PWM signals, and when the output signal of the RS latch is in a low level, the PWM signals are immediately blocked, so that the function of hardware overcurrent protection is realized.
Claims (7)
1. The utility model provides an asynchronous machine control system overflows hardware protection device which characterized in that:
the current sampling circuit is used for receiving and outputting a current signal of the asynchronous motor;
the current positive and negative overcurrent judgment circuit is used for judging the positive and negative overcurrent of a current signal output by the current sampling circuit;
the overcurrent signal collecting circuit is used for collecting current signals output by the current positive and negative overcurrent judging circuit;
the RS latch circuit is used for latching the current signals output by the overcurrent signal summarizing circuit;
comprises a power-on delay circuit for providing an output signal for the RS latch;
a PWM lockout circuit including lockout for signals of an external DSP processor;
the current sampling circuit, the current positive and negative direction overcurrent judging circuit, the overcurrent signal collecting circuit, the RS latch circuit and the PWM locking circuit are sequentially connected, the PWM locking circuit is connected with an external DSP processor, the electrifying delay circuit is connected with the RS latch circuit, and the current sampling circuit is connected with the asynchronous motor.
2. The asynchronous motor control system overcurrent hardware protection device of claim 1, wherein: the current sampling circuit comprises three-phase samplers of an asynchronous motor, namely an A-phase sampler, a B-phase sampler and a C-phase sampler, each phase sampler comprises a current sensor, a first resistor, a first capacitor and a first operational amplifier, the asynchronous motor is respectively connected with the input end of the current sensor of the three-phase sampler, the output end of the current sensor of each phase sampler is sequentially connected to the same-direction input end of the first operational amplifier through the respective first resistor, the first capacitor is connected between the first resistor and the same-direction input end of the first operational amplifier, the reverse input end of the first operational amplifier is connected with the output end of the first operational amplifier, and the first operational amplifier is connected with an AVCC analog signal power supply; and the current sensors of the three-phase sampler are connected with a current positive and negative overcurrent judging circuit.
3. The over-current hardware protection device of the asynchronous motor control system according to claim 2, characterized in that: the current positive and negative over-current judgment circuit comprises a second resistor, a third resistor, a fourth resistor, a fifth resistor, a second capacitor, a third capacitor and six comparators, wherein one end of the second resistor is connected with an AVCC analog signal power supply, the other end of the second resistor is grounded after passing through the third resistor and the second capacitor respectively, and the second resistor is connected to the first comparator, the third comparator and the fifth comparator respectively; one end of a fifth resistor is connected with an AVCC analog signal power supply, the other end of the fifth resistor is grounded after passing through a fourth resistor and a third capacitor respectively, and the fifth resistor is connected to a second comparator, a fourth comparator and a sixth comparator respectively; the output ends of three first operational amplifiers of a three-phase sampler of the current sampling circuit are respectively connected with a first comparator, a second comparator, a third comparator, a fourth comparator, a fifth comparator and a sixth comparator; the output ends of the six comparators are connected with the over-current signal collecting circuit.
4. The over-current hardware protection device of the asynchronous motor control system according to claim 3, characterized in that: each comparator comprises a second operational amplifier, a sixth resistor and a third capacitor, the second operational amplifier is connected with an AVCC analog signal power supply, the sixth resistor is connected between the AVCC analog signal power supply and the output end of the second operational amplifier, and the output end of the second operational amplifier is connected with the third capacitor and then grounded; a second resistor of the current positive and negative direction overcurrent judging circuit is respectively connected to the homodromous input end of a second operational amplifier of the first comparator, the third comparator and the fifth comparator, and a fifth resistor is respectively connected to the reverse input end of the second operational amplifier of the second comparator, the third comparator and the fifth comparator; the reverse input end of the second operational amplifier of the first comparator and the same-direction input end of the second operational amplifier of the second comparator are both connected with the output end of the first operational amplifier of the A-phase collector of the current sampling circuit, the reverse input end of the second operational amplifier of the third comparator and the same-direction input end of the second operational amplifier of the fourth comparator are both connected with the output end of the first operational amplifier of the B-phase collector of the current sampling circuit, and the reverse input end of the second operational amplifier of the fifth comparator and the same-direction input end of the second operational amplifier of the sixth comparator are both connected with the output end of the first operational amplifier of the C-phase collector of the current sampling circuit; and the output ends of the second operational amplifiers of the six comparators are connected with the over-current signal summarizing circuit.
5. The over-current hardware protection device of the asynchronous motor control system according to claim 3, characterized in that:
the over-current signal collecting circuit comprises five AND gates, each AND gate is connected with an AVCC analog signal power supply, the output end of the first AND gate is connected with the first input end of a fourth AND gate, the output end of the second AND gate is connected with the second input end of the fourth AND gate, the output end of the fourth AND gate is connected with the first input end of a fifth AND gate, and the output end of the third AND gate is connected with the second input end of the fifth AND gate; the output ends of second operational amplifiers of a first comparator and a second comparator of the current positive-negative over-current judging circuit are respectively connected with the first input end and the second input end of the first AND gate, the output ends of second operational amplifiers of a third comparator and a fourth comparator are respectively connected with the first input end and the second input end of the second AND gate, and the output ends of second operational amplifiers of the fourth comparator and a fifth comparator are respectively connected with the first input end and the second input end of the third AND gate; and the output end of the fifth AND gate is connected with the RS latch circuit.
6. The asynchronous motor control system overcurrent hardware protection device of claim 5, wherein: the RS latch circuit comprises a first NAND gate and a second NAND gate, the first NAND gate and the second NAND gate are both connected with an AVCC analog signal power supply, a first input end of the first NAND gate is connected with an upper delay circuit, a second input end of the first NAND gate is connected with an output end of the second NAND gate, an output end of the first NAND gate is respectively connected with a first input end of the second NAND gate and a PWM locking circuit, and a second input end of the second NAND gate is connected with an output end of a fifth AND gate of an overcurrent signal collecting circuit.
7. The asynchronous motor control system overcurrent hardware protection device of claim 6, wherein: the power-on delay circuit comprises a 55 timer TLC555, a diode, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a fourth capacitor, a fifth capacitor, a sixth capacitor and a triode, wherein a DISCH end of the 55 timer TLC555 is respectively connected with one end of the seventh resistor and one end of the ninth resistor, the other end of the seventh resistor is sequentially connected with a CONT end of the 55 timer TLC555 after passing through the fourth capacitor and the fifth capacitor, a TRIG end and a THRES end of the 55 timer TLC555 are respectively connected between the seventh resistor and the fourth capacitor, a THRES end of the 55 timer TLC555 is sequentially connected between the ninth resistor and the tenth resistor through the diode and the eighth resistor, a VDD end and a RESET end of the 55 timer TLC555 are respectively connected between the ninth resistor and the tenth resistor, an OUT end of the 55 timer TLC555 is respectively connected with one end of the eleventh resistor and a B base of the triode, an emitter end of the 55 timer TLC is connected with the other end of the triode TLC555, the eleventh resistor and the eleventh resistor are respectively connected between a collector of the ninth resistor and the tenth resistor, and a collector of the sixth resistor are respectively connected with a GND, and a collector of the triode C, and a signal power supply source of a signal source; and a first input end of a first NAND gate of the RS latch circuit is connected between a triode of the power-on delay circuit and the sixth capacitor.
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