CN218848603U - ARINC429 aviation bus implementation circuit - Google Patents
ARINC429 aviation bus implementation circuit Download PDFInfo
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- CN218848603U CN218848603U CN202223328266.8U CN202223328266U CN218848603U CN 218848603 U CN218848603 U CN 218848603U CN 202223328266 U CN202223328266 U CN 202223328266U CN 218848603 U CN218848603 U CN 218848603U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The utility model provides an ARINC429 aviation bus realization circuit, which comprises an 8-bit singlechip, a NAND gate IC5B, an electronic switch and a voltage comparison circuit, wherein the voltage comparison circuit comprises an operational amplifier; the 8-bit singlechip is connected with the NAND gate, the electronic switch and the voltage comparison circuit consisting of the operational amplifier. The utility model discloses a ARINC429 aviation bus realizes the circuit, and is with low costs, simple easy-to-use, and the circuit is stable.
Description
Technical Field
The utility model relates to an aviation bus technical field especially relates to a ARINC429 aviation bus realizes circuit.
Background
The ARINC429 protocol provides for the transmission of digital data information in a serial fashion using twisted pair shielded wire, with unidirectional transmission, i.e., only 1 transmitting device is allowed on the bus, and there may be multiple (< 20) receiving devices. When two devices need to transmit information in two directions, a separate transmission bus is used in each direction. The information transmission adopts a bipolar return-to-zero tri-state code modulation mode, namely modulation signals are modulated by a three-level state consisting of a high state, a zero state and a low state. Transmitter and receiver level ranges as shown in fig. 2.
In the existing market, an STM32 ARM single chip microcomputer is adopted, and a standard ARINC429 signal is generated by matching with an expensive ARINC429 bus chip and a drive chip, and a block diagram is shown in FIG. 3. The special ARIN429 bus interface chip and the drive chip are expensive, the 32-bit ARM single chip microcomputer is high in price, and the writing program is complicated.
SUMMERY OF THE UTILITY MODEL
To foretell defect, the utility model aims to provide an ARINC429 aviation bus realizes circuit, and is with low costs, simple easy-to-use, the circuit is stable.
In order to achieve the above object, the utility model provides an ARINC429 aviation bus realizes circuit, including 8 bit singlechips, NAND gate IC5B, electronic switch and voltage comparison circuit, the voltage comparison circuit includes operational amplifier; the 8-bit singlechip is connected with the NAND gate, the electronic switch and the operational amplifier to form a voltage comparison circuit.
Preferably, the 8-bit single chip generates a timing pulse CLOCK, and the ARINC429 bus data to be transmitted is transmitted when the CLOCK pulse is high, and a standard ARINC429 bus signal is output through the nand gate IC5B, the electronic switch and the voltage comparison circuit formed by the operational amplifier.
Further, the number of the nand gates IC5B is 1, and the number of the electronic switches is 2, namely, the electronic switch IC2A and the electronic switch IC2B.
Furthermore, pins 5 and 6 of the nand gate IC5B are both connected to the 8-bit single chip microcomputer, pins 5 and 6 of the nand gate IC5B are also connected in parallel to pins 12 of the electronic switch IC2B, pins 11 of the electronic switch IC2B are connected to the 8-bit single chip microcomputer, pins 4 of the nand gate IC5B are connected to pins 13 of the electronic switch IC2A, and pins 1 of the electronic switch IC2A are respectively connected to one end of the capacitor C4, one end of the resistor R2, and one end of the resistor R3; the other end of the capacitor C4 is connected with a power supply VCC, the other end of the resistor R2 is connected with the power supply VCC, and the other end of the resistor R3 is grounded; pin 2 of electronic switch IC2A and pin 10 of electronic switch IC2B are connected in parallel to the voltage comparison circuit.
Further, the voltage comparison circuit includes 4 operational amplifiers, which are respectively an operational amplifier IC3A, an operational amplifier IC3B, an operational amplifier IC3C, and an operational amplifier IC3D;
the pin 2 of the electronic switch IC2A and the pin 10 of the electronic switch IC2B are connected in parallel to the pin 2 of the operational amplifier IC3A and the pin 5 of the operational amplifier IC 3B.
Furthermore, pin 2 of the operational amplifier IC3A is further connected to pin 1 of the operational amplifier IC3A and pin 10 of the operational amplifier IC3C through a resistor R11, pin 11 of the operational amplifier IC3A is connected to the power supply VEE, and pin 11 of the operational amplifier IC3A is further connected to ground through a capacitor C10; the 4 pins of the operational amplifier IC3A are connected with a power supply VCC, and the 4 pins of the operational amplifier IC3A are also grounded through a capacitor C9; a pin 3 of the operational amplifier IC3A is respectively connected with one end of a resistor R8 and one end of a resistor R9, the other end of the resistor R8 is grounded, and the other end of the resistor R9 is connected with a power supply VCC;
Furthermore, pin 6 of the operational amplifier IC3B is connected to one end of the resistor R6 and one end of the resistor R7 through the resistor R4, respectively, the other end of the resistor R6 is grounded, and the other end of the resistor R9 is connected to the power supply VCC; the pin 6 of the operational amplifier IC3B is also connected with the pin 7 of the operational amplifier IC3B and the pin 12 of the operational amplifier IC3D through a resistor R5;
Further, pin 2 of the electronic switch IC2A and pin 10 of the electronic switch IC2B are connected to pin 2 of the operational amplifier IC3A via a resistor R10.
Further, the nand gate IC5B adopts a chip with a model number of 74HC02, 2 electronic switches all adopt switch chips with a model number of CD4066, and 4 operational amplifiers all adopt high-precision operational amplifier chips with a model number of TLE 2144.
The utility model provides a ARINC429 aviation bus realizes circuit, and is with low costs, simple easy-to-use, the circuit is stable.
Drawings
Fig. 1 is a signal circuit diagram of an ARINC429 aviation bus implementation circuit of the present invention;
FIG. 2 is a waveform diagram of ARINC429 bus in the background art;
fig. 3 is a block diagram of a prior art ARINC429 bus implementation in the background art.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the invention.
Referring to fig. 1, the utility model provides a ARINC429 aviation bus realizes circuit, including 8 bit singlechips, NAND gate IC5B, electronic switch and voltage comparison circuit, the voltage comparison circuit includes operational amplifier.
Using IO/P3.4 of an 8-bit singlechip as a CLOCK mark; IO/P3.5 of the 8-bit singlechip is used as a DATA mark; in software, a timer of an 8-bit 8051 singlechip is used for generating a 32-bit timing pulse CLOCK according to the rate of a standard ARINC429 bus, and the pulse width is 40us when 12.5K is used; the pulse width is 5us when 100K is used. At the same time, ARINC429 bus data to be transmitted are sent out from the first bit to the 32 th bit when the CLOCK pulse is high level, and a standard ARINC429 bus signal is output through a voltage comparison circuit consisting of an NAND gate, an electronic switch and an operational amplifier.
Specifically, 1 nand gate IC5B is provided, and a chip of the type 74HC02 is used.
The electronic switch is provided with 2, is electronic switch IC2A and electronic switch IC2B respectively, and 2 electronic switches all adopt the switch chip that the model is CD 4066.
The voltage comparison circuit comprises 4 operational amplifiers, namely an operational amplifier IC3A, an operational amplifier IC3B, an operational amplifier IC3C and an operational amplifier IC3D, wherein the 4 operational amplifiers are all high-precision operational amplifier chips with the model number of TLE 2144.
Specifically, the 5 pin and the 6 pin of the nand gate IC5B are both connected to an IO/P3.4 pin (not shown) of the 8-bit monolithic computer, and the IO/P3.4 pin of the 8-bit monolithic computer is used as a CLOCK identifier, and the CLOCK identifier in fig. 1 is connected to the 5 pin and the 6 pin of the nand gate IC 5B.
A pin 4 of the NAND gate IC5B is connected with a pin 13 of the electronic switch IC2A, and a pin 1 of the electronic switch IC2A is respectively connected with one end of the capacitor C4, one end of the resistor R2 and one end of the resistor R3; the other end of the capacitor C4 is connected with a power supply VCC, the other end of the resistor R2 is connected with the power supply VCC, and the other end of the resistor R3 is grounded; the pin 2 of the electronic switch IC2A and the pin 10 of the electronic switch IC2B are connected in parallel to the pin 2 of the operational amplifier IC3A and the pin 5 of the operational amplifier IC 3B.
The pin 2 of the operational amplifier IC3A is also connected to the pin 1 of the operational amplifier IC3A and the pin 10 of the operational amplifier IC3C through a resistor R11 respectively, the pin 11 of the operational amplifier IC3A is connected with a power supply VEE, and the pin 11 of the operational amplifier IC3A is also grounded through a capacitor C10; the 4 pins of the operational amplifier IC3A are connected with a power supply VCC, and the 4 pins of the operational amplifier IC3A are also grounded through a capacitor C9; the pin 3 of the operational amplifier IC3A is connected to one end of the resistor R8 and one end of the resistor R9, respectively, the other end of the resistor R8 is grounded, and the other end of the resistor R9 is connected to the power supply VCC.
The operational amplifier IC3C has pins 9 and 8 connected to the-429 output terminals of the standard ARINC429 bus signal.
A pin 6 of the operational amplifier IC3B is respectively connected with one end of a resistor R6 and one end of a resistor R7 through a resistor R4, the other end of the resistor R6 is grounded, and the other end of a resistor R9 is connected with a power supply VCC; the pin 6 of the operational amplifier IC3B is also connected to the pin 7 of the operational amplifier IC3B and the pin 12 of the operational amplifier IC3D via a resistor R5, respectively.
The utility model discloses use 8 bit singlechips to combine CD4066 switch chip, 74HC02 chip and TLE2144 high accuracy operational amplifier chip, can produce 12.5K, 100K standard ARINC429 signal to reserve has IO mouth, the bus interface of singlechip, for follow-up integrated circuit board extension (use button control integrated circuit board bus signal to change or receive the change of instruction control ARINC429 bus through the RS232 bus) reservation.
The 8-bit single chip microcomputer with low price and simplicity and usability is adopted to replace an STM32 single chip microcomputer, and the ARINC429 bus chip and the bus driving chip with high price are replaced by the stable operational amplifier with low price.
The utility model provides a ARINC429 aviation bus realizes circuit, and is with low costs, simple easy-to-use, the circuit is stable.
Of course, the present invention can be embodied in many other forms without departing from the spirit or essential attributes thereof, and it is intended that all such modifications and variations be considered within the spirit or scope of the present invention as defined by the appended claims.
Claims (9)
1. An ARINC429 aviation bus implementation circuit is characterized by comprising an 8-bit singlechip, an NAND gate IC5B, an electronic switch and a voltage comparison circuit, wherein the voltage comparison circuit comprises an operational amplifier; the 8-bit singlechip is connected with the NAND gate, the electronic switch and the voltage comparison circuit consisting of the operational amplifier.
2. The ARINC429 aviation bus realization circuit as claimed in claim 1, wherein an 8-bit single chip microcomputer generates a timing pulse CLOCK, ARINC429 bus data to be transmitted is transmitted when the CLOCK pulse is high level, and a standard ARINC429 bus signal is output through a NAND gate IC5B, an electronic switch and a voltage comparison circuit composed of an operational amplifier.
3. The ARINC429 aviation bus implementation circuit as claimed in claim 1, wherein there are 1 NAND gate IC5B and 2 electronic switches, electronic switch IC2A and electronic switch IC2B.
4. The ARINC429 aviation bus realization circuit as claimed in claim 3, wherein pins 5 and 6 of NAND gate IC5B are both connected to an 8-bit single chip microcomputer, pins 5 and 6 of NAND gate IC5B are also connected in parallel to pin 12 of electronic switch IC2B, pin 11 of electronic switch IC2B is connected to the 8-bit single chip microcomputer, pin 4 of NAND gate IC5B is connected to pin 13 of electronic switch IC2A, pin 1 of electronic switch IC2A is respectively connected to one end of capacitor C4, one end of resistor R2 and one end of resistor R3; the other end of the capacitor C4 is connected with a power supply VCC, the other end of the resistor R2 is connected with the power supply VCC, and the other end of the resistor R3 is grounded; pin 2 of electronic switch IC2A and pin 10 of electronic switch IC2B are connected in parallel to the voltage comparison circuit.
5. The ARINC429 aviation bus implementation circuit of claim 4, wherein the voltage comparison circuit comprises 4 operational amplifiers, respectively operational amplifier IC3A, operational amplifier IC3B, operational amplifier IC3C, operational amplifier IC3D;
the pin 2 of the electronic switch IC2A and the pin 10 of the electronic switch IC2B are connected in parallel to the pin 2 of the operational amplifier IC3A and the pin 5 of the operational amplifier IC 3B.
6. The ARINC429 aviation bus implementation circuit as claimed in claim 5, wherein pin 2 of the operational amplifier IC3A is further connected to pin 1 of the operational amplifier IC3A and pin 10 of the operational amplifier IC3C through a resistor R11, respectively, pin 11 of the operational amplifier IC3A is connected to a power supply VEE, and pin 11 of the operational amplifier IC3A is further connected to ground through a capacitor C10; the 4 pins of the operational amplifier IC3A are connected with a power supply VCC, and the 4 pins of the operational amplifier IC3A are also grounded through a capacitor C9; the pin 3 of the operational amplifier IC3A is respectively connected with one end of a resistor R8 and one end of a resistor R9, the other end of the resistor R8 is grounded, and the other end of the resistor R9 is connected with a power supply VCC;
pins 9 and 8 of the operational amplifier IC3C are connected to the-429 output terminals of the standard ARINC429 bus signal.
7. The ARINC429 aviation bus realization circuit as claimed in claim 6 wherein pin 6 of operational amplifier IC3B is connected to one end of resistor R6 and one end of resistor R7 respectively through resistor R4, the other end of resistor R6 is grounded, the other end of resistor R9 is connected to power VCC; the pin 6 of the operational amplifier IC3B is also connected with the pin 7 of the operational amplifier IC3B and the pin 12 of the operational amplifier IC3D through a resistor R5;
pins 13 and 14 of the operational amplifier IC3D are connected to the +429 output terminals of the standard ARINC429 bus signal.
8. The ARINC429 aviation bus implementation circuit as claimed in claim 5, wherein pin 2 of electronic switch IC2A and pin 10 of electronic switch IC2B are connected to pin 2 of operational amplifier IC3A via resistor R10.
9. The ARINC429 aviation bus implementation circuit as claimed in claim 5, wherein NAND IC5B is a chip with model 74HC02, 2 electronic switches are switch chips with model CD4066, and 4 operational amplifiers are high-precision operational amplifier chips with model TLE 2144.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223328266.8U CN218848603U (en) | 2022-12-13 | 2022-12-13 | ARINC429 aviation bus implementation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223328266.8U CN218848603U (en) | 2022-12-13 | 2022-12-13 | ARINC429 aviation bus implementation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN218848603U true CN218848603U (en) | 2023-04-11 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202223328266.8U Active CN218848603U (en) | 2022-12-13 | 2022-12-13 | ARINC429 aviation bus implementation circuit |
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| Country | Link |
|---|---|
| CN (1) | CN218848603U (en) |
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2022
- 2022-12-13 CN CN202223328266.8U patent/CN218848603U/en active Active
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