CN218827102U - Semiconductor packaging structure - Google Patents

Abstract

Embodiments of the present application provide a semiconductor package structure, including a first wire structure, a first electronic element, and a second electronic element; the first electronic element is positioned on the first lead structure, and a first active surface of the first electronic element faces the first lead structure; the second electronic element is positioned on the first lead structure and is spaced apart from the first electronic element, and the second active surface of the second electronic element faces the first lead structure; the first wire structure includes a trace located below the first active surface and the second active surface, the trace electrically connecting the first electronic component and the second electronic component, and a full projection of the trace in the longitudinal direction being located within an edge of the first active surface. The present application is directed to a semiconductor package structure, so as to solve at least the problem of trace damage of a first conductive line structure in the semiconductor package structure.

Description

Semiconductor packaging structure

Technical Field

Embodiments of the present application relate to a semiconductor package structure.

Background

As the demand for the function and performance of semiconductor packages increases, the degree of integration of chips in fan-out chips (FO die) increases, and the number of layers of loaded redistribution layers (RDLs) increases. The greater the number of RDL layers and the greater the density of chips, the greater the stress at the chip-to-chip interface will be. As shown in FIG. 1a for a fan-out chip on board (FOCOS) 10, an Application Specific Integrated Circuit (ASIC) 20 is in signal communication with a High Bandwidth Memory (HBM) 30 primarily through a redistribution layer trace (RDL trace) 52 in RDL 50 located below a Die Gap (Die Gap) 40 between ASIC 20 and HBM 30. Since the HBM 30 is a composite 3D package component, which has a complex structure and contains a large amount of polymer material, when heated, the component is more susceptible to thermal influence, which results in a large amount of expansion and deformation warpage (as shown in fig. 1 b), so that the redistribution layer traces 52 located below the chip gap 40 are easily damaged.

In addition, the stress between the chips also causes the underfill/underfill (Under-fill) to fail to withstand deformation and break. The complication of the module chip system in a multi-chip module (MCM) is a serious problem of stress accumulation, which is also a cause of underfill cracking. The primer which can be found according to the engineering experiment direction at present can effectively solve the problem of primer fracture. Therefore, the problem of underfill cracking of the semiconductor package cannot be effectively solved, and the yield is also low (less than 20%). The largest stress strain is concentrated at the corner (corner) 32 of the ASIC 20 faced by the HBM 30, resulting in delamination (delamination) and cracking (crack) problems at the underfill (under fill) 60, as shown in fig. 1 c-1 d (fig. 1d is a partially enlarged view at the corner 32 in fig. 1 c). And in practice, the higher the temperature, the more severe the deformation expansion of the HBM 30 and the more severe the delamination and cracking at the corners 32. The underfill 60, however, cannot maintain consistent deformation with the HBM 30 due to its low Coefficient of Thermal Expansion (CTE), and thus cannot effectively balance the warpage problem. And the internal material of the HBM 30 cannot be replaced with a non-polymer material at present to improve the above problem.

The RDL 50 has a large number of layers and is made of a soft material, and cannot effectively bear stress concentration caused by the multi-chip module. Delamination and cracking at corner 32 due to stress strain concentrations continues to expand in the direction of RDL 50 resulting in a break in RDL trace 52 below die gap 40. The number of layers of the RDL 50 cannot be reduced, and the problem of stress-strain concentration cannot be alleviated, so that warpage (warp) due to stress-strain concentration is also difficult to control.

The stress problem of the underfill 60 is currently typically alleviated by increasing the distance between the ASIC 20 and the HBM 30 (e.g., increasing the distance between the two to 200 μm), but an increase in the separation distance in turn decreases the speed of transmission of signals between the two. And when the lateral dimension of the FOCOS 10 exceeds, for example, 830mm2 or more, it is difficult to solve the problem that the underfill 60 is easily broken even if the distance between the ASIC 20 and the HBM 30 is increased.

SUMMERY OF THE UTILITY MODEL

In view of the problems in the related art, it is an object of the present application to provide a semiconductor package structure to solve at least the problem of damage to traces in a first wire structure.

To achieve the above object, the present application provides a semiconductor package structure including a first wire structure, a first electronic element, and a second electronic element; the first electronic element is positioned on the first lead structure, and a first active surface of the first electronic element faces the first lead structure; the second electronic element is positioned on the first lead structure and is separated from the first electronic element, and the second active surface of the second electronic element faces the first lead structure; the first wire structure includes a trace located under the first active surface and the second active surface, the trace electrically connecting the first electronic element and the second electronic element, and a full projection of the trace in the longitudinal direction is located within an edge of the first active surface.

In some embodiments, the heat dissipation device further comprises a heat dissipation element, wherein the heat dissipation element is positioned on the second electronic element and is positioned on one side of the first electronic element in the horizontal direction.

In some embodiments, an underfill layer is also included, the underfill layer encapsulating the second electronic component.

In some embodiments, the underfill layer also encapsulates at least a portion of the first electronic component, the underfill layer filling a space between the first electronic component and the heat dissipation element.

In some embodiments, a molding compound encapsulating the underfill layer, the first electronic component, and the second electronic component and covering the traces is also included, the molding compound having a rigidity greater than a rigidity of the underfill layer.

In some embodiments, the first electronic component has a plurality of first interconnects electrically connected to the first wire structures on the first active surface, and a top surface of the first interconnects is higher than a top surface of the second electronic component.

In some embodiments, the electronic device further includes a first conductive pillar located on one side of the second electronic element and located under the first interconnection element, the first conductive pillar is electrically connected to the first connection element, and a thickness of the first conductive pillar is greater than a thickness of the second electronic element.

In some embodiments, the conductive structure further includes a second conductive line structure located above the first conductive pillar and the second electronic element, and the second conductive line structure is located between the first electronic element and the first conductive pillar.

In some embodiments, the second lead structure includes an opening exposing an upper surface of the second electronic component, and the heat dissipation member is attached to the upper surface of the second electronic component.

In some embodiments, the electronic device further comprises a lead between the first conductive pillar and the second electronic element, the lead electrically connecting the second conductive line structure and the first conductive line structure, the lead and the first conductive line structure not including a seed layer therebetween.

Drawings

The various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1a is a schematic diagram of a semiconductor package structure in the prior art.

FIG. 1b is a schematic view of the warpage of a semiconductor package structure in the prior art.

FIG. 1c is a schematic diagram of the delamination and cracking of the underfill layer of a prior art semiconductor package structure.

Fig. 1d is an enlarged view of a portion of fig. 1c at the corner.

Fig. 2A is a schematic diagram of a semiconductor package structure according to a first embodiment of the present application.

Fig. 2B is a schematic diagram of a semiconductor package structure according to a second embodiment of the present application.

Fig. 3 is a schematic diagram of signal transmission paths of a first electronic component and a second electronic component according to an embodiment of the present application.

Fig. 4A is a schematic diagram of a semiconductor package structure according to a third embodiment of the present application.

Fig. 4B is a schematic diagram of a semiconductor package structure according to a fourth embodiment of the present application.

Fig. 4C is a partial schematic view of a second conductive line structure in a semiconductor package structure according to an embodiment of the present application.

Fig. 5A is a schematic diagram of a semiconductor package structure according to a fifth embodiment of the present application.

Fig. 5B is a schematic diagram of a semiconductor package structure according to a sixth embodiment of the present application.

Fig. 6 is a partial schematic view of a semiconductor package structure according to a seventh embodiment of the present application.

Fig. 7A-7D are schematic top views according to various embodiments of the present application.

Fig. 8 a-8 k are formation steps provided in accordance with an embodiment of the present application to form the semiconductor package structure shown in fig. 2A.

Fig. 9 a-9 f illustrate formation steps provided in accordance with an embodiment of the present application to form the semiconductor package structure shown in fig. 2B.

Detailed Description

In order to better understand the spirit of the embodiments of the present application, the following description is given in conjunction with some preferred embodiments of the present application.

Embodiments of the present application will be described in detail below. Throughout the specification, the same or similar components and components having the same or similar functions are denoted by like reference numerals. The embodiments described herein with respect to the figures are illustrative in nature, are diagrammatic in nature, and are used to provide a basic understanding of the present application. The embodiments of the present application should not be construed as limiting the present application.

As used herein, the terms "substantially", "substantially" and "about" are used to describe and illustrate minor variations. When used in conjunction with an event or circumstance, the terms can refer to instances where the event or circumstance occurs precisely as well as instances where the event or circumstance occurs in close proximity.

In this specification, unless specified or limited otherwise, relative terms such as: the words "central," "longitudinal," "lateral," "front," "rear," "right," "left," "inner," "outer," "lower," "upper," "horizontal," "vertical," "above," "below," "top," "bottom," and derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," etc.) should be construed to refer to the orientation as then described in the discussion or as shown in the drawing. These relative terms are for convenience of description only and do not require that the present application be constructed or operated in a particular orientation.

For convenience in description, "first," "second," "third," and the like may be used herein to distinguish between different components of a figure or series of figures. "first," "second," "third," etc. are not intended to describe corresponding components.

The embodiment of the application provides a semiconductor packaging structure. Fig. 2A-2B show schematic diagrams of semiconductor package structures 1000 of different embodiments. Fig. 2A shows a structure diagram of a semiconductor package structure 1000-1 according to a first embodiment of the present application. Fig. 2B shows a block diagram of a semiconductor package structure 1000-2 according to a second embodiment of the present application. Referring to fig. 2A-2B in combination, the semiconductor package structure 1000 (semiconductor package structure 1000-1, semiconductor package structure 1000-2) includes a first electronic element 100, a second electronic element 200, and a first conductive line structure 300. The first electronic component 100 and the second electronic component 200 are disposed on the first lead structure 300, wherein the first electronic component 100 and the second electronic component 200 are spaced apart (spaced apart from each other in both the horizontal and vertical directions). The first electronic component 100 includes a first active surface 110, and the first active surface 110 is disposed toward the first conductive line structure 300. The second electronic component 200 includes a second active surface 210, and the second active surface 210 is disposed toward the first conductive line structure 300. The first conductive line structure 300 includes a trace 302 located under the first electronic component 100 and the second electronic component 200, the trace 302 is electrically connected to the first active surface 110 at one end and the second active surface 210 at the other end, and the first electronic component 100 and the second electronic component 200 are electrically connected through the trace 302. Wherein in the vertical direction the projection of the trace 302 is located within the first edge 115 of the first active surface 110. In some embodiments, the first electronic component 100 is a High Bandwidth Memory (HBM) die. In some embodiments, the second electronic component 200 is an Application Specific Integrated Circuit (ASIC) chip.

In the semiconductor package structure 1000 provided in the embodiment of the present application, the trace 302 electrically connecting the first electronic component 100 and the second electronic component 200 is located within the projection range of the first electronic component 100, i.e. not beyond the edge of the first electronic component 100, so that the trace 302 is free from the stress concentration at the chip gap in the prior art.

In some embodiments, a heat dissipation element 500 is disposed on the second electronic component 200 to provide heat dissipation for the second electronic component 200. In the horizontal direction, the heat dissipation element 500 is juxtaposed and spaced apart from the first electronic element 100, and a projection of the heat dissipation element 500 in the horizontal direction overlaps the first electronic element 100. A connection member 510 is provided between the heat dissipation member 500 and the second electronic component 200, and the heat dissipation member 500 is attached to the upper surface of the second electronic component 200 through the connection member 510. In some embodiments, the material of the heat dissipation element 500 includes metal. In some embodiments, the material of the heat dissipation element 500 may be stainless steel (SUS). In some embodiments, the connector 510 includes a Thermal Interface Material (TIM) through which heat generated by the second electronic component 200 can be more rapidly transferred to the heat dissipation component 500.

The first conductive line structure 300 is provided thereon with an underfill layer 600 encapsulating the second electronic component 200. In some embodiments, the underfill layer 600 surrounds only the sidewalls of the second electronic component 200 and the second active surface 210, as shown in fig. 2B. In some other embodiments, the underfill layer 600 is further disposed on the periphery of the first electronic element 100, surrounds the first active surface 110 of the first electronic element 100 and a part of the side edge of the first electronic element 100 facing away from the heat dissipation element 500, and fills the space between the first electronic element 100 and the heat dissipation element 500, as shown in fig. 2A. Wherein a portion of the underfill layer 600 between the electronic component 100 and the heat dissipation component 500 constitutes the spacer 550. The first electronic component 100 and the heat dissipation component 500 are spaced apart by a spacer 550. In the semiconductor package structure 1000 of the embodiment of the present application, the rigidity of the underfill layer 600 is less than that of the heat dissipation member 500. In some embodiments, the underfill layer 600 may be, for example, a Capillary Underfill (CUF).

The heat dissipation element 500 disposed above the second electronic component 200 for dissipating heat solves the problem that the second electronic component 200 is not easily disposed on the bottom layer for dissipating heat. Meanwhile, the elastic modulus (modulus) of the heat dissipation member 500 is higher than that of the spacer 550. In some embodiments, the heat dissipation element 500 is made of stainless steel with an elastic modulus of 193GPa, and the silicon material of the spacer 550 has an elastic modulus of 131GPa. The higher elastic modulus of the heat dissipation element 500 makes stress easier to concentrate at the heat dissipation element 500, and because the heat dissipation element 500 has stronger material rigidity, higher stress can be resisted, and meanwhile, the underfill layer 600 does not exist below the heat dissipation element 500, so that the problem of glue crack is avoided, the problems of fracture and damage inside the semiconductor packaging structure 1000 can be avoided due to the arrangement of the heat dissipation element 500, and the integrity of the semiconductor packaging structure 1000 is ensured.

The first conductive line structure 300 is further provided with a mold compound 700 encapsulating the first electronic element 100, the second electronic element 200 and the underfill layer 600. Wherein the mold compound 700 surrounds sidewalls of the first electronic component 100 and the heat dissipation member 500 and is further disposed between the first electronic component 100 and the first conductive line structure 300, the mold compound 700 surrounds the underfill layer 600 around the second electronic component 200. In the embodiment shown in fig. 2B, the molding compound 700 also fills the space between the first electronic component 100 and the heat dissipation component 500 and constitutes the spacer 550 in this embodiment. The top surface of the molding compound 700 is flush with the top surface of the first electronic component 100 and the top surface of the heat dissipation member 500. In the embodiment of the present application, the rigidity of the heat dissipation element 500 is greater than that of the molding compound 700 than that of the underfill layer 600.

The first electronic component 100 has a plurality of first interconnects 112 on the first active surface 110, and the first electronic component 100 is electrically connected to the first conductive line structure 300 through the first interconnects 112. Wherein the bottom surface of the first interconnection 112 is higher than the top surface of the second electronic element 200. A first conductive pillar 120 is disposed below the first interconnection 112, and the first conductive pillar 120 and the second electronic element 200 are juxtaposed in a horizontal direction. The first conductive pillar 120 has one end electrically connected to the first interconnection 112 and the other end connected to the first conductive line structure 300. The first electronic element 100 and the first conductive line structure 300 are electrically connected through the first interconnection 112 and the first conductive pillar 120 for signal transmission. Wherein the pitch (pitch) of the first conductive pillars 120 is greater than the pitch of the first interconnects 112. The thickness of the first conductive pillar 120 is greater than the thickness of the second electronic element 200. In some embodiments, the material of the first conductive pillar 120 includes copper.

A second conductive line structure 400 is further disposed between the first conductive pillar 120 and the first electronic element 100, wherein the second conductive line structure 400 extends to above the second electronic element 200. The second conductive line structure 400 includes an opening 410. The upper surface of the second electronic component 200 is exposed through the opening 410, and the connection member 510 is located within the opening 410. The sidewalls of the second conductive line structure 400 are flush with the sidewalls of the first conductive line structure 300.

The second electronic component 200 has a plurality of second interconnects 212 on the second active surface 210, and the second electronic component 200 is electrically connected to the first conductive line structure 300 through the second interconnects 212. The trace 302 in the first conductive line structure 300 has one end connected to the second interconnection 212 and the other end connected to the first conductive pillar 120 electrically connected to the first interconnection 112.

Fig. 3 is a diagram of fig. 2A, highlighting the first interconnect 112, the second interconnect 212 of fig. 2A. In some embodiments, the thickness H1 of the first interconnection 112 is 50 μm, the sum H2 of the thicknesses of the first conductive pillar 120 and the second conductive wire structure 400 is 100 μm, the thickness H3 of the second interconnection 212 is 40 μm, the distance W1 between the first conductive pillar 120 and the first edge 115 is 2380 μm, the distance W2 between the second interconnection 212 and the second edge 215 of the second electronic element 200 is 200 μm, the distance W3 between the first electronic element 100 and the heat dissipation element 500 is 100 μm, the distance W4 between the first edge 115 and the heat dissipation element 500 is 70 μm, and the transmission distance of signals between the first electronic element 100 and the second electronic element 200 can reach 2740 μm, compared with the prior art arrangement (e.g., 1 a) in which chips are arranged side by side, the embodiments of the present application dislocate the first electronic element 100 and the second electronic element 200 up and down, so that a portion of the second electronic element 200 is located below the first electronic element 100, the transmission distance of signals is 40 μm to 140 μm, thereby improving the signal transmission performance of the semiconductor package structure.

On the other hand, the first electronic component 100 and the second electronic component 200 of the present application are vertically displaced, and a portion of the second electronic component 200 is located below the first electronic component 100, so that stress at a corner of the first electronic component 100 facing the second electronic component 200 can be resisted. Meanwhile, the reduction of the distance between the first electronic component 100 and the second electronic component 200 in the horizontal direction reduces the size of the semiconductor package structure 1000 in the horizontal direction, for example, reduces the area size, which is more beneficial to the miniaturization of the semiconductor package structure 1000.

In some embodiments, as shown in fig. 4A-4B, the second conductive line structure 400 completely covers the second electronic component 200, and is not provided with the opening 410 exposing the second electronic component 200 as shown in fig. 2A to 3. Fig. 4A shows a block diagram of a semiconductor package structure 1000-3 according to a third embodiment of the present application. Fig. 4B shows a block diagram of a semiconductor package structure 1000-4 according to a fourth embodiment of the present application. In the embodiment shown in fig. 4A, compared with the embodiment shown in fig. 2A, the arrangement is the same except for the second conductive line structure 400. The embodiment shown in fig. 4B is identical to the embodiment shown in fig. 2B except for the second conductive line structure 400. The second conductive line structure 400 includes a dielectric layer 420 and a second conductive pillar 220. One end of the second conductive pillar 220 is exposed through the top surface of the second conductive line structure 400, and is connected to the connecting component 510 above the second conductive line structure 400, and the other end is connected to the second electronic component 200. In some embodiments, the second conductive pillars 220 are used for heat dissipation of the second electronic element 200. In some embodiments, the second conductive line structure 400 further includes a seed layer 250 disposed between the second conductive pillar 220 and the second electronic element 200, as shown in fig. 4C. The seed layer 250 is located between the second conductive pillar 220 and the upper surface (passive surface) of the second electronic element 200, and the second conductive pillar 220 is connected to the second electronic element 200 through the seed layer 250. In some embodiments, the material of the second conductive pillar 220 includes copper. In some embodiments, the material of the dielectric layer 420 includes Polyimide (PI).

In some embodiments, more of the second electronic component 200 extends below the first electronic component 100 than the embodiment shown in fig. 4A-4B, as shown in fig. 5A-5B. Fig. 5A shows a schematic structural diagram of a semiconductor package structure 1000-5 according to a fifth embodiment of the present application. Fig. 5B shows a schematic structural diagram of a semiconductor package structure 1000-6 according to a sixth embodiment of the present application. Wherein the second edge 215 of the second electronic component 200 does not exceed the third edge 117 of the first electronic component 100 opposite the first edge 115.

In some other embodiments, the semiconductor package structure 1000 further includes leads 800, as shown in fig. 6. Lead 800 is located between first conductive pillar 120 and second electronic element 200, and is horizontally spaced from first conductive pillar 120 and second electronic element 200. The lead 800 has one end connected to the first conductive line structure 300 and the other end connected to the second conductive line structure 400, and is electrically connected to the first conductive line structure 300 and the second conductive line structure 400. Wherein no seed layer is present between the wires 800 and the first wire structure 300. In some embodiments, the wire diameter of the lead 800 may be 17.5 μm and the pitch may be 50 μm. In some embodiments, the pitch of leads 800 is less than the pitch of first conductive pillars 120.

The lead 800 can be directly electrically connected to the first wire structure 300 and the second wire structure 400, and the pitch of the lead 800 is smaller, so as to shorten the transmission path of the first electronic element 100 and the second electronic element 200 and increase the signal transmission speed therebetween. In some embodiments, the deviation in the horizontal direction of the top and bottom ends of the lead 800 is no more than 0.028mm.

In the semiconductor package structure 1000, the number and arrangement of the first electronic element 100 and the second electronic element 200 can be adjusted according to actual requirements. Fig. 2A to 5B are only sectional views, and do not show the actual number of the first and second electronic components 100 and 200, and the heat dissipation member 500. In some embodiments, fig. 7A to 7D illustrate top views of a semiconductor package structure 1000 according to embodiments of the present application, in which an arrangement of a first electronic element 100 and a heat dissipation element 500 is illustrated, and a second electronic element 200 is located below the heat dissipation element 500 (not illustrated in fig. 7A to 7D), and embodiments of the present application are not limited to the arrangement illustrated in fig. 7A to 7D.

In the embodiment of the present application, the first electronic element 100 and the second electronic element 200 are vertically displaced, so that the portion of the second electronic element 200 is located below the first electronic element 100, thereby dispersing stress to avoid the problems of cracking, delamination, and the like of the semiconductor package structure 1000, and controlling the warpage of the semiconductor package structure 1000 within a range of ± 100 μm. While the partially over-lapping integrated mode interconnect of the first and second electronic components 100, 200 of the present application performs better (faster signal transmission) and is less costly (without the need to provide a large pitch between the first and second electronic components 100, 200) than, for example, the 2.5D Molded integrated circuit (2.5D Molded IC) shown in fig. 1 a. And the horizontal dimension of the semiconductor package structure 1000 provided by the embodiment of the present application may exceed, for example, 830mm2. The semiconductor package structure 1000 provided by the embodiment of the application can be applied to a display card such as a fan-out chip on substrate (FOCOS), a 5G Network Server (5G Network Server), and the like.

Embodiments of the present application also provide methods of forming semiconductor package structures 1000. A method for forming the semiconductor package structure 1000 is described with reference to fig. 8a to 8k and fig. 9a to 9 f. Fig. 8 a-8 k illustrate formation steps for forming the semiconductor package structure 1000-1 shown in fig. 2A. Fig. 9 a-9 f illustrate formation steps to form the semiconductor package structure 1000-2 shown in fig. 2B.

Referring to fig. 8a, a first conductive line structure 300 is provided. Wherein. The first conductive line structure 300 is disposed on the carrier 702, and the first conductive pillar 120 is disposed on the first conductive line structure 300. In some embodiments, the material of the first conductive pillar 120 includes copper. In some embodiments, carrier 702 comprises a glass carrier.

Referring to fig. 8b, the second electronic component 200 is disposed on the first conductive line structure 300, and a first underfill 610 is filled between the bottom of the second electronic component 200 and the first conductive line structure 300 such that the bottom and a portion of the sidewalls of the second electronic component 200 are surrounded by the first underfill 610. The second electronic element 200 and the first conductive pillar 120 are arranged in parallel and at an interval in the horizontal direction, and the active surface 210 of the second electronic element 200 faces the first conductive line structure 300. In some embodiments, the second electronic component 200 comprises an ASIC.

Referring to fig. 8c, a molding process is performed to form a first molding 710 encapsulating the second electronic element 200, the first underfill 610 and the first conductive pillar 120 on the first conductive line structure 300. Wherein a top surface of the first mold 710 is higher than a top surface of the second electronic component 200.

Referring to fig. 8d, a planarization process (e.g., a grinding process) is performed to planarize the first molding 710, the second electronic element 200, and the first underfill 610 until the top surfaces of the first conductive pillars 120 are exposed. Wherein the planarized first mold 710 is flat and coplanar with the top surface of the second electronic element 200.

Referring to fig. 8e, a patterned second conductive line structure 400 is formed over the first mold 710 and the second electronic element 200. The second conductive line structure 400 includes an opening 410 exposing the upper surface of the second electronic component 200.

With continued reference to fig. 8f, the first electronic element 100 is disposed on the second conductive line structure 400 above the first conductive pillar 120, and the heat dissipation element 500 is disposed above the opening 410, and the second underfill 620 is filled between the bottom of the first electronic element 100 and the second conductive line structure 400, such that part of the sidewall and the bottom of the first electronic element 100 are surrounded by the second underfill 620, and the second underfill 620 fills the space between the first electronic element 100 and the heat dissipation element 500. The first electronic component 100 and the heat dissipation component 500 are laterally juxtaposed and spaced apart. The active surface 110 of the first electronic component 100 faces the first conductive line structure 300. The heat dissipation member 500 is attached to the upper surface of the second electronic component 200 by a connector 510. In some embodiments, the material of the heat dissipation element 500 includes metal. In some embodiments, the material of the heat dissipation element 500 may be stainless steel (SUS). In some embodiments, the connection 510 includes a Thermal Interface Material (TIM). In the present embodiment, the first underfill 610 and the second underfill 620 together constitute the underfill layer 600 in the finally formed semiconductor package structure 1000-1.

Referring next to fig. 8g, a second mold 720 encapsulating the first electronic component 100, the heat dissipation element 500, and the second underfill 620 is formed. The second mold member 720 is positioned on the second lead structure 400, surrounding the tops of the first electronic component 100 and the heat dissipation member 500 and surrounding sidewalls of the first electronic component 100 and the heat dissipation member 500, which are not surrounded by the second filler 620. The first molding part 710 and the second molding part 720 together constitute a molding compound 700 in the finally formed semiconductor package structure 1000-1.

Referring to fig. 8h, a de-bonding process is performed to separate the carrier 702 from the first conductive line structure 300, so as to obtain a first structure 730.

Referring to fig. 8i, the first structure 730 is inverted to dispose the solder ball 705 on the first wire structure 300, resulting in a second structure 740. In some embodiments, the solder balls 705 may be formed by a controlled collapse chip attach process (C4 solder process). In some other embodiments, the solder balls 705 may also be formed by a Physical Vapor Deposition (PVD) process.

Referring to fig. 8j, the second structure 740 is fixed by being placed upside down on the first tape 707, and then the second molding member 720 is planarized. Wherein the first tape 707 serves to prevent the displacement of the second structure 740 when the second molding 720 is planarized. The top surface of the planarized second mold 720 is flush with the top surface of the first electronic component 100 and the top surface of the heat dissipation member 500, and the first electronic component 100 and the heat dissipation member 500 are exposed through the second mold 720. In some embodiments, the second molding 720 may be planarized by a grinding process.

Referring to fig. 8k, the third structure 750 obtained in fig. 8j is debonded from the first adhesive tape 707 and inverted on the second adhesive tape 709, and then a plurality of third structure 750 components at a wafer level (wafer level) are separated into a plurality of individual third structures 750 through, for example, a dicing (saw) process, so as to obtain the semiconductor package structure 1000-1 shown in fig. 2A. The second adhesive tape 709 is used to fix components of the plurality of third structures 750, so that the plurality of third structures 750 are sequentially separated in a relatively fixed position state, and undesired situations such as separation and scattering of the third structures 750 are avoided when the plurality of third structures 750 are separated.

A method of forming the semiconductor package structure 1000-2 is described with reference to fig. 9 a-9 f. In which, the steps of forming the semiconductor package structure 1000-2 can refer to the steps of forming the semiconductor package structure 1000-1. For example, after the formation steps of fig. 8 a-8 e, the steps of fig. 9 a-9 f are performed to form a semiconductor package structure 1000-2.

Referring to fig. 9a, the first electronic element 100 is disposed at the second conductive line structure 400 above the first conductive pillar 120, and the heat dissipation element 500 is disposed at the opening 410, wherein the first electronic element 100 and the heat dissipation element 500 are laterally juxtaposed and spaced apart. And the heat dissipation member 500 is attached to the upper surface of the second electronic component 200 by the connection member 510.

Referring next to fig. 9b, a second molding part 720 encapsulating the first electronic component 100 and the heat dissipation element 500 is formed. Wherein the second mold 720 surrounds the bottom of the first electronic component 100 and the sidewalls of the first electronic component 100 and the heat dissipation component 500, and fills the space between the first electronic component 100 and the heat dissipation component 500. The first molding part 710 and the second molding part 720 together constitute a molding compound 700 in the finally obtained semiconductor package structure 1000. The first underfill 610 forms the underfill layer 600 in the resulting semiconductor package structure 1000.

Referring to fig. 9c, similar to the step shown in fig. 8h, a de-bonding process is performed to separate the carrier 702 from the first conductive line structure 300, so as to obtain a first structure 730.

Referring to fig. 9d, similar to the step shown in fig. 8i, a solder ball 705 is disposed on the first wire structure 300 by, for example, a C4 soldering process or a PVD process, resulting in a second structure 740.

Referring to fig. 9e, similar to the step shown in fig. 8j, the second mold member 720 is planarized such that the top surface of the second mold member 720 is flush with the top surface of the first electronic component 100 and the top surface of the heat dissipation member 500.

Referring to fig. 9f, a third structure 750 is singulated by, for example, a dicing process, similar to the step shown in fig. 8j, resulting in the semiconductor package structure 1000-2 shown in fig. 2B.

In the method for forming the semiconductor package structure 1000-2, the first electronic element 100 and the heat dissipation element 500 are directly packaged by the second molding member 720, so that the process steps are simplified, and cost control is facilitated.

The steps of forming the semiconductor package 1000 shown in fig. 4A-4B may refer to the implementation steps shown in fig. 8 a-8 k and fig. 9 a-9 f. Except that in the step of forming the second conductive line structure 400, the opening 410 exposing the second electronic element 200 is not required to be formed through a patterning process. Therefore, the forming method also has the advantages of simplifying process steps and saving cost.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims (10)

1. A semiconductor package, comprising:

a first conductive line structure;

a first electronic element located on the first wire structure, a first active surface of the first electronic element facing the first wire structure;

a second electronic element; a second conductive line structure on the second active surface of the second electronic component, the second conductive line structure having a second conductive layer;

wherein the first wire structure comprises a trace located below the first active face and the second active face, the trace electrically connecting the first electronic element and the second electronic element, a projection of the entire trace in the longitudinal direction being located within an edge of the first active face.

2. The semiconductor package structure of claim 1, further comprising:

and the heat dissipation element is positioned on the second electronic element and positioned on one side of the first electronic element in the horizontal direction.

3. The semiconductor package structure of claim 2, further comprising:

and the underfill layer encapsulates the second electronic element.

4. The semiconductor package structure of claim 3, wherein the underfill layer further encapsulates at least a portion of the first electronic component, the underfill layer filling a space between the first electronic component and the heat spreading component.

5. The semiconductor package structure of claim 3 or 4, further comprising:

a mold compound encapsulating the underfill layer, the first electronic element, and the second electronic element and covering the traces, the mold compound having a rigidity greater than a rigidity of the underfill layer.

6. The semiconductor package structure of claim 2, wherein the first electronic component has a plurality of first interconnects on the first active surface electrically connecting the first wire structures, the first interconnects having top surfaces higher than top surfaces of the second electronic components.

7. The semiconductor package structure of claim 6, further comprising:

the first conductive pillar is located on one side of the second electronic element and located below the first interconnection, the first conductive pillar is electrically connected with the first interconnection, and the thickness of the first conductive pillar is larger than that of the second electronic element.

8. The semiconductor package structure of claim 7, further comprising:

and a second conductive line structure located above the first conductive pillar and the second electronic element, the second conductive line structure being located between the first electronic element and the first conductive pillar.

9. The semiconductor package structure of claim 8, wherein the second conductive line structure comprises an opening exposing an upper surface of the second electronic component, and the heat dissipation element is attached to the upper surface of the second electronic component.

10. The semiconductor package structure of claim 8, further comprising:

a lead between the first conductive pillar and the second electronic element, the lead electrically connecting the second conductive line structure and the first conductive line structure, the lead and the first conductive line structure not including a seed layer therebetween.

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