CN114068479A - Semiconductor package structure and manufacturing method thereof - Google Patents

Semiconductor package structure and manufacturing method thereof Download PDF

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Publication number
CN114068479A
CN114068479A CN202111371454.6A CN202111371454A CN114068479A CN 114068479 A CN114068479 A CN 114068479A CN 202111371454 A CN202111371454 A CN 202111371454A CN 114068479 A CN114068479 A CN 114068479A
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electronic element
semiconductor package
layer
package structure
redistribution layer
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吕文隆
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/54—Providing fillings in containers, e.g. gas fillings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/8121—Applying energy for connecting using a reflow oven

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

In the process of bonding the second electronic element to the redistribution layer, the solder on the second electronic element is in a non-aligned state with the pad of the redistribution layer, and when reflow processing is performed, the second electronic element is close to the first electronic element due to the cohesive force of the solder until the side wall of the second electronic element is attached to the side wall of the first electronic element, so that no gap exists between the first electronic element and the second electronic element, no underfill material exists between the first electronic element and the second electronic element, and the gap position between the first electronic element and the second electronic element is replaced by the second electronic element with higher rigidity, so that the fracture problem caused by thermal stress is solved.

Description

Semiconductor package structure and manufacturing method thereof
Technical Field
The disclosure relates to the technical field of semiconductors, and particularly relates to a semiconductor packaging structure and a manufacturing method thereof.
Background
In the FOCoS (Fan-Out Chip on Substrate) structure, the underfill material under the die gap during Thermal cycling cannot release Thermal stress due to CTE (Coefficient of Thermal Expansion) mismatch among multiple materials in the whole semiconductor package structure, so that the crack (crack) in the area under the die gap in the redistribution layer is caused. If a stiffener is added to the redistribution layer to block the fracture path, the stress may extend toward the sidewalls of the stiffener, causing delamination between the sidewalls of the stiffener and the underfill.
Disclosure of Invention
The present disclosure provides a semiconductor package structure and a method of manufacturing the same.
In a first aspect, the present disclosure provides a semiconductor package structure, including:
a rewiring layer;
and the first electronic element and the second electronic element are arranged on the rewiring layer side by side and are electrically connected with the rewiring layer, and the side wall of the first electronic element is contacted with the side wall of the second electronic element.
In some alternative embodiments, the sidewalls of the first electronic element or the sidewalls of the second electronic element comprise a buffer layer.
In some optional embodiments, further comprising:
and the first filling material is filled among the first electronic element, the second electronic element and the rewiring layer.
In some alternative embodiments, the buffer layer has a rigidity greater than that of the first filler material.
In some alternative embodiments, a barrier layer is disposed between the buffer layer and the first/second electronic element.
In some alternative embodiments, the second electronic component is electrically connected to the redistribution layer through a first interconnect structure.
In some alternative embodiments, the first interconnect structure is a solder element.
In some alternative embodiments, a center of the upper surface of the first interconnect structure is on a different vertical plane than a center of the lower surface of the first interconnect structure.
In some alternative embodiments, a side surface of the first interconnect structure is inclined with respect to an upper surface of the redistribution layer.
In some alternative embodiments, the first electronic component is an application specific integrated circuit chip and the second electronic component is a high bandwidth memory chip; or
The second electronic component is an application specific integrated circuit chip and the first electronic component is a high bandwidth memory chip.
In some optional embodiments, further comprising:
and the molding sealing layer is used for coating the first electronic element and the second electronic element.
In some optional embodiments, further comprising:
the substrate, the rewiring layer is located on the substrate.
In some alternative embodiments, the substrate has a recess.
In some optional embodiments, further comprising:
and the bridge chip is arranged in the concave part, and the bridge chip is electrically connected with the first electronic element and the second electronic element.
In some optional embodiments, further comprising:
and the second filling material is filled between the concave part and the bridge chip.
In some optional embodiments, the bridge chip includes a first bridge line.
In some optional embodiments, the bridge chip is electrically connected to the first electronic element and the second electronic element through the redistribution layer.
In some optional embodiments, the redistribution layer further comprises:
and the second bridging line is positioned below the gap between the first electronic element and the second electronic element.
In some alternative embodiments, the first electronic component is electrically connected to the redistribution layer through a second interconnect structure.
In some alternative embodiments, the second interconnect structure is a pad, a conductive pillar, a solder, or a wire.
In a second aspect, the present disclosure provides a method for manufacturing a semiconductor package structure, including:
forming a rewiring layer;
bonding a first electronic component to the redistribution layer;
placing a second electronic element with a first interconnection structure on the redistribution layer, wherein the first interconnection structure and a pad of the redistribution layer are in a non-aligned state, and the second electronic element is arranged side by side with the first electronic element;
and performing reflow treatment, namely aligning and bonding the second electronic element to the bonding pad of the redistribution layer, and moving the second electronic element to a direction close to the first electronic element until the side wall of the first electronic element is contacted with the side wall of the second electronic element.
In some optional embodiments, before the forming the redistribution layer, the method further includes:
providing a substrate; and
the forming of the redistribution layer includes:
forming the redistribution layer on the substrate.
In some optional embodiments, the redistribution layer comprises a second bridging line located below a gap between the first and second electronic components.
In some optional embodiments, after the providing the substrate, further comprising:
providing a recess on the substrate;
and arranging a bridge chip in the concave part, wherein the bridge chip comprises a first bridge circuit.
In the process of bonding the second electronic element to the redistribution layer, the solder on the second electronic element is in a non-aligned state with the pad of the redistribution layer, and when reflow processing is performed, the second electronic element is close to the first electronic element due to the cohesive force of the solder until the side wall of the second electronic element is attached to the side wall of the first electronic element, so that no gap exists between the first electronic element and the second electronic element, no underfill material exists between the first electronic element and the second electronic element, and the gap position between the first electronic element and the second electronic element is replaced by the second electronic element with higher rigidity, so that the fracture problem caused by thermal stress is solved.
Drawings
Other features, objects and advantages of the disclosure will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
fig. 1 to 6 are first to sixth schematic structural views of a semiconductor package structure according to an embodiment of the present disclosure;
fig. 7 to 18 are schematic structural views in the manufacturing process of the semiconductor package structure according to the embodiment of the present disclosure.
Description of the symbols:
1-first electronic element, 2-second electronic element, 3-rewiring layer, 31-second bridging line, 4-first filler, 5-barrier layer, 6-first interconnection structure, 7-molding layer, 8-substrate, 81-recess, 9-bridging chip, 91-first bridging line, 92-wafer, 921-crystal grain, 93-adhesive layer, 94-insulating layer, 95-seed layer, 10-second filler, 11-second interconnection structure, 12-external electrical connector, 13-buffer layer.
Detailed Description
The following description of the embodiments of the present disclosure will be provided in conjunction with the accompanying drawings and examples, and those skilled in the art can easily understand the technical problems and effects of the present disclosure. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. In addition, for convenience of description, only portions related to the related invention are shown in the drawings.
It should be noted that the structures, proportions, and dimensions shown in the drawings and described in the specification are for the understanding and reading of the present disclosure, and are not intended to limit the conditions under which the present disclosure can be implemented, so they are not technically significant, and any modifications of the structures, changes in the proportions and adjustments of the dimensions should be made without affecting the efficacy and attainment of the same. In addition, the terms "above", "first", "second" and "a" as used herein are for the sake of clarity only, and are not intended to limit the scope of the present disclosure, and changes or modifications of the relative relationship may be made without substantial changes in the technical content.
It should be readily understood that the meaning of "in.. on," "over,", and "above" in this disclosure should be interpreted in the broadest sense such that "in.. on" not only means "directly on something," but also means "on something" including an intermediate member or layer between the two.
Furthermore, spatially relative terms, such as "below," "lower," "over," "upper," and the like, may be used in this disclosure to describe one element or component's relationship to another element or component as illustrated in the figures for ease of description. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 ° or at other orientations) and the spatially relative descriptors used in this disclosure interpreted accordingly as such.
In addition, the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
Fig. 1 is a first structural schematic diagram of a semiconductor package structure according to an embodiment of the present disclosure. As shown in fig. 1, the semiconductor package structure includes a redistribution layer 3, a first electronic element 1, a second electronic element 2, a buffer layer 13, a first filler 4, and a substrate 8. The first electronic component 1 and the second electronic component 2 are arranged side by side on the redistribution layer 3 and are electrically connected with the redistribution layer 3. The sidewalls of the first electronic component 1 may contact the sidewalls of the second electronic component 2. The rewiring layer 3 may be provided on the substrate 8. The sidewalls of the first electronic component 1 or the sidewalls of the second electronic component 2 may include a buffer layer 13.
In the present embodiment, the first electronic element 1 may be electrically connected to the rewiring layer 3 through the second interconnect structure 11. The second electronic element 2 may be electrically connected to the rewiring layer 3 through the first interconnect structure 6. The first interconnect structure 6 may be a solder element. The side face of the first interconnect structure 6 may be inclined with respect to the upper surface of the rewiring layer 3. The center of the upper surface of the first interconnect structure 6 may be in a different vertical plane than the center of the lower surface of the first interconnect structure 6. The longitudinal cross-section of the first interconnect structure 6 may be in the form of a parallelogram. The structural features of the first interconnect structure 6 may be formed by a reflow process during the manufacturing process. In the manufacturing process, the first interconnection structure 6 of the second electronic component 2 and the pad of the redistribution layer 3 are in a non-aligned state (a relatively offset position), and when reflow processing is performed, the second electronic component 2 moves in the direction of the first electronic component 1 due to the cohesive force of the solder, so that the first interconnection structure 6 is deformed and is inclined with respect to the upper surface of the redistribution layer 3. In addition, the second interconnect structure 11 may also have the same structural features as the first interconnect structure 6 (refer to fig. 3).
In this embodiment, the first filling material 4 may be filled between the first electronic element 1, the second electronic element 2 and the redistribution layer 3. The first filler 4 can fill the gap between the three materials, so as to improve the overall structural strength.
In this embodiment, the buffer layer 13 may cover the second electronic element 2, or conversely, the buffer layer 13 may cover the first electronic element 1, so that the buffer layer 13 may protect the first electronic element 1 or the second electronic element 2. The buffer layer 13 may employ a non-metallic material such as an organic material such as Polyimide (PI), epoxy, acrylic, a molding compound, or the like, and an inorganic material such as oxide (SiOx, SiNx, TaOx), glass, silicon, ceramic, or the like. The rigidity of the buffer layer 13 may be greater than the rigidity of the first filler 4. A buffer layer 13 having high rigidity is provided between the first electronic component 1 and the second electronic component 2, whereby deformation and fracture can be resisted.
In the present embodiment, the external electrical connectors 12 may be solder balls, Ball Grid Array (BGA) balls, controlled collapse chip connection (C4) bumps, or micro bumps, for example.
In this embodiment, the substrate 8 may include fibers to improve the strength and support of the substrate 8, thereby improving the stability of the overall structure.
In the present embodiment, the second bridge line 31 in the rewiring layer 3 may be located below the gap between the first electronic component 1 and the second electronic component 2. The material of the second bridge line 31 in the rewiring layer 3 is, for example, copper (Cu), silver (Ag), gold (Au), aluminum (Al), nickel (Ni), titanium (Ti), lead (Pb), or the like.
Fig. 2 is a second structural schematic diagram of a semiconductor package structure according to an embodiment of the disclosure. The difference from the semiconductor package structure shown in fig. 1 is that the substrate 8 in the semiconductor package structure shown in fig. 2 may have a concave portion 81 and may further include a bridge chip 9 disposed in the concave portion 81 and a second filling material 10 filled between the concave portion 81 and the bridge chip 9.
In the present embodiment, the recess 81 may be in the form of a through hole or a blind hole of various shapes, or the like. The recess 81 can provide a receiving space for the bridge chip 9, reducing the thickness of the entire structure. The second filling material 10 can fill the gap between the concave portion 81 and the bridge chip 9, and thus the stability of the entire structure can be enhanced.
The semiconductor package structure shown in fig. 1 is different from the semiconductor package structure shown in fig. 2 in that the bridge chip 9 in the semiconductor package structure shown in fig. 2 may include a first bridge line 91, and the bridge chip 9 may be electrically connected to the first electronic component 1 and the second electronic component 2 through the redistribution layer 3. That is, the semiconductor package shown in fig. 1 is fabricated with the bridge circuit design in the redistribution layer, while the semiconductor package shown in fig. 2 is fabricated with the bridge circuit disposed in the bridge chip.
Fig. 3 is a third structural schematic diagram of a semiconductor package structure according to an embodiment of the disclosure. The difference from the semiconductor package structure shown in fig. 2 is that the semiconductor package structure shown in fig. 3 may further include a barrier layer 5. The barrier layer 5 may be provided between the buffer layer 13 and the first/second electronic element 1/2. The barrier layer 5 may employ a non-metallic material such as an organic material such as Polyimide (PI), epoxy, acrylic, a molding compound, etc., and an inorganic material such as oxide (SiOx, SiNx, TaOx), glass, silicon, ceramic, etc. The barrier layer 5 may be made of the same material as the buffer layer 13 or may be made of a material having higher rigidity than the buffer layer 13, whereby the fracture resistance can be further improved. In addition, the distance over which the second electronic component 2 is displaced during the reflow process can be better controlled and compensated for by the design of the barrier layer 5. When the second electronic component 2 is attached to the barrier layer 5, a gap between the first electronic component 1 and the second electronic component 2 can be avoided.
Fig. 4 is a fourth structural schematic diagram of a semiconductor package structure according to an embodiment of the present disclosure. Fig. 5 is a fifth structural schematic diagram of a semiconductor package structure according to an embodiment of the disclosure. Fig. 2, 4 and 5 show different embodiments of the second interconnect structure 11. The second interconnect structure 11 in the semiconductor package structure shown in fig. 2 may be a conductive pillar and a solder element. The second interconnect structure 11 in the semiconductor package structure shown in fig. 4 may be a pad and a solder element. The second interconnect structure 11 in the semiconductor package structure shown in fig. 5 may be a wire, i.e., the second electronic element 2 is bonded to the redistribution layer 3 by wire bonding.
Fig. 6 is a sixth structural schematic of a semiconductor package structure according to an embodiment of the present disclosure. The semiconductor package structure shown in fig. 2 is different in that the semiconductor package structure shown in fig. 6 may further include a mold sealing layer 7. The mold seal 7 may encapsulate the first and second electronic components 1 and 2. The molding material used for the molding layer 7 may include Epoxy resin (Epoxy resin), Filler (Filler), Catalyst (Catalyst), Pigment (Pigment), Release Agent (Release Agent), Flame Retardant (Flame Retardant), Coupling Agent (Coupling Agent), Hardener (hardner), Low Stress absorbent (Low Stress Absorber), Adhesion Promoter (Adhesion Promoter), Ion Trapping Agent (Ion Trapping Agent), and the like. The mold sealing layer 7 may function to fix the first electronic component 1 and the second electronic component 2.
Fig. 7 to 18 are schematic structural views in the manufacturing process of the semiconductor package structure according to the embodiment of the present disclosure.
Referring to fig. 7, a wafer 92 is provided, an adhesive layer 93 is disposed on one side of the wafer 92, and an insulating layer 94, a seed layer 95 and a first bridge circuit 91 are sequentially disposed on the other side of the wafer 92.
Here, the adhesive layer 93 may be a Die Attach Film (DAF).
Referring to fig. 8, the wafer 92 is diced.
Referring to fig. 9, a plurality of dies 921(Die) are formed, resulting in a plurality of bridge chips 9.
Referring to fig. 10, a substrate 8 is provided. A recess 81 is formed in the substrate 8.
Here, the concave portion 81 may be formed by a process such as laser or etching.
Referring to fig. 11, the bridge chip 9 in fig. 9 is picked up and placed in the recess 81 of the substrate 8.
Referring to fig. 12, the second filling material 10 is filled between the concave portion 81 and the bridge chip 9.
Referring to fig. 13, a redistribution layer 3 is formed on a substrate 8.
The redistribution layer 3 may be formed by a currently known or future developed technology, which is not specifically limited in the present disclosure, and for example, the redistribution layer 3 may be formed by photolithography, electroplating (plating), Electroless plating (electroplating), and the like.
Referring to fig. 14, the first electronic component 1 is soldered to the redistribution layer 3. Specifically, it may be soldered onto the rewiring layer 3 through the second interconnect structure 11 on the first electronic component 1.
Referring to fig. 15, the second electronic component 2 having the first interconnect structure 6 is placed above the redistribution layer 3, and the pads of the first interconnect structure 6 and the redistribution layer 3 are in a non-aligned state, so that the second electronic component 2 and the first electronic component 1 can be arranged side by side.
Referring to fig. 16, a reflow process aligns and bonds the second electronic component 2 to the pad of the redistribution layer 3, and moves the second electronic component 2 toward the first electronic component 1 until the sidewall of the first electronic component 1 contacts the sidewall of the second electronic component 2. And obtaining the semiconductor packaging structure.
Referring to fig. 17, a first filling material 4 is filled between the first electronic component 1, the second electronic component 2 and the redistribution layer 3.
Referring to fig. 18, a semiconductor package structure is obtained.
In the process of bonding the second electronic element 2 to the redistribution layer 3, firstly, the solder on the second electronic element 2 and the pad of the redistribution layer 3 are in a non-aligned state, and then when reflow processing is performed, the second electronic element 2 is close to the first electronic element 1 due to the cohesive force of the solder until the side wall of the second electronic element 2 is attached to the side wall of the first electronic element 1, so that no gap exists between the first electronic element 1 and the second electronic element 2, no underfill material exists between the first electronic element 1 and the second electronic element 2, and the gap position between the first electronic element 1 and the second electronic element 2 is replaced by the second electronic element 2 with higher rigidity, so that the problem of fracture caused by thermal stress is solved.
While the present disclosure has been described and illustrated with reference to particular embodiments thereof, such description and illustration are not intended to limit the present disclosure. It will be clearly understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not be drawn to scale. There may be a difference between the technical reproduction in the present disclosure and the actual device due to variables in the manufacturing process and the like. There may be other embodiments of the disclosure that are not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to fall within the scope of the claims appended hereto. Although the methods disclosed in this disclosure have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated in the present disclosure, the order and grouping of the operations is not a limitation of the present disclosure.

Claims (10)

1. A semiconductor package structure, comprising:
a rewiring layer;
and the first electronic element and the second electronic element are arranged on the rewiring layer side by side and are electrically connected with the rewiring layer, and the side wall of the first electronic element is contacted with the side wall of the second electronic element.
2. The semiconductor package structure of claim 1, wherein a sidewall of the first electronic element or a sidewall of the second electronic element comprises a buffer layer.
3. The semiconductor package structure of claim 2, further comprising:
and the first filling material is filled among the first electronic element, the second electronic element and the rewiring layer.
4. The semiconductor package structure of claim 3, wherein the buffer layer has a rigidity greater than a rigidity of the first filler material.
5. The semiconductor package structure of claim 2, further comprising:
and the barrier layer is arranged between the buffer layer and the first electronic element/the second electronic element.
6. The semiconductor package structure of claim 1, wherein the second electronic element is electrically connected to the redistribution layer through a first interconnect structure.
7. The semiconductor package structure of claim 6, wherein the first interconnect structure is a solder element.
8. The semiconductor package structure of claim 6, wherein a side of the first interconnect structure is sloped with respect to an upper surface of the redistribution layer.
9. The semiconductor package structure of claim 1, wherein the redistribution layer further comprises:
and the second bridging line is positioned below the gap between the first electronic element and the second electronic element.
10. The semiconductor package structure of claim 1, wherein the first electronic element is electrically connected to the redistribution layer through a second interconnect structure.
CN202111371454.6A 2021-11-18 2021-11-18 Semiconductor package structure and manufacturing method thereof Pending CN114068479A (en)

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