CN114050146A

CN114050146A - Semiconductor package structure and manufacturing method thereof

Info

Publication number: CN114050146A
Application number: CN202111293935.XA
Authority: CN
Inventors: 吕文隆
Original assignee: Advanced Semiconductor Engineering Inc
Current assignee: Advanced Semiconductor Engineering Inc
Priority date: 2021-11-03
Filing date: 2021-11-03
Publication date: 2022-02-15

Abstract

According to the semiconductor packaging structure and the manufacturing method thereof, the redistribution layer is directly arranged on the substrate, the groove is formed in the substrate, in addition, the functional chip and the bridge chip are combined in advance, and then the bridge chip is arranged in the groove, so that a conductive column manufacturing process and a mold sealing manufacturing process are not needed, and the yield is improved. In addition, the groove provides a placing space for the bridge chip, so that the thickness of the whole structure is reduced.

Description

Semiconductor package structure and manufacturing method thereof

Technical Field

The disclosure relates to the technical field of semiconductors, and particularly relates to a semiconductor packaging structure and a manufacturing method thereof.

Background

In some cases, the thickness of the entire structure includes the thickness of the substrate, the bridge Chip, and the functional Chip in a System-on-Chip (SOC) structure. In the manufacturing process, the conductive posts are required to be manufactured around the bridge chip to realize the connection between the substrate and the functional chip, and the process for manufacturing the conductive posts is easy to have the phenomenon of post falling, so that the yield of the process is low. Moreover, two molding processes are required to protect the structure (the conductive pillar, the bridge chip, and the functional chip), which makes the process complicated. In addition, due to the thinning process performed after the molding, stress is generated between the functional chips to generate cracks.

Disclosure of Invention

The present disclosure provides a semiconductor package structure and a method of manufacturing the same.

In a first aspect, the present disclosure provides a semiconductor package structure, including:

the circuit structure is provided with a groove and comprises a substrate and a rewiring layer arranged on the substrate;

the combined chip comprises a first chip, a second chip and a bridging chip, wherein the first chip and the second chip are arranged on the rewiring layer and are respectively positioned on two sides of the groove, and the bridging chip is arranged in the groove and is electrically connected with the first chip and the second chip.

In some optional embodiments, the combination chip further comprises:

and the first filling material is arranged among the bridge chip, the first chip and the second chip.

In some optional embodiments, the semiconductor package structure further comprises:

and the second filling material is arranged between the combined chip and the circuit structure.

In some alternative embodiments, the first filler material is in contact with the second filler material.

In some optional embodiments, the second filling material contacts a sidewall of the redistribution layer in the groove.

In some alternative embodiments, the second filler material contacts sidewalls of the substrate in the recess.

In some optional embodiments, a predetermined distance is provided between the bridge chip and the bottom surface of the second filling material.

In some alternative embodiments, the bridge chip is in contact with a bottom surface of the second filler material.

In some optional embodiments, the width of the redistribution layer is smaller than the width of the substrate.

In some optional embodiments, the side of the redistribution layer facing the groove is in a shape of a step.

and the first rewiring layer is arranged on the first chip and is electrically connected with the first chip.

and the second rewiring layer is arranged on the second chip and is electrically connected with the second chip.

and the third triple wiring layer is arranged on the bridging chip and is electrically connected with the bridging chip.

In some optional embodiments, the third rewiring layer is electrically connected to the first/second rewiring layer, which is electrically connected to the rewiring layer.

and the fourth rewiring layer is electrically connected with the rewiring layer and the bridging chip respectively, and a plurality of functional chips are arranged on the fourth rewiring layer.

a heat dissipation structure disposed on the first chip and the second chip.

In some alternative embodiments, the heat dissipating structure has at least one recess.

In a second aspect, the present disclosure provides a method for manufacturing a semiconductor package structure, including:

providing a combined chip and a circuit structure with a groove, wherein the combined chip comprises a first chip, a second chip and a bridging chip, and the circuit structure comprises a substrate and a heavy wiring layer arranged on the substrate;

and flip-chip bonding the combined chip on the rewiring layer, and placing the bridge chip in the groove.

In some alternative embodiments, the combined chip is pre-formed by:

providing the first chip and the second chip;

and flip-chip bonding the bridge chip on the first chip and the second chip to obtain the combined chip.

In some alternative embodiments, the line structure is pre-formed by:

forming a groove on the substrate;

and forming a rewiring layer on the substrate to obtain the circuit structure.

Drawings

Other features, objects and advantages of the disclosure will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:

fig. 1 to 4 are first to fourth schematic structural views of a semiconductor package structure according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram illustrating an interconnection manner between a bridge chip and a first chip/a second chip of a semiconductor package structure according to an embodiment of the disclosure;

fig. 6 to 9 are schematic structural diagrams in the manufacturing process of a circuit structure in a semiconductor package structure according to an embodiment of the disclosure;

fig. 10 to 13 are schematic structural views in the manufacturing process of a combined chip in a semiconductor package structure according to an embodiment of the present disclosure;

fig. 14 to 16 are schematic structural views in the manufacturing process of the semiconductor package structure according to the embodiment of the present disclosure.

Description of the symbols:

1-line structure, 11-substrate, 111-opening, 112-via hole, 12-rewiring layer, 13-groove, 2-combined chip, 21-first chip, 22-second chip, 23-bridging chip, 24-first filling material, 25-first rewiring layer, 26-second rewiring layer, 27-third rewiring layer, 28-interconnection structure, 281-solder, 282-conductive column, 3-second filling material, 41-fourth rewiring layer, 42-functional chip, 5-heat dissipation structure, 6-mold sealing layer, 7-external electrical connector.

Detailed Description

The following description of the embodiments of the present disclosure will be provided in conjunction with the accompanying drawings and examples, and those skilled in the art can easily understand the technical problems and effects of the present disclosure. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. In addition, for convenience of description, only portions related to the related invention are shown in the drawings.

It should be noted that the structures, proportions, and dimensions shown in the drawings and described in the specification are for the understanding and reading of the present disclosure, and are not intended to limit the conditions under which the present disclosure can be implemented, so they are not technically significant, and any modifications of the structures, changes in the proportions and adjustments of the dimensions should be made without affecting the efficacy and attainment of the same. In addition, the terms "above", "first", "second" and "a" as used herein are for the sake of clarity only, and are not intended to limit the scope of the present disclosure, and changes or modifications of the relative relationship may be made without substantial changes in the technical content.

It should be readily understood that the meaning of "in.. on," "over,", and "above" in this disclosure should be interpreted in the broadest sense such that "in.. on" not only means "directly on something," but also means "on something" including an intermediate member or layer between the two.

Furthermore, spatially relative terms, such as "below," "lower," "over," "upper," and the like, may be used in this disclosure to describe one element or component's relationship to another element or component as illustrated in the figures for ease of description. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 ° or at other orientations) and the spatially relative descriptors used in this disclosure interpreted accordingly as such.

In addition, the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Fig. 1 is a first structural schematic diagram of a semiconductor package structure according to an embodiment of the present disclosure. As shown in fig. 1, the semiconductor package structure includes a circuit structure 1, a composite chip 2, a second filling material 3, a heat dissipation structure 5, and an external electrical connector 7. Wherein the line structure 1 may have a recess 13. The wiring structure 1 may include a substrate 11 and a redistribution layer 12 provided on the substrate 11. The combined chip 2 may include a first chip 21, a second chip 22, a bridge chip 23, and a first filler 24. The first chip 21 and the second chip 22 may be provided on the rewiring layer 12 and located on both sides of the groove 13, respectively. The bridge chip 23 may be disposed in the recess 13 and electrically connect the first chip 21 and the second chip 22.

In this embodiment, the first chip 21 and the second chip 22 may be chips with various functions, and the first chip 21 may be, for example, a High Bandwidth Memory (HBM) chip. The second chip 22 may be, for example, an Application Specific Integrated Circuit (ASIC) chip.

In this embodiment, the first filling material 24 may be disposed between the bridge chip 23, the first chip 21 and the second chip 22. The first filler material 24 can increase the bonding strength between the chips in the combined chip 2. In addition, the first redistribution layer 25 may be disposed on the first chip 21, the second redistribution layer 26 may be disposed on the second chip 22, and the dielectric material of the first filling material 24 and the dielectric material of the first redistribution layer 25/the second redistribution layer 26 may be the same material, so that the first filling material 24 may serve as a buffer between the bridge chip 23 and the first redistribution layer 25/the second redistribution layer 26 to avoid the thermal expansion coefficient mismatch between the bridge chip 23 and the first redistribution layer 25/the second redistribution layer 26.

In this embodiment, the second filling material 3 may be disposed between the combined chip 2 and the circuit structure 1. The second filler 3 may be in contact with the first filler 24. The second filling material 3 may contact the sidewall of the redistribution layer 12 and the sidewall of the substrate 11 in the groove 13. Since the second filler 3 is filled between the combined chip 2 and the substrate 11, there is no direct contact between the combined chip 2 and the substrate 11, thereby avoiding stress generated by the direct contact.

In this embodiment, the side of the redistribution layer 12 facing the groove 13 may have a shape of a step. That is, the width of the rewiring layer 12 may be smaller than the width of the substrate 11. In the manufacturing process, in order to avoid the suspension state of the redistribution layer 12 (i.e. the width of the redistribution layer 12 is greater than that of the substrate 11), the whole structure is prevented from being unstable due to the unsupported redistribution layer 12. In addition, the outline of the redistribution layer 12 in the groove 13 can be matched with the outline of the first filling material 24, and the outline shape of the combined chip 2 can be better adapted.

In this embodiment, the substrate 11 may include fibers to improve the strength and support capability of the substrate 11, thereby improving the stability of the whole structure. The width of the recess 13 of the substrate 11 may be larger than the width of the bridge chip 23 to ensure that the recess 13 can accommodate the bridge chip 23. The recess 13 in the substrate 11 may provide space for placing the bridge chip 23, reducing the thickness of the overall structure.

In the present embodiment, the external electrical connection members 7 may be solder balls, Ball Grid Array (BGA) balls, controlled collapse chip connection (C4) bumps or micro bumps, for example.

In this embodiment, the heat dissipation structure 5 may be provided on the first chip 21 and the second chip 22. The heat dissipation structure 5 may perform a heat dissipation function, and may be a heat sink or other conductive material such as aluminum (Al), copper (Cu), chromium (Cr), tin (Sn), gold (Au), silver (Ag), nickel (Ni), stainless steel, or the like.

In some cases, the semiconductor package structure may further include a mold layer 6 covering the first chip 21, the second chip 22, and the heat dissipation structure 5.

Fig. 2 is a second structural schematic diagram of a semiconductor package structure according to an embodiment of the disclosure. With respect to the semiconductor package structure shown in fig. 1, the combined chip 2 of the semiconductor package structure shown in fig. 2 may further include a fourth rewiring layer 41 connected to the rewiring layer 12 and the bridge chip 23, respectively. A plurality of functional chips 42 may be connected to the fourth re-wiring layer 41, whereby the semiconductor package structure may integrate a larger number of chips.

Fig. 3 is a third structural schematic diagram of a semiconductor package structure according to an embodiment of the disclosure. In the semiconductor package structure shown in fig. 1, a predetermined distance may be provided between the bridge chip 23 and the bottom surface 31 of the second filling material 3. In the semiconductor package structure shown in fig. 3, the bridge chip 23 may directly contact the bottom surface 31 of the second filling material 3.

Fig. 4 is a fourth structural schematic diagram of a semiconductor package structure according to an embodiment of the present disclosure. The heat dissipation structure 5 in the semiconductor package structure shown in fig. 4 may have at least one recess 51, as compared to the semiconductor package structure shown in fig. 1, whereby the heat dissipation area may be increased, and the heat dissipation effect may be improved.

Fig. 5 is a schematic structural diagram of an interconnection manner between the bridge chip 23 and the first/

second chips

21 and 22 of the semiconductor package structure according to the embodiment of the disclosure. Taking the interconnection manner between the bridge chip 23 and the first chip 21 as an example, the bridge chip 23 may be provided with a third redistribution layer 27, and the first chip 21 may be provided with a first redistribution layer 25, as shown in fig. 5 (a), a pad of the third redistribution layer 27 and a pad of the first redistribution layer 25 may be directly interconnected. As shown in fig. 5 (b), the interconnect structure 28 may include solder, and then the pad of the third redistribution layer 27 and the pad of the first redistribution layer 25 may be interconnected by solder 281. As shown in fig. 5 (c), the interconnect structure 28 may include conductive pillars 282 and solder 281, and then the pads of the third redistribution layer 27 and the pads of the first redistribution layer 25 may be interconnected through the conductive pillars 282.

Fig. 6 to 9 are schematic structural diagrams in the manufacturing process of the circuit structure in the semiconductor package structure according to the embodiment of the disclosure.

Referring to fig. 6, a groove 13 is formed on a substrate 11.

Here, the groove 13 may be formed by a laser or an etching process.

Referring to fig. 7, an opening 111 is formed on the substrate 11.

Referring to fig. 8, the opening 111 is filled with a conductive material to form a via hole 112.

Referring to fig. 9, a redistribution layer 12 is formed on a substrate 11, resulting in a circuit structure 1 having a recess 13.

The redistribution layer 12 may be formed by a currently known or future developed redistribution layer forming technique, which is not specifically limited in this disclosure, and may be formed by photolithography, electroplating (plating), Electroless plating (electroplating), or the like.

Fig. 10 to 13 are schematic structural diagrams in the manufacturing process of the combined chip in the semiconductor package structure according to the embodiment of the present disclosure.

Referring to fig. 10, the first chip 21 and the second chip 22 are placed on the heat dissipation structure 5.

Referring to fig. 11, a bridge chip 23 is flip-chip bonded to the first chip 21 and the second chip 22. Here, the heat dissipation structure 5 may replace a carrier plate for supporting the first chip 21 and the second chip 22. Therefore, the subsequent process of removing the carrier can be reduced, and the heat dissipation structure 5 is directly used to replace the carrier.

Here, the interconnections between the bridge chip 23 and the first and

second chips

21 and 22 may be accomplished by a reflow soldering process.

Referring to fig. 12, a first filling material 24 is filled between the first chip 21, the second chip 22 and the bridge chip 23.

Referring to fig. 13, the combined chip 2 is obtained by singulation.

Referring to fig. 14, the combined chip 2 is picked up.

Referring to fig. 15, the combined chip 2 is flip-chip bonded to the redistribution layer 12, the combined chip 2 is flip-chip bonded to the redistribution layer, and the bridge chip 23 is disposed in the groove 13.

Here, the interconnection between the combined chip 2 and the rewiring layer 12 may be accomplished by a reflow soldering process.

Referring to fig. 16, the second filling material 3 is filled between the combined chip 2 and the circuit structure 1. And then the molding layer 6 is formed to cover the first chip 21, the second chip 22 and the heat dissipation structure 5.

According to the method for manufacturing the semiconductor packaging structure, the redistribution layer 12 is directly arranged on the substrate 11, the groove 13 is formed in the substrate 11, in addition, the functional chip 42 and the bridge chip 23 are combined in advance, and then the bridge chip 23 is arranged in the groove 13, so that a conductive column process and a mold sealing process are not needed, and the yield is improved. In addition, since the bridge chip 23 is disposed in the groove 13 of the substrate 11, the thickness of the entire structure is reduced.

While the present disclosure has been described and illustrated with reference to particular embodiments thereof, such description and illustration are not intended to limit the present disclosure. It will be clearly understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not be drawn to scale. There may be a difference between the technical reproduction in the present disclosure and the actual device due to variables in the manufacturing process and the like. There may be other embodiments of the disclosure that are not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to fall within the scope of the claims appended hereto. Although the methods disclosed in this disclosure have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated in the present disclosure, the order and grouping of the operations is not a limitation of the present disclosure.

Claims

1. A semiconductor package structure, comprising:

2. The semiconductor package structure of claim 1, wherein the combination chip further comprises:

3. The semiconductor package structure of claim 2, wherein the semiconductor package structure further comprises:

4. The semiconductor package structure of claim 3, wherein the first filler material is in contact with the second filler material.

5. The semiconductor package structure of claim 3, wherein the second filler material contacts sidewalls of the redistribution layer within the recess.

6. The semiconductor package structure of claim 3, wherein the second filler material contacts sidewalls of the substrate in the recess.

7. The semiconductor package structure of claim 3, wherein the bridge chip is a predetermined distance from the bottom surface of the second filler material.

8. The semiconductor package structure of claim 1, wherein a width of the redistribution layer is less than a width of the substrate.

9. The semiconductor package structure of claim 8, wherein a side of the redistribution layer facing the recess is shaped in a step-like manner.

10. The semiconductor package structure of claim 1, wherein the semiconductor package structure further comprises:

a first redistribution layer provided on the first chip and electrically connected to the first chip;

the second rewiring layer is arranged on the second chip and is electrically connected with the second chip;

the third triple wiring layer is arranged on the bridging chip and is electrically connected with the bridging chip;

the third rewiring layer is electrically connected to the first/second rewiring layer, and the first/second rewiring layer is electrically connected to the rewiring layer.