CN218783796U

CN218783796U - Power-on circuit based on time delay reset chip

Info

Publication number: CN218783796U
Application number: CN202223357587.0U
Authority: CN
Inventors: 黎讴; 王浩
Original assignee: Guangzhou Electronic Technology Co Ltd
Current assignee: Guangzhou Electronic Technology Co Ltd
Priority date: 2022-12-13
Filing date: 2022-12-13
Publication date: 2023-03-31
Anticipated expiration: 2032-12-13

Abstract

The utility model discloses a last electric circuit based on time delay reset chip should go up the electric circuit and include time delay reset chip circuit module, RC buffer circuit module and on-off control circuit module, time delay reset chip circuit module is including the time delay chip that resets, the time delay chip that resets is including the output pin that resets, the output pin that resets with the input of RC buffer circuit module is connected, the output of RC buffer circuit module with the input of on-off control circuit module is connected, the output of on-off control circuit module exports enable signal. The power-on time sequence function of multiple voltages of the chip can be achieved, normal starting of the chip can be guaranteed, cost can be reduced, the PCB space is reduced, time delay is accurate, stability is high, and anti-interference performance is strong.

Description

Power-on circuit based on time delay reset chip

Technical Field

The utility model relates to a power technical field especially relates to a last electric circuit based on time delay reset chip.

Background

In recent years, many high performance embedded processors typically require multiple supply voltages. If the time sequence of the multi-path voltage is not correct, the system can be started normally, the long-term stability of the circuit is influenced, even latch-up effect can occur, and devices are burnt out. Therefore, a certain power-on timing control circuit must be added. The common power-on sequence scheme adopts a special power management chip which controls the power-on sequence of each path of voltage according to an internal sequence controller, but the peripheral circuit of the chip is complex, the cost is higher, the occupied space of a PCB (printed circuit board) is large, and the level of an enabling pin of a DC-DC (direct current-direct current) is uncertain when the power supply is powered on, so that the power-on sequence function cannot be ensured. In addition, if RC and MOS tube time delay are adopted, inaccuracy and poor interference resistance are easily caused.

SUMMERY OF THE UTILITY MODEL

To the defect that above-mentioned prior art exists, the utility model aims to provide a go up electric circuit based on time delay chip that resets can solve the last electric time sequence function of chip multivoltage, not only can ensure the normal start of chip, moreover can reduce cost, reduce the PCB space, the time delay is accurate, stability is high, interference immunity is strong.

In order to achieve the above object, the utility model provides a last electric circuit based on time delay chip that resets should go up the electric circuit and include time delay chip circuit module, RC buffer circuit module and the on-off control circuit module that resets, time delay chip circuit module that resets includes the time delay chip that resets, the time delay chip that resets is including the output pin that resets, reset the output pin with the input of RC buffer circuit module is connected, the output of RC buffer circuit module with the input of on-off control circuit module is connected, the output of on-off control circuit module outputs enable signal.

Preferably, the RC buffer circuit module includes at least one third resistor, at least one second capacitor and at least one fifth resistor, and the reset output pin is commonly connected to a first end of the third resistor, a first end of the second capacitor and a first end of the fifth resistor.

Preferably, the second end of the third resistor is connected to a system supply voltage, and the second capacitor is connected to ground.

Preferably, the switch control circuit module includes at least one second resistor and a second switching tube, a second end of the fifth resistor is connected to a base of the second switching tube, a collector of the second switching tube is connected to a first end of the second resistor, and an emitter of the second switching tube is connected to ground.

Preferably, the switch control circuit module further includes at least one first resistor and a first switch tube, a collector of the second switch tube is connected to a base of the first switch tube, and a collector of the first switch tube is connected to a first end of the first resistor and outputs an enable signal.

Preferably, the second end of the first resistor and the first end of the second resistor are commonly connected to a system supply voltage.

Preferably, the switch control circuit module further includes at least one sixth resistor, a first end of the sixth resistor is commonly connected to the base of the first switch tube and the collector of the second switch tube, and a second end of the sixth resistor is connected to ground.

Preferably, the switch control circuit module further includes at least one fourth resistor, a first end of the fourth resistor is commonly connected to the first switch tube and the first end of the first resistor, and a second end of the fourth resistor is connected to ground.

Preferably, the first switch tube and the second switch tube comprise NPN transistors.

Preferably, the delay reset chip circuit module includes at least one first capacitor, the delay reset chip includes a power pin and a ground pin, the power pin and a first end of the first capacitor are connected to a system supply voltage, and the ground pin and a second end of the first capacitor are connected to ground.

Compared with the prior art, the beneficial effects of the utility model are that:

the utility model provides a go up electric circuit based on time delay chip U1 that resets, should go up electric circuit and include time delay chip circuit module that resets, RC buffer circuit module and on-off control circuit module, time delay chip circuit module that resets includes the time delay chip that resets, the time delay chip that resets includes the output pin that resets, reset the output pin and be connected with the input of RC buffer circuit module, the output of RC buffer circuit module is connected with the input of on-off control circuit module, the output of on-off control circuit module exports enable signal. Therefore, the utility model discloses can solve the last electric time sequence function of chip multivoltage, not only can ensure the normal start of chip, moreover can reduce cost, reduce the PCB space, the time delay is accurate, stability is high, interference immunity is strong.

Drawings

In order to more clearly illustrate the technical solution of the embodiments of the present invention, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

Fig. 1 is a circuit block diagram provided by the power-on circuit based on the delay reset chip of the present invention;

fig. 2 is a schematic circuit diagram provided by the power-on circuit based on the delay reset chip of the present invention;

the description of the reference numerals,

1. a delay reset chip circuit module; 2. an RC buffer circuit module; 3. a switch control circuit module; u1, a time delay reset chip; RESET, RESET output pin; r1, a first resistor; r2 and a second resistor; r3 and a third resistor; r4, a fourth resistor; r5 and a fifth resistor; r6 and a sixth resistor; c1, a first capacitor; c2, a second capacitor; q1, a first switch tube; q2 and a second switching tube.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, of the embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be further understood that the term "and/or" as used in the specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.

Please refer to fig. 1, an embodiment of the present invention provides an upper power circuit based on a time delay RESET chip U1, the upper power circuit includes a time delay RESET chip circuit module 1, an RC buffer circuit module 2 and a switch control circuit module 3, the time delay RESET chip circuit module 1 includes a time delay RESET chip U1, the time delay RESET chip U1 includes a RESET output pin RESET, the RESET output pin RESET is connected with an input end of the RC buffer circuit module 2, an output end of the RC buffer circuit module 2 is connected with an input end of the switch control circuit module, and an output end of the switch control circuit module 3 outputs an enable signal DC-EN. Therefore, the utility model discloses can solve the last electric time sequence function of chip multivoltage, not only can ensure the normal start of chip, moreover can reduce cost, reduce the PCB space, the time delay is accurate, stability is high, interference immunity is strong.

Referring to fig. 2, the utility model discloses based on the circuit schematic diagram that the last electric circuit of time delay chip U1 that resets provided, time delay chip circuit module 1 that resets includes at least one first electric capacity C1, and time delay chip U1 that resets includes power pin and ground pin, power pin and first electric capacity C1's first end connected system supply voltage, ground pin and first electric capacity C1's second end ground connection. Specifically, the utility model discloses preferably select the chip of ADM706RArz model, this chip can produce the output level of time delay 200ms.

The RC buffer circuit module 2 comprises at least one third resistor R3, at least one second capacitor C2 and at least one fifth resistor R5, and the RESET output pin RESET is commonly connected with a first end of the third resistor R3, a first end of the second capacitor C2 and a first end of the fifth resistor R5. The second end of the third resistor R3 is connected to the system supply voltage, and the second capacitor C2 is connected to ground.

The switch control circuit module 3 comprises at least one second resistor R2 and a second switch tube Q2, a second end of the fifth resistor R5 is connected with a base of the second switch tube Q2, a collector of the second switch tube Q2 is connected with a first end of the second resistor R2, and an emitter of the second switch tube Q2 is connected to the ground.

It should be noted that the first switch Q1 and the second switch Q2 of the present invention preferably include NPN triodes. Specifically, when selecting the PNP triode, technical personnel in this field can refer to the utility model discloses an embodiment carries out the relevance and modifies, and its functional effect is unanimous with the effect of NPN triode, the utility model discloses do not limit here and give unnecessary details. In addition, the same applies to the MOS transistor.

Further, the switch control circuit module 3 further includes at least one first resistor R1 and a first switch Q1, a collector of the second switch Q2 is connected to a base of the first switch Q1, and a collector of the first switch Q1 is connected to a first end of the first resistor R1 and outputs an enable signal DC-EN. The second end of the first resistor R1 and the first end of the second resistor R2 are connected with a system supply voltage together.

Further, the switch control circuit module 3 further includes at least one sixth resistor R6, a first end of the sixth resistor R6 is commonly connected to the base of the first switch Q1 and the collector of the second switch Q2, and a second end of the sixth resistor R6 is connected to ground.

Further, the switch control circuit module 3 further includes at least one fourth resistor R4, a first end of the fourth resistor R4 is connected to the first switch Q1 and a first end of the first resistor R1, and a second end of the fourth resistor R4 is connected to ground.

It should be understood that, in the above embodiment, at least one first resistor R1 may also be used, and a plurality of first resistors R1 may also be used to be connected in series or in parallel, which is not limited herein, and the electrical effect is consistent with the effect of only one first resistor R1, that is, the resistance value of only one first resistor R1 is the same as the resistance value of the plurality of first resistors R1 connected in series or in parallel. Therefore, the at least one second resistor R2, the at least one third resistor R3, the at least one fourth resistor R4, the at least one fifth resistor R5, the at least one sixth resistor R6, the at least one first capacitor C1, and the at least one second capacitor C2 are similar to each other, and are not described herein again.

The utility model discloses last electric circuit's theory of operation based on time delay reset chip U1 as follows: when the system power supply voltage reaches the working voltage (2.7-3.3V) of the delay reset chip U1, the delay reset chip U1 starts to work, and the reset delay output delay time in the delay reset chip U1 is 200ms. When the RESET time is within 200ms, the RESET output pin RESET of the delay RESET chip U1 outputs a low level, the low level passes through the third resistor R3 and the second capacitor C2 of the RC buffer circuit module 2, and then is limited by the fifth resistor R5, the second switching tube Q2 is in a cut-off state, the first switching tube Q1 is turned on due to voltage division of the second resistor R2 and the sixth resistor R6, and the collector level of the first switching tube Q1 is pulled down to a low level, so that the output enable signal DC-EN is a low level, and the output of the DC-DC electric chip is turned off. When the RESET time is longer than 200ms, the RESET output pin RESET of the delay RESET chip U1 outputs a high level, the high level passes through the third resistor R3 and the second capacitor C2 of the RC buffer circuit module 2, then the current is limited by the fifth resistor R5, the second switch tube Q2 is turned on, the base level of the first switch tube Q1 is pulled down to a low level, the first switch tube Q1 is turned off, and the output enable signal DC-EN is a high level due to voltage division of the first resistor R1 and the fourth resistor R4, and the DC-DC electric chip is turned on to output, thereby completing the first-stage power-on timing function requirement.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of various equivalent modifications or replacements within the technical scope of the present invention, and these modifications or replacements should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. The power-on circuit based on the time delay reset chip is characterized by comprising a time delay reset chip circuit module, an RC buffer circuit module and an on-off control circuit module, wherein the time delay reset chip circuit module comprises a time delay reset chip which comprises a reset output pin, the reset output pin is connected with the input end of the RC buffer circuit module, the output end of the RC buffer circuit module is connected with the input end of the on-off control circuit module, and the output end of the on-off control circuit module outputs an enable signal.

2. The power-on circuit based on the delayed reset chip as claimed in claim 1, wherein the RC buffer circuit module comprises at least one third resistor, at least one second capacitor and at least one fifth resistor, and the reset output pin is commonly connected to a first terminal of the third resistor, a first terminal of the second capacitor and a first terminal of the fifth resistor.

3. The power-on circuit based on the delayed reset chip as claimed in claim 2, wherein a second terminal of the third resistor is connected to a system supply voltage, and the second capacitor is connected to ground.

4. The power-on circuit based on the delayed reset chip as claimed in claim 3, wherein the switch control circuit module includes at least one second resistor and a second switch tube, a second end of the fifth resistor is connected to a base of the second switch tube, a collector of the second switch tube is connected to a first end of the second resistor, and an emitter of the second switch tube is connected to ground.

5. The power-on circuit based on the delayed reset chip as claimed in claim 4, wherein the switch control circuit module further comprises at least one first resistor and a first switch tube, a collector of the second switch tube is connected to a base of the first switch tube, and a collector of the first switch tube is connected to a first end of the first resistor and outputs an enable signal.

6. The power-on circuit based on the delayed reset chip of claim 5, wherein the second end of the first resistor and the first end of the second resistor are commonly connected to a system supply voltage.

7. The power-on circuit based on the delayed reset chip as claimed in claim 5, wherein the switch control circuit module further comprises at least one sixth resistor, a first end of the sixth resistor is commonly connected to the base of the first switch tube and the collector of the second switch tube, and a second end of the sixth resistor is connected to ground.

8. The power-on circuit based on the delayed reset chip as claimed in claim 5, wherein the switch control circuit module further comprises at least one fourth resistor, a first end of the fourth resistor is commonly connected to the first switch tube and the first end of the first resistor, and a second end of the fourth resistor is connected to ground.

9. The power-on circuit based on the delayed reset chip of claim 5, wherein the first switch tube and the second switch tube comprise NPN transistors.

10. The power-on circuit based on the delayed reset chip of claim 1, wherein the delayed reset chip circuit module comprises at least one first capacitor, the delayed reset chip comprises a power pin and a ground pin, the power pin and a first end of the first capacitor are connected to a system supply voltage, and the ground pin and a second end of the first capacitor are connected to ground.