CN2187361Y - Improved Chinese and Western language picture-characters television decoder - Google Patents

Abstract

The utility model discloses a Chinese and Western language picture-character television decoder which belongs to the technical field of pictorial communication and comprises a WST Western language picture-character television decoder and a multiplex message receiving, processing and displaying circuit connected by an I<2>C bus, wherein a special multiplex chip is connected with a CPU, an EPROM data and an address interface by a data bus and an address bus and is communicated with an RAM by an ASIC internal address and a data line so as to realize the data processing and displaying function of the decoder, and finally, an R, a G, a B and a BLANK are output. The utility model has the advantages of simple structure, small power consumption, strong reliability and low cost.

Description

Improved Chinese and Western language picture-characters television decoder

The utility model belongs to the image communication technical field, further relate to a kind of be used for handling at the TV Field blanking interval transmit graph text information, and with its be shown in the modified model on the video screen, the western language teletext decoder.

In, the western language teletext decoder is based on WST western language teletext decoder, Applied Computer Techniques expansion Chinese character improves a kind of west, the compatible teletext decoder of Chinese of ability of drawing.It can get off the message pick-up that vertical blanking period transmits by customer requirements, is presented at after treatment on the TV screen.

China's utility model patent " in, western language teletext decoder " (patent No. ZL92209492.6) disclosed decoder is made up of WST western language decoder and multiplex's message pick-up, processing, display circuit two parts, the entire circuit complex structure, disturb greatly, power consumption is big, cost is high.

In the modified model that the purpose of this utility model is to provide that a kind of circuit structure is simple, power consumption is little, good reliability, cost are low, the western language teletext decoder.

The utility model comprises WST western language teletext decoder and through I ²Multiplex's message pick-up, processing, display circuit two parts that the C bus connects.WST western language decoder is made up of video frequency processing chip (VIP) SAA5246 and page or leaf memory (RAM) 6264; Multiplex's message pick-up, processing, display circuit are made up of control microcomputer (CPU), program, character, figure, Chinese character base (EPROM) many merits special chip (ASIC), data, demonstration memory (RAM) and phase-locked loop (PLL).

Control microcomputer CPU passes through I ²The C bus links to each other with video frequency processing chip VIP in the WST decoder, realize the UNICOM of serial data, many merits special chip (ASIC) is a core of the present utility model, it links to each other with CPU, EPROM data, address mouth by data/address bus, address bus, link to each other with RAM by address, data wire, realize data processing, the Presentation Function of decoder.Export R, G, B and BLANK signal at last.Phase-locked loop (PLL) is with the clock of VIP and the 6MHZ clock lock of CPU and ASIC.

Below in conjunction with accompanying drawing the utility model is further described.

Fig. 1 is the utility model integrated circuit schematic diagram.

Fig. 2 is many merits of the utility model special chip ASIC circuit diagram.

The utility model multiplex (MUX) message pick-up, processing, display part are by control micropolar CPU, 80C31 or 87C51(2), phase-locked loop pll 74HC4046(3), data, display buffer ram memory 62256(4), many merits special chip ASIC-GX2001(5), program, character, shape library EPROM, 27C256(6a) and I and II standard Chinese character storehouse EPROM27C040(6b) form.

CPU(2) pass through I ²The C bus receives serial data and the clock that WST decoder (1a) VIP comes, special chip ASIC(5) by data/address bus D ₀-D ₇With CPU(2) and EPROM(6) data port be connected, realize exchanges data, by address bus A ₀-A ₁₅With CPU(2) address mouth A ₈-A ₁₅Link to each other, with EPROM(6) address mouth A ₀-A ₁₅Link to each other, realize addressing.ASIC(5) data wire P ₀-P ₇Address wire C ₀-C ₁₄With RAM(4) data, address mouth link to each other, realize exchanges data and addressing, at last by ASIC(5) output R, G, B and BLANK signal.Phase-locked loop pll (3) is with VIP(1) timer clock and CPU(2) ASIC(5) and the 6MHZ clock lock.Program, character, shape library (6a) are the deposit operation programs, the read-only memory of western language, character, shape library, I and II standard Chinese character storehouse (6b) is the read-only memory EPROM that deposits the I and II standard Chinese character, their address, data are through bus and CPU(2) ASIC(5) link to each other, output enable OE is by CPU(2) PSEN holds control.Many merits special chip is by display control circuit CRTC(9), decoding circuit DECODER(7), pulse width modulation circuit PWM(8), video output circuit VIDIO(10), timing circuit TIMER(11) and switch matrix (12) form.The data port of decoding circuit (7) and data/address bus D ₀-D ₇Connect, and by ASIC internal data line and PWM(8), CRTC(9) and data port VIDIO(10) be connected.The address A of decoding circuit (7) ₈-A ₁₅With CPU(2) address wire be connected, link to each other the read/write line and CPU(2 of decoding circuit (7) after treatment with switch matrix (12)) RD/WR link to each other.And the control line of control line display control circuit CRTC links to each other.Pulse width modulation circuit PWM(8) is the programmable pulse modulation signal generator, produces output waveform PWMA-C able to programme, EDM Generator of Adjustable Duty Ratio.Its clock is from the RD delivery outlet of VIP, and programming data is from data/address bus.

Display control circuit CRTC(9) Shu Chu television line, field signal and VIDIO(10) linking to each other becomes address signal with data/address bus input and links to each other with switch matrix (12).Timing circuit TIMER(11) for CRTC(9), VIDEO(10) 2MHZ, 1MHZ and 6MHZ clock are provided, input F TIMER(11) is from VIP(1).Video output VIDRO(10) with CRTC(9) row, field synchronization H, V output link to each other, data/address bus links to each other with the data of data, display buffer ram memory, output and synchronous R, G, B and the BLANK signal of TV, the required sequential of VIDIO is exported by TIMER, switch matrix (12) and DECODER(7) and the CRTC address wire be connected, to the switching of CPU and CRTC buffering storage portions address.

The utility model has been owing to adopted many merits special chip ASIC of design voluntarily, and it comprises and has substituted display control chip 6845, printing interface 8155, timing circuit, 17 universal integrated circuit chips such as decoding circuit 74HC138, combinational circuit.Thereby in making, western language teletext decoder multiplex (MUX) message pick-up, processing, display circuit greatly simplify, it has not only dwindled the pcb board area, and reduced line, thereby having reduced width of cloth blackberry lily disturbs, reduced power consumption, improved the reliability of decoder, become among ratio of performance to price optimum a kind of follow-on, the western language teletext decoder.

Claims (3)

1, a kind of follow-on in, the western language teletext decoder, it comprises WST western language teletext decoder and multiplex's message pick-up, processing, display circuit, it is characterized in that: control microcomputer CPU passes through I ²The C bus links to each other with video frequency processing chip VIP in the WST decoder, carry out the UNICOM of serial data, multiplex's special chip ASIC links to each other with CPU, EPROM data, address mouth by data/address bus, address bus, ASIC links to each other with RAM by address, data wire, realize data processing, the Presentation Function of decoder, export R, G, B and BLANK signal at last, phase-locked loop pll is used for the clock lock with the clock of video frequency processing chip VIP and CPU and ASIC.

2, decoder as claimed in claim 1 is characterized in that: described control microcomputer CPU adopts 80C31 chip or 87C51 chip.

3, decoder as claimed in claim 1, it is characterized in that: described multiplex's special chip ASIC is by display control circuit CRTC, decoding circuit DECODER, pulse width modulation circuit PWM, video output circuit VIDEO, timing circuit TIMER and switch matrix are formed, the data port of decoding circuit is connected with data/address bus and receives pulse width modulation circuit by many merits special chip ASIC internal data line, the data port of display control circuit and video output circuit, the decoding circuit home address links to each other with switch matrix, the read/write line of decoding circuit is connected with the read/write signal of CPU, control line links to each other with the control line of display control circuit, pulse width modulation circuit is the programmable pulse modulation signal generator, its clock is from the RD delivery outlet of WST decoder video process chip VIP, the data port of display control circuit is connected with data/address bus, the data port of video output is connected with data/address bus, and with the H of display control circuit, the V signal output line connects, output R, G, B and BLANK signal.

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