CN218730965U - Semiconductor structure - Google Patents

Abstract

The utility model provides a semiconductor structure. The semiconductor structure includes: a chip; a sensor disposed on the chip and having a sensing region remote from the chip; the cover body is arranged on the chip and is adjacent to the sensing area, and the cover body and the chip jointly form a closed space for accommodating the sensor. Above-mentioned technical scheme can dwindle the airtight space volume that is used for the holding sensor at least, promotes the product reliability.

Description

Semiconductor structure

Technical Field

The utility model relates to the field of semiconductor technology, more specifically relates to a semiconductor structure.

Background

There are two approaches to the hermetic requirements of some optical products. The first way is to use a mask (lid) 10 as shown in fig. 1A, wherein the mask body 10 comprises a wall 11 disposed on a carrier plate 20 and a glass cover 13 disposed on the wall 11. However, this method occupies a large area of the carrier 20, and the utilization rate of the carrier 20 is low. In addition, since the size of the enclosed space 35 for accommodating the chip 30 and the sensor 40 is large, the amount of gas in the enclosed space 35 is also large, and it is difficult to seal the structure on the carrier 20 with the general cover body 10. Therefore, for example, during the reflow process, the gas in the enclosed space 35 is liable to expand, so that the glass lid 13 is pushed open (so-called popcorn effect) and has a reliability problem. As shown in fig. 1B, gas expansion 38 causes the glass cover 13 to be pushed open at the structurally weak point where the glass cover 13 meets the wall 11 due to the popcorn effect. The use of ceramic substrates can achieve an integral seal, but at a higher price and larger size. In addition, the height of the mask body 10 is low, for example, the bottom surface of the wall 11 under the glass cover 13 is lower than the top surface of the sensor 40, so that the chip 30 with the required height cannot be placed inside the mask body 10 or cannot be applied to the case where the height of the enclosed space 35 is required.

A second approach is to use an open cavity molding (open cavity molding) configuration as shown in fig. 1C, in which the glass cover 13 is disposed over the cavity 36 defined by the molding compound 70. However, the mold for realizing such a structure is expensive, has a large tolerance, has a high risk of glue overflow, cannot remove the glue overflow with a medicament, and has a low utilization rate of the carrier plate 20, which is not favorable for miniaturization. In addition, the height of the molding compound 70 is also unstable, so that the glass cover 13 is easily tilted.

SUMMERY OF THE UTILITY MODEL

To the above-mentioned problem among the correlation technique, the utility model provides a semiconductor structure can dwindle the airtight space volume that is used for the holding sensor at least, reduces the risk problem of puffed rice effect, promotes the product reliability.

According to some embodiments, a semiconductor structure is provided. The semiconductor structure includes: a chip; a sensor disposed on the chip and having a sensing region remote from the chip; the cover body is arranged on the chip and is adjacent to the sensing area, and the cover body and the chip jointly form a closed space for accommodating the sensor.

In some embodiments, the mask includes a transparent portion disposed over the sensing region.

In some embodiments, the width of the transparent portion in the lateral direction is less than the width of the chip and greater than the width of the sensor.

In some embodiments, the semiconductor structure further comprises: the chip is positioned on the carrier plate; and the lead is electrically connected with the first bonding pad of the chip and the carrier plate.

In some embodiments, a mask is disposed between the first pad and the sensor.

In some embodiments, the sensor is electrically connected to the second pad of the chip.

In some embodiments, the active surface of the sensor faces and is bonded to the chip, the active surface of the sensor being encapsulated by the underfill.

In some embodiments, the mask has a space for accommodating the lead.

In some embodiments, the space for housing the leads is filled with a molding compound.

In some embodiments, the carrier plate is provided therein with an exhaust through hole communicating with the space for accommodating the lead.

In the semiconductor structure, the cover body and the chip jointly form the closed space for accommodating the sensor, so that the volume of the closed space for accommodating the sensor is reduced, the risk problem of gas explosion in the closed space can be reduced, and the reliability of the product is improved.

Drawings

Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A is a schematic cross-sectional view of a conventional semiconductor structure employing a masking body for hermetic sealing requirements.

FIG. 1B is a schematic cross-sectional view of the semiconductor structure shown in FIG. 1A showing a popcorn effect.

Fig. 1C is a schematic cross-sectional view of an open cavity molding structure for hermetic sealing requirements in a conventional semiconductor structure.

Figure 2 is a cross-sectional schematic view of a semiconductor structure according to one embodiment of the present application.

FIG. 3 is a cross-sectional schematic view of a semiconductor structure according to one embodiment of the present application.

Figure 4 is a cross-sectional schematic view of a semiconductor structure according to one embodiment of the present application.

Figure 5 is a cross-sectional schematic view of a semiconductor structure according to one embodiment of the present application.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are in direct contact, as well as embodiments in which additional features are formed between the first and second features such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

As used herein, the terms "substantially", "substantially" and "about" are used to describe and illustrate minor variations. When used in conjunction with an event or circumstance, the terms can refer to both an instance in which the event or circumstance occurs precisely as well as an instance in which the event or circumstance occurs in close proximity.

For convenience in description, "first," "second," "third," and the like may be used herein to distinguish between different components of a figure or series of figures. "first," "second," "third," etc. are not intended to describe corresponding components.

According to an embodiment of the present application, a semiconductor structure is provided. Fig. 2 is a cross-sectional schematic view of a semiconductor structure 100 according to one embodiment of the present application. In some embodiments, the semiconductor structure 100 may comprise an optical device. In other embodiments, the semiconductor structure 100 may be an electronic device other than an optical device.

Referring to fig. 2, a semiconductor structure 100 includes a carrier 110. The carrier board 110 may be a substrate. The carrier board 110 may also be a printed circuit board or the like. The chip 102 is located on the carrier 110, and the sensor 104 is disposed on the chip 102. In some embodiments, the sensor 104 may be an optical sensor, such as a photodiode or the like. The sensor 104 has a sensing area remote from the chip 102. The sensing region may be an upper surface or a portion of an upper surface of the sensor 104 remote from the chip 102. The chip 102 is used to control the sensor 104. Chip 102 may be an Application Specific Integrated Circuit (ASIC), and chip 102 may be any suitable type of chip for controlling sensor 104.

Masking body 120 is disposed over chip 102 and adjacent to the sensing region of sensor 104. The cover mask 120 and the chip 102 together form a closed space 115 for accommodating the sensor 104. Here, the top and side surfaces of the sealed space 115 are formed by the mask body 120, and the bottom surface of the sealed space 115 is formed by the chip 102.

In the semiconductor structure 100, the mask body 120 and the chip 102 together form the enclosed space 115 for accommodating the sensor 104, so that the volume of the enclosed space 115 for accommodating the sensor 104 and the gas capacity therein are reduced, and the risk of explosion of gas (such as air or moisture) in the enclosed space 115 can be reduced by reducing the content of the gas, thereby improving the product reliability. In addition, the hermetic sealing of the closed space 115 in which the sensor 104 is located is achieved by the mask body 120 and the chip 102, and therefore the cost price of the product is advantageous.

In the embodiment shown in fig. 2, the mask 120 includes a transparent portion 124 disposed over the sensing area of the sensor 104. The transparent portion 124 may pass light (e.g., some particular wavelength of light), and the light passes through the transparent portion 124 to the sensing region of the sensor 104. In some embodiments, the transparent portion 124 of the mask 120 may be made of glass. In other embodiments, the transparent portion 124 may be made of other materials that are transparent to light.

The width of the transparent portion 124 in the lateral direction is smaller than the width of the chip 102 and larger than the width of the sensor 104. Masking body 120 also includes walls 122 connected between transparent portion 124 and chip 102. The material of the wall 122 may be a metallic material, or may be any other suitable material. The wall 122 is configured to laterally surround the sensor 104. The wall 122 may be configured in an annular shape that laterally surrounds the sensor 104. The wall 122 may be above the upper surface of the sensor 104. The outer side of the wall 122 may be coplanar with the outer side of the transparent portion 124. A wall 122 disposed on the chip 102 may be used to support the transparent portion 124. Since the masking body 120 does not need to be disposed on the carrier 110, the utilization rate of the carrier 110 is improved. In addition, since the transparent portion 124 is not disposed on the molding compound but disposed on the wall 122, the problem that the transparent portion 124 is easily inclined due to the unstable height of the molding compound is avoided, and the degree of freedom in adjusting the height of the mask 120 is also improved.

The active surface 103 of the chip 102 is arranged away from the carrier plate 110 and towards the chip 102, the active surface 103 having at least one first pad 106a located outside the enclosed space 115. The wires 118 electrically connect the first pads 106a of the chip 102 and the carrier plate 110. The mask body 120 is disposed between the first pads 106a and the sensor 104. Specifically, the wall 122 of the mask 120 is connected at a position between the first pad 106a on the active surface 103 and the sensor 104.

The first pads 106a and the leads 118 are covered by a molding compound 140. The molding compound 140 also covers the outer side of the wall 122, and at least a portion of the outer side of the transparent portion 124. The top surface of the molding compound 140 is sloped, and the top surface of the molding compound 140 gradually decreases from one end in contact with the transparent portion 124 toward the opposite end. The molding compound 140 may be configured in an annular shape that laterally surrounds the mask body 120. The molding compound 140 may be used to help secure the cover wall 122 and the transparent portion 124, thereby enhancing the structural strength of the interface between the wall 122 and the transparent portion 124, which may prevent the popcorn effect from occurring at the interface between the wall 122 and the transparent portion 124. In addition, the masking body 120 can prevent the molding compound 140 from overflowing into the enclosed space 115 where the sensor 104 is located during the dispensing operation, thereby improving the reliability of the product.

According to some embodiments, sensor 104 is flip-chip bonded to chip 102. That is, the active surface 105 of the sensor 104 is disposed opposite the active surface 103 of the die 102, and the active surface 105 of the sensor 104 is bonded to the active surface 103 of the die 102. The active surface 103 of the chip 102 also has a second bonding pad 106b located within the enclosed space 115. The active surface 105 of the sensor 104 is electrically connected to the second pad 106b. The second pad 106b may include a plurality of pads disposed apart from each other. The active surface 105 of the sensor 104 may be connected to the second pads 106b by solder balls, copper pillars, or other suitable electrical connection means. The active surface 105 and the second pads 106b of the sensor 104 are coated with an underfill 130.

According to some embodiments, referring to fig. 2, the process of forming the semiconductor structure 100 comprises the steps of: providing a carrier plate 110; arranging the chip 102 on the carrier board 110, with the active surface 103 of the chip 102 being remote from the carrier board 110; bonding the first pads 106a of the chip 102 to the carrier board 110 with the wires 118 and bonding the active surface 105 of the sensor 104 with the second pads 106b of the chip 102 in a flip-chip manner on the chip 102, forming an underfill 130; providing a wall 122 between the first pad 106a and the second pad 106b on the active surface 103 of the chip 102, and then providing a transparent portion 124 on the wall 122; a dispensing operation is performed to form a molding compound 140 covering the leads 118 outside the wall 122 and the transparent portion 124.

Fig. 3 is a cross-sectional schematic view of a semiconductor structure 200 according to one embodiment of the present application. The same components in the semiconductor structure 200 shown in fig. 3 as those in the semiconductor structure 100 shown in fig. 2 are given the same reference numerals, and repeated descriptions of the same components are omitted. Only the differences between the semiconductor structure 200 shown in fig. 3 and the semiconductor structure 100 shown in fig. 2 will be described below.

In the semiconductor structure 200 shown in fig. 3, the wall 222 of the masking body 220 is made of a transparent material. Wall 222 and transparent portion 224 of mask body 220 are formed of the same material, e.g., both glass. In this embodiment, the wall 222 and the transparent portion 224 are a single piece of transparent material. The molding compound 140 covers at least a portion of the outer side of the mask body 220. The top of the molding compound 140 may be coplanar with the top surface of the transparent portion 224 or lower than the top surface of the transparent portion 224.

By constructing walls 222 of transparent material as a single piece with transparent portion 224, the overall structural strength of mask body 220 can be increased, and the situation where a separate transparent portion is pushed away can be avoided. As described above, since the masking body 220 is not disposed on the carrier 110, the utilization rate of the carrier 110 can be improved. In addition, the masking body 220 can prevent the molding compound 140 from overflowing into the enclosed space 115 where the sensor 104 is located during the dispensing operation, thereby improving the reliability of the product.

According to some embodiments, referring to fig. 3, the process of forming the semiconductor structure 200 may include the steps of: providing a carrier plate 110; arranging the chip 102 on the carrier board 110, with the active surface 103 of the chip 102 being remote from the carrier board 110; bonding the first pads 106a of the chip 102 to the carrier board 110 with the wires 118 and bonding the active surface 105 of the sensor 104 with the second pads 106b of the chip 102 in a flip-chip manner on the chip 102, forming an underfill 130; an integral piece connecting wall 222 and transparent portion 224 between first pad 106a and second pad 106b on active surface 103 of chip 102; a dispensing operation is performed to form the molding compound 140 covering the leads 118 outside the integrated body of the wall 222 and the transparent portion 224.

Fig. 4 is a cross-sectional schematic view of a semiconductor structure 300 according to one embodiment of the present application. The same components in the semiconductor structure 300 shown in fig. 4 as those in the semiconductor structure 200 shown in fig. 2 are given the same reference numerals, and repeated descriptions of the same components are omitted.

In the semiconductor structure 300 shown in fig. 4, the mask 320 has a space 142 for accommodating the lead 118. Specifically, wall 322 of masking body 320 extends upward from active surface 103 of chip 102 to contact transparent portion 124, and then also extends laterally over leads 118 to define space 142 below wall 322 for receiving leads 118. Wall 322 may be constructed of a metallic material. The space 142 may be disposed around the sensor 104. Also, a portion of the wall 322 may protrude from the bottom surface of the transparent part 124 to extend upward to surround the side surface of the transparent part 124.

The space 142 for housing the leads 118 is filled with a molding compound 140. A portion of the molding compound 140 is located on the chip 102, and another portion is located on the carrier 110. The side of molding compound 140 adjacent sensor 104 is in contact with wall 322, and the side of molding compound 140 remote from sensor 104 is exposed by wall 322. The side of the molding compound 140 remote from the sensor 104 is coplanar with the corresponding side of the wall 322 on the molding compound 140. In the semiconductor structure 300, the amount of the molding compound 140 may be reduced compared to the semiconductor structure 100 (see fig. 2) and the semiconductor structure 200 (see fig. 3).

According to some embodiments, referring to fig. 4, the process of forming the semiconductor structure 300 may include the steps of: providing a carrier plate 110; arranging the chip 102 on the carrier board 110, with the active surface 103 of the chip 102 being remote from the carrier board 110; bonding the first pads 106a of the chip 102 to the carrier board 110 with the wires 118 and bonding the active surface 105 of the sensor 104 with the second pads 106b of the chip 102 in a flip-chip manner on the chip 102, forming an underfill 130; a wall 322 with a space 142 is provided between the first pad 106a and the second pad 106b on the active surface 103 of the chip 102, and a side of the wall 322 away from the sensor 104 may be provided with a plurality of pillars (not shown, for example, pillars are provided at four corners of the top view, respectively) supported between the carrier board 110 and the wall 322, and then the transparent part 124 is provided on the wall 322; performing a dispensing operation to form a molding compound 140 covering the leads 118 in the space 142 below the wall 322; a dicing operation is performed to remove the pillars, resulting in the semiconductor structure 300 shown in fig. 4.

Fig. 5 is a cross-sectional schematic view of a semiconductor structure 400 according to one embodiment of the present application. The same components in the semiconductor structure 400 shown in fig. 5 as those in the semiconductor structure 200 shown in fig. 2 are given the same reference numerals, and repeated descriptions of the same components are omitted.

In the semiconductor structure 400 shown in fig. 5, the mask body 420 has a space 442 for accommodating the lead 118. Specifically, the space 442 for accommodating the lead 118 is formed in the wall 422 of the mask 420. Space 442 may be disposed around sensor 104. Also, a portion of the wall 422 may have a bottom surface protruding from the transparent part 124 to extend upward and surround the side surface of the transparent part 124.

In the semiconductor structure 400, the space 442 for accommodating the lead 118 is a cavity, and the wall 422 of the mask 420 forms the side and top surfaces of the space 442. Since the space 442 is formed in the wall 322, the wall 322 has a first leg 428 connected to the chip 102 and a second leg 429 connected to the carrier board 110. First leg 428 has a height measured from the top surface of space 442 to the bottom end of first leg 428, and second leg 429 has a height measured from the top surface of space 442 to the bottom end of second leg 429. The height of the second leg 429 is greater than the height of the first leg 428. Since the molding compound is not disposed in the space 442, the dispensing operation for forming the molding compound 140 can be omitted.

In the embodiment shown in fig. 5, the space 442 is vented through the carrier plate 110. The carrier plate 110 has an exhaust through hole 119 communicating with the space 442, and the exhaust through hole 119 penetrates the carrier plate 110. The space 442 may be vented through the vent aperture 119.

According to some embodiments, referring to fig. 5, the process of forming the semiconductor structure 400 may include the steps of: providing a carrier plate 110; arranging the chip 102 on the carrier board 110, with the active surface 103 of the chip 102 being remote from the carrier board 110; bonding the first pads 106a of the chip 102 to the carrier board 110 with the wires 118 and bonding the sensor 104 with the second pads 106b of the chip 102 in a flip-chip manner on the chip 102, forming an underfill 130; a wall 422 having a space 442 is provided between the first pad 106a and the second pad 106b on the active surface 103 of the chip 102, and then the transparent part 124 is provided on the wall 422.

Although the sensor 104 is applied in each of the semiconductor structures 100, 200, 300, and 400 described above, in other embodiments, non-sensor devices may be applied in each of the semiconductor structures 100, 200, 300, and 400, i.e., the sensor 104 may be replaced with a device requiring a large-sized enclosed space 115 above the chip 102. In addition, there may be no sensor 104 or any device in the enclosed space 115 or on the chip 102.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present invention as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (10)

1. A semiconductor structure, comprising:

a chip;

a sensor disposed on the chip and having a sensing region remote from the chip;

the cover body is arranged on the chip and is close to the sensing area, and the cover body and the chip jointly form a closed space for accommodating the sensor.

2. The semiconductor structure of claim 1,

the mask includes a transparent portion disposed over the sensing region.

3. The semiconductor structure of claim 2,

the width of the transparent portion in the lateral direction is smaller than the width of the chip and larger than the width of the sensor.

4. The semiconductor structure of claim 1, further comprising:

the chip is positioned on the carrier plate;

and the lead is electrically connected with the first bonding pad of the chip and the carrier plate.

5. The semiconductor structure of claim 4,

the mask is disposed between the first pad and the sensor.

6. The semiconductor structure of claim 4,

the sensor is electrically connected to the second pad of the chip.

7. The semiconductor structure of claim 1,

an active surface of the sensor faces and is bonded to the chip, the active surface of the sensor being coated with an underfill.

8. The semiconductor structure of claim 4,

the cover body is provided with a space for accommodating the lead.

9. The semiconductor structure of claim 8,

the space for accommodating the leads is filled with a molding compound.

10. The semiconductor structure of claim 8, wherein said trench isolation region is formed by a process of forming a trench isolation region

An exhaust through hole communicated with the space for accommodating the lead is arranged in the carrier plate.

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