CN218675744U - Extensible high-density electroencephalogram acquisition equipment - Google Patents
Extensible high-density electroencephalogram acquisition equipment Download PDFInfo
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- CN218675744U CN218675744U CN202223120376.5U CN202223120376U CN218675744U CN 218675744 U CN218675744 U CN 218675744U CN 202223120376 U CN202223120376 U CN 202223120376U CN 218675744 U CN218675744 U CN 218675744U
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Abstract
The embodiment of the utility model provides an extensible high density brain electricity collection equipment relates to brain electricity collection technology field. The equipment comprises a main circuit unit, a control circuit unit and at least one front end acquisition unit, wherein the control circuit unit and the front end acquisition unit are respectively connected with the main circuit unit. The front-end acquisition unit receives the electroencephalogram signals acquired by the electroencephalogram sampling electrode and transmits the electroencephalogram signals to the control circuit unit through the main circuit unit. The main circuit unit is used for receiving an acquisition instruction sent by an upper computer and transmitting the acquisition instruction to the control circuit unit. And the control circuit unit is used for controlling the front end acquisition unit connected with the front end sampling interface on the main circuit unit to synchronously acquire signals based on the acquisition instruction. The utility model discloses in make equipment inner structure compacter through modular circuit design, reduce the equipment volume, front end acquisition unit can freely expand to 8 collection module for the total number of leading can reach 256 passageways, satisfies high density brain electricity collection demand.
Description
Technical Field
The utility model relates to an electroencephalogram collection technology field, concretely relates to extensible high-density electroencephalogram collection equipment.
Background
The brain electrical signal is a bioelectricity signal generated by normal physiological activities of cerebral neurons, and compared with non-invasive brain electrical signals, invasive brain electrical signals have higher spatial resolution and larger bandwidth, and the excitation condition of a single neuron and the coding mode of a neuron cluster can be observed more accurately. The invasive brain-computer interface can control external mechanical equipment to complete complex actions more frequently, accurately and flexibly. The method has the advantages that invasive electroencephalogram signals with high density, high bandwidth and high quality are collected, and the method has important significance for neuroscience brain function research and clinical medical diagnosis.
Most of the existing desk-top digital electroencephalographs are specialized in medical diagnosis and scientific research by hospitals and research institutes, collect non-invasive electroencephalogram signals, and are large in size and not easy to move. The existing invasive signal acquisition equipment is often large in size and complex in connection, the number of sampling channels is fixed, the price is high, and the data sampling precision is not high. Most wearable portable acquisition equipment can only be used for non-invasive electroencephalogram signal acquisition, and due to the limitation of wireless transmission data bandwidth, the sampling speed is low, the sampling speed is usually not greater than 2000sps, the number of sampling channels is small, the sampling channels are usually not greater than 64 channels, and the lithium battery cannot support long-time continuous acquisition.
Based on the technical problems, the applicant proposes a technical scheme of the application.
Disclosure of Invention
The utility model aims at providing an extensible high density brain electricity collection system makes equipment inner structure compacter through modular circuit design, reduces the equipment volume, and front end acquisition unit can freely expand, expands to 8 collection module at most for total lead number can reach 256 passageways, satisfies high density brain electricity collection demand.
In order to achieve the above object, the utility model provides an extensible high density brain electricity collection equipment, include: the device comprises a main circuit unit, a control circuit unit and at least one front end acquisition unit; the main circuit unit is in communication connection with the control circuit unit, a plurality of front-end sampling interfaces are arranged on the main circuit unit, the front-end sampling units correspond to the electroencephalogram sampling electrodes one by one, one end of each front-end sampling unit is connected to one front-end sampling interface, and the other end of each front-end sampling unit is connected to the corresponding electroencephalogram sampling electrode; the front-end acquisition unit is arranged to receive the electroencephalogram signals acquired by the electroencephalogram sampling electrode and is transmitted to the control circuit unit through the main circuit unit; the main circuit unit is used for receiving an acquisition instruction sent by an upper computer and transmitting the acquisition instruction to the control circuit unit; and the control circuit unit is used for controlling the front end acquisition unit connected with the front end sampling interface on the main circuit unit to synchronously acquire signals based on the acquisition instruction.
In one embodiment, each of the front-end acquisition units comprises: the system comprises a conductive connector, a signal conditioning circuit and a front end acquisition chip which are sequentially connected; the lead connector is electrically connected with the electroencephalogram sampling electrode, and the front-end acquisition chip is connected to a front-end sampling interface on the main circuit unit; the signal conditioning circuit is used for carrying out bandwidth limitation on electroencephalogram signals sent by the electroencephalogram sampling electrode connected with the lead connector; the front-end acquisition chip is used for forwarding the received electroencephalogram signals sent by the signal conditioning circuit to the main circuit unit.
In an embodiment, each of the front-end acquisition units includes a plurality of the front-end acquisition chips, and the plurality of the front-end acquisition chips are connected in a daisy chain manner.
In one embodiment, each of the front-end acquisition units further comprises an anti-static protection circuit; in each front-end acquisition unit, one end of the anti-static protection circuit is connected to the connection position of the conductive connector and the signal conditioning circuit, and the other end of the anti-static protection circuit is grounded.
In one embodiment, the lead connector has 32 channels connected to the electroencephalogram acquisition electrodes, and the number of the front-end acquisition units is 8.
In one embodiment, the front-end acquisition chips are 8-channel sampling, and the number of the front-end acquisition chips is 4.
In one embodiment, the main circuit unit further comprises a DC power input interface, a power conditioning circuit, a power isolation circuit, a signal isolation circuit, a control circuit interface, and a USB connector; the DC power supply input interface is connected with a working power supply; the input end of the power conditioning circuit is connected with the DC power input interface, the output end of the power conditioning circuit is connected with the power isolation circuit, and the power conditioning circuit is used for converting the accessed working power supply voltage into the 5V working voltage required by the main circuit unit and the control circuit unit; the input end of the power supply isolation circuit is connected with the output end of the power supply conditioning circuit, and the power supply isolation circuit is used for isolating the 5V working voltage into a 5V safe voltage and converting the 5V working voltage into a 3.3V safe voltage; one end of the signal isolation circuit is connected with the front-end acquisition unit, and the other end of the signal isolation circuit is connected with the control circuit unit and is used for isolating a digital signal obtained by converting an electroencephalogram signal in the front-end acquisition unit from a digital signal in the control circuit unit; one end of the control circuit interface is connected with the signal isolation circuit, and the other end of the control circuit interface is connected with the control circuit unit; the USB connector is respectively connected with the control circuit interface and the upper computer, and the upper computer is in USB connection with the main circuit unit through the USB connector.
In one embodiment, the control circuit unit is arranged on a first printed circuit board, the front end acquisition unit is arranged on a second printed circuit board, and the main circuit unit is arranged on a third printed circuit board; the first printed circuit board is connected with the third printed circuit board through a control circuit interface arranged on the main circuit unit, so that the first printed circuit board and the third printed circuit board are stacked in an up-and-down space; the second printed circuit board is connected with the third printed circuit board through the front end sampling interface arranged on the main circuit unit, so that the second printed circuit board and the third printed circuit board are stacked in an up-and-down space.
In one embodiment, the control circuit unit comprises an FPGA chip, and an SDRAM chip and a USB control chip which are respectively in communication connection with the FPGA chip; the FPGA chip is used for receiving the electroencephalogram signals transmitted by the main circuit unit, processing the electroencephalogram signals, transmitting the processed electroencephalogram signals to the main circuit unit, receiving an acquisition instruction sent by the upper computer, and controlling the front-end acquisition unit to start signal acquisition according to the acquisition instruction; the SDRAM chip is used for carrying out data caching on the electroencephalogram signals; the USB control chip is used for controlling USB data communication between the FPGA chip and the main circuit unit.
In one embodiment, the control circuit unit further includes a clock circuit, and the clock circuit is configured to provide a system clock for the FPGA chip.
Drawings
FIG. 1 is a schematic structural diagram of an expandable high-density electroencephalogram acquisition device according to the present invention;
FIG. 2 is a schematic diagram of a signal conditioning circuit in an expandable high density electroencephalogram acquisition device according to the present invention;
FIG. 3 is a schematic diagram of a daisy chain connection structure between a plurality of front-end acquisition chips in an expandable high-density electroencephalogram acquisition device according to the present invention;
FIG. 4 is a schematic diagram of an anti-static protection circuit in an expandable high density electroencephalogram acquisition device according to the present invention;
FIG. 5 is a schematic diagram of a power isolation circuit in the expandable high density electroencephalogram acquisition device according to the present invention;
FIG. 6 is a schematic diagram of a signal isolation circuit in an expandable high-density electroencephalogram acquisition device according to the present invention;
fig. 7 is a schematic diagram of a power conditioning circuit in the expandable high-density electroencephalogram acquisition device of the present invention.
Detailed Description
Various embodiments of the present invention will be described in detail below with reference to the accompanying drawings so that the objects, features and advantages of the invention can be more clearly understood. It should be understood that the embodiments shown in the drawings are not intended as limitations on the scope of the invention, but are merely illustrative of the true spirit of the technical solution of the invention.
In the following description, for the purposes of illustrating various disclosed embodiments, certain specific details are set forth in order to provide a thorough understanding of the various disclosed embodiments. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of the specific details. In other instances, well-known devices, structures and techniques associated with this application may not be shown or described in detail to avoid unnecessarily obscuring the description of the embodiments.
Throughout the specification and claims, the word "comprise" and variations thereof, such as "comprises" and "comprising", will be understood to have an open, inclusive meaning, i.e., will be interpreted to mean "including, but not limited to", unless the context requires otherwise.
Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
As used in this specification and the appended claims, the singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. It should be noted that the term "or" is generally employed in its sense including "or/and" unless the context clearly dictates otherwise.
In the following description, for the sake of clarity, the structure and operation of the present invention will be described with the aid of directional terms, but the terms "front", "rear", "left", "right", "outer", "inner", "outer", "inward", "upper", "lower", etc. should be understood as words of convenience and not as words of limitation.
The utility model relates to an extensible high density brain electricity collection equipment, as shown in fig. 1, extensible high density brain electricity collection equipment include main circuit unit 2 and respectively with control circuit unit 3, a N front end collection unit 1 that main circuit unit 2 is connected, front end collection unit 1 can freely expand, is equipped with 8 front end collection units 1 in this embodiment. The main circuit unit 2 is in communication connection with the control circuit unit 3, a plurality of front end sampling interfaces 24 are arranged on the main circuit unit 2, each front end acquisition unit 1 is respectively connected to the front end sampling interfaces 24 on the main circuit unit 2, and each front end acquisition unit 1 is connected to the electroencephalogram sampling electrode 5. The front-end acquisition unit 1 is used for receiving the electroencephalogram signals acquired by the electroencephalogram sampling electrode 5. The front-end acquisition unit 1 connected with the front-end sampling interface 24 on the main circuit unit 2 synchronously acquires signals. The electroencephalogram signals received by the front-end acquisition units 1 are transmitted to the control circuit unit through the main circuit unit.
The front-end acquisition unit 1 comprises a conductive connector 10, a signal conditioning circuit 11 and a front-end acquisition chip 12 which are connected in sequence. The lead connector 10 is connected with the electroencephalogram sampling electrode 5, the front-end acquisition chip 12 is connected to a front-end sampling interface 24 on the main circuit unit 2, the signal conditioning circuit 11 is used for performing bandwidth limitation on electroencephalogram signals sent by the electroencephalogram sampling electrode 5 connected with the lead connector 10, and the front-end acquisition chip 12 is used for forwarding the received electroencephalogram signals sent by the signal conditioning circuit 11 to the main circuit unit 2.
The signal conditioning circuit 11 limits the bandwidth of the electroencephalogram signal by adopting a low-pass anti-aliasing filter, and is used for reducing the signal amplitude of which the amplitude is higher than the nyquist frequency. As shown in fig. 2, the signal conditioning circuit 11 forms a low-pass anti-aliasing filter by connecting a 4.7nF capacitor in series with a 4.99k ohm resistor, and performs bandwidth limitation on the input signal, thereby reducing the signal amplitude which is much higher than the nyquist frequency and improving the signal-to-noise ratio.
The number of the front-end acquisition chips 12 is multiple, in some examples, as shown in fig. 3, the number of the front-end acquisition chips 12 is 4, and the 4 front-end acquisition chips 12 are connected in a daisy chain manner to form 32 channels of sampling frequency to receive the electroencephalogram signals. The 8 front-end acquisition units form 256 channels, 24-bit synchronous sampling, low input reference noise and high sampling rate are adopted to acquire analog signals, analog signals are subjected to analog-to-digital conversion in an ADS1299 chip adopted by the front-end acquisition chip 12, and meanwhile, a programmable gain amplifier, an internal standard and an on-board oscillator are arranged in the ADS1299 chip adopted by the front-end acquisition chip 12, so that the size of the equipment is greatly reduced.
In some examples, the front-end acquisition unit 1 further includes an anti-static protection circuit, the anti-static protection circuit is connected to a connection point of the conductive connector 10 and the signal conditioning circuit 11, and the other end of the anti-static protection circuit is grounded. As shown in fig. 4, the anti-static protection circuit is two diodes connected oppositely, and 4 paths of anti-static protection are provided for 4 front-end acquisition chips 12.
The front-end acquisition units 1 are provided with a plurality of front-end acquisition units, in some examples, the number of the front-end acquisition units 1 can be 8 at most, and 8 front-end acquisition units 1 receive 8 paths of electroencephalogram signals in parallel, so that the total number of leads reaches 256 channels, and the high-density signal sampling requirement is met. One end of the front-end acquisition unit 1 is connected to one front-end sampling interface 24, and the other end of the front-end acquisition unit 1 is connected to the corresponding electroencephalogram sampling electrode 5; the front-end acquisition unit 1 is arranged to receive the electroencephalogram signals acquired by the electroencephalogram sampling electrode 5 and is transmitted to the control circuit unit 3 through the main circuit unit 2. The control circuit unit 3 performs data summarization and data caching on 8 paths of electroencephalogram signals formed by the 8 front-end acquisition units 1.
The main circuit unit 2 is used for transmitting the electroencephalogram signals to the control circuit unit 3 and transmitting the electroencephalogram signals cached by the control circuit unit 3 to the upper computer 4. The main circuit unit 2 comprises a power conditioning circuit 21, a power isolation circuit 22, a signal isolation circuit 23, a front-end acquisition interface 24, a control circuit interface 27, a DC power input interface 26 and a USB connector 25. The main circuit unit 2 is connected to the upper computer 4 through a USB communication line via a USB connector 25. The DC power input interface 26 is connected to a working power supply, the input end of the power conditioning circuit 21 is connected to the DC power input interface 26, the output end of the power conditioning circuit 21 is connected to the power isolation circuit 22, and the power conditioning circuit 21 is configured to convert the connected working power supply voltage into the 5V working voltage required by the main circuit unit 2 and the control circuit unit 3. As shown in fig. 7, in the power conditioning circuit 21, DC1 is connected to a 5V operating power supply voltage, and is connected in parallel to a capacitor C9 through a resistor L1 to form a preceding stage LC filter, and is filtered by an EMI filter FL1, and is output as a 5V operating voltage through a common mode filter L2 and a regulator chip U2, a fuse FH1 is connected between the resistor L1 and the EMI filter FL1, and a diode D1 is connected in parallel to the capacitor C9.
The input end of the power isolation circuit 22 is connected to the output end of the power conditioning circuit 21, and the power isolation circuit 22 is configured to isolate the 5V working voltage into a 5V safe voltage and convert the 5V working voltage into a 3.3V safe voltage. As shown in fig. 5, the isolation component U6 outputs a 5V safety voltage to power the main circuit unit 2 and the control circuit unit 3, and the isolation component U5 outputs a 3.3V safety voltage to power the front-end acquisition unit 1.
One end of the signal isolation circuit 23 is connected with the front-end acquisition unit 1 through the front-end acquisition interface 24, and the other end of the signal isolation circuit 23 is connected with the control circuit unit 3 through the control circuit interface 27, and is used for isolating digital signals obtained by converting electroencephalogram signals in the front-end acquisition unit from digital signals in the control circuit unit. As shown in fig. 6, the input and output terminals of the components U3 and U4 are respectively connected to the front-end acquisition chip 12 and the FPGA, so as to isolate the electroencephalogram signal in the front-end acquisition unit 1 from the digital signal in the control circuit unit 3, thereby reducing noise.
The front-end acquisition interface 24 is used for connecting the front-end acquisition unit 1, and the front-end acquisition unit 1 is stacked on the main circuit unit 2 through a front-end acquisition port. In some examples, the control circuit unit 3 is disposed on a first printed circuit board, the front end pickup unit 1 is disposed on a second printed circuit board, and the main circuit unit 2 is disposed on a third printed circuit board. The first printed circuit board is connected with the third printed circuit board through a control circuit interface 27 arranged on the main circuit unit 2, so that the first printed circuit board and the third printed circuit board are stacked in an up-down space. The second printed circuit board is connected with the third printed circuit board through the front end sampling interface 24 arranged on the main circuit unit 2, so that the second printed circuit board and the third printed circuit board are stacked in an up-down space. The control circuit interface 27 is used for connecting the control circuit unit 3, and the control circuit unit 3 is stacked on the main circuit unit 2 through the control circuit interface 27. The two types of printed circuit boards of the front-end acquisition unit 1 and the control circuit unit 3 and the third type of printed circuit board of the main circuit unit 2 at the bottom form a stacking design in space through a pin and female connection interface mode, so that the interior of the equipment is more compact, and the volume of the equipment is reduced.
The control circuit unit 3 receives the electroencephalogram signals transmitted by the main circuit unit 2, performs data aggregation and data caching on the electroencephalogram signals, and transmits the electroencephalogram signals to the main circuit unit 2. The control circuit unit 3 comprises an FPGA chip 31, and an SDRAM chip 32, a USB control chip 30 and a clock circuit 33 which are respectively connected with the FPGA chip 31 in a communication manner. The FPGA chip 31 is used for receiving the electroencephalogram signals transmitted by the main circuit unit 2, summing and caching the electroencephalogram signals, controlling the electroencephalogram signals to be transmitted to the main circuit unit 2, receiving an acquisition instruction sent by the upper computer 4, and controlling the front-end acquisition unit 1 to start signal acquisition according to the acquisition instruction. The SDRAM chip 32 is used for data caching of the filtered electroencephalogram signal. The USB control chip 30 is used for controlling USB data communication with the upper computer 4. The upper computer 4 sends an instruction to the FPGA chip 31 through the USB, and the FPGA sends data to the upper computer 4 through the USB. When the upper computer 4 sends a signal acquisition command, the FPGA independently controls 8 front-end acquisition units 1 and 8 SPI interfaces to work in parallel through 8 SPI interfaces, so that data acquisition is guaranteed to be parallel, and acquired data are gathered to a buffer area to be transmitted in the FPGA. The FPGA chip 31 is combined with the USB2.0 control chip, and the requirements of data acquisition and synchronous uploading which cannot be achieved by a common single chip microcomputer are met.
While the preferred embodiments of the present invention have been described in detail above, it should be understood that aspects of the embodiments can be modified, if necessary, to employ aspects, features and concepts of the various patents, applications and publications to provide yet further embodiments.
These and other changes can be made to the embodiments in light of the above detailed description. In general, in the claims, the terms used should not be construed to be limited to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled.
Claims (10)
1. An expandable high-density electroencephalogram acquisition device, comprising: the device comprises a main circuit unit, a control circuit unit and at least one front end acquisition unit; the main circuit unit is in communication connection with the control circuit unit, a plurality of front-end sampling interfaces are arranged on the main circuit unit, the front-end sampling units correspond to the electroencephalogram sampling electrodes one by one, one end of each front-end sampling unit is connected to one front-end sampling interface, and the other end of each front-end sampling unit is connected to the corresponding electroencephalogram sampling electrode; the front-end acquisition unit is arranged to receive the electroencephalogram signals acquired by the electroencephalogram sampling electrode and is transmitted to the control circuit unit through the main circuit unit;
the main circuit unit is used for receiving an acquisition instruction sent by an upper computer and transmitting the acquisition instruction to the control circuit unit;
and the control circuit unit is used for controlling the front end acquisition unit connected with the front end sampling interface on the main circuit unit to synchronously acquire signals based on the acquisition instruction.
2. The scalable high-density brain electrical acquisition device of claim 1, wherein each said front-end acquisition unit comprises: the system comprises a conductive connector, a signal conditioning circuit and a front end acquisition chip which are sequentially connected;
the lead connector is electrically connected with the electroencephalogram sampling electrode, and the front-end acquisition chip is connected to a front-end sampling interface on the main circuit unit;
the signal conditioning circuit is used for carrying out bandwidth limitation on electroencephalogram signals sent by the electroencephalogram sampling electrode connected with the lead connector;
the front-end acquisition chip is used for forwarding the received electroencephalogram signals sent by the signal conditioning circuit to the main circuit unit.
3. The scalable high-density electroencephalogram acquisition device of claim 2, wherein each front-end acquisition unit comprises a plurality of front-end acquisition chips, and the plurality of front-end acquisition chips are connected in a daisy chain manner.
4. The scalable high-density electroencephalogram acquisition device of claim 2, wherein each of said front-end acquisition units further comprises an anti-static protection circuit;
in each front-end acquisition unit, one end of the anti-static protection circuit is connected to the connection position of the conductive connector and the signal conditioning circuit, and the other end of the anti-static protection circuit is grounded.
5. The expandable high-density brain electrical acquisition device of claim 2, wherein the lead connector has 32 channels to connect to the brain electrical acquisition electrodes, the number of front-end acquisition units being 8.
6. The scalable high-density brain electrical acquisition device of claim 5, wherein the front-end acquisition chips are 8-channel sampling, the number of front-end acquisition chips being 4.
7. The scalable high-density electroencephalogram acquisition device of claim 1, wherein the main circuit unit further comprises a DC power input interface, a power conditioning circuit, a power isolation circuit, a signal isolation circuit, a control circuit interface, and a USB connector;
the DC power supply input interface is connected with a working power supply;
the input end of the power conditioning circuit is connected with the DC power input interface, the output end of the power conditioning circuit is connected with the power isolation circuit, and the power conditioning circuit is used for converting the accessed working power supply voltage into the 5V working voltage required by the main circuit unit and the control circuit unit;
the input end of the power supply isolation circuit is connected with the output end of the power supply conditioning circuit, and the power supply isolation circuit is used for isolating the 5V working voltage into a 5V safe voltage and converting the 5V working voltage into a 3.3V safe voltage;
one end of the signal isolation circuit is connected with the front-end acquisition unit, and the other end of the signal isolation circuit is connected with the control circuit unit and is used for isolating the electroencephalogram signals in the front-end acquisition unit from the digital signals in the control circuit unit;
one end of the control circuit interface is connected with the signal isolation circuit, and the other end of the control circuit interface is connected with the control circuit unit;
the USB connector is respectively connected with the control circuit interface and the upper computer, and the upper computer is in USB connection with the main circuit unit through the USB connector.
8. The scalable high-density electroencephalogram acquisition device of claim 1, wherein the control circuit unit is disposed on a first printed circuit board, the front-end acquisition unit is disposed on a second printed circuit board, and the main circuit unit is disposed on a third printed circuit board;
the first printed circuit board is connected with the third printed circuit board through a control circuit interface arranged on the main circuit unit, so that the first printed circuit board and the third printed circuit board are stacked in an up-and-down space;
the second printed circuit board is connected with the third printed circuit board through the front end sampling interface arranged on the main circuit unit, so that the second printed circuit board and the third printed circuit board are stacked in an up-and-down space.
9. The scalable high-density electroencephalogram acquisition device of claim 1, wherein the control circuit unit comprises an FPGA chip, and an SDRAM chip and a USB control chip which are in communication connection with the FPGA chip respectively;
the FPGA chip is used for receiving the electroencephalogram signals transmitted by the main circuit unit, processing the electroencephalogram signals, transmitting the processed electroencephalogram signals to the main circuit unit, receiving an acquisition instruction sent by the upper computer, and controlling the front-end acquisition unit to start signal acquisition according to the acquisition instruction;
the SDRAM chip is used for carrying out data caching on the electroencephalogram signals;
the USB control chip is used for controlling USB data communication between the FPGA chip and the main circuit unit.
10. The scalable high-density electroencephalograph acquisition device of claim 9, wherein the control circuit unit further comprises a clock circuit for providing a system clock for the FPGA chip.
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| CN202223120376.5U CN218675744U (en) | 2022-11-23 | 2022-11-23 | Extensible high-density electroencephalogram acquisition equipment |
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| CN202223120376.5U CN218675744U (en) | 2022-11-23 | 2022-11-23 | Extensible high-density electroencephalogram acquisition equipment |
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