CN218630071U - Power semiconductor device resistance and capacitance integrated stand-alone tester - Google Patents

Abstract

The utility model relates to a power semiconductor device resistance-capacitance integration unit tester for realize power semiconductor device's input resistance, input capacitance, output capacitance, reverse capacitance multichannel scan test under different direct current bias voltage conditions, including control circuit, LCR test circuit, grid bias voltage circuit, drain electrode bias voltage circuit and multichannel isolator matrix circuit. The resistance-capacitance integrated single tester for the power semiconductor device integrates the control circuit, the LCR test circuit, the grid bias circuit, the drain bias circuit and the multi-channel isolating switch matrix circuit into a single tester, is simple to operate and convenient to maintain, has lower manufacturing cost, and greatly improves the test precision and the test efficiency.

Description

Power semiconductor device resistance and capacitance integrated stand-alone tester

technical field

The utility model is mainly applied to the multi-channel scanning test of the input resistance Rg, the input capacitance Ciss, the output capacitance Coss and the reverse capacitance Crss of power semiconductor devices (such as MOSFET, IGBT, etc.) under the DC bias voltage, and particularly relates to a power semiconductor Device resistance and capacitance integrated stand-alone tester.

Background technique

With the rapid development of my country's new energy vehicles and photovoltaic power generation and energy storage industries, power semiconductor devices (MOSFET, IGBT, etc.) are more and more widely used, with increasing demand and higher performance. The miniaturization and high power density of power semiconductor devices are the main directions of development, requiring power semiconductor devices to work at higher frequencies. Since the resistance and capacitance parameters of power semiconductor devices will affect the frequency characteristics of the product, more and more attention has been paid to them. Taking MOSFET as an example, the input resistance Rg, input capacitance Ciss, output capacitance Coss, and reverse capacitance Crss will directly affect the switching characteristics of the power semiconductor device.

At present, the resistance and capacitance test equipment on the market is integrated by the independent function stand-alone through the host computer software. The functional stand-alone mainly includes: LCR tester, grid bias power supply, drain bias power supply, isolation switch matrix, industrial computer, etc. The disadvantages of the system integration scheme are: poor precision, low efficiency, high cost, large volume, complicated operation, difficult maintenance, and unable to meet customers' accurate measurement of resistance and capacitance parameters of power devices.

Utility model content

In order to solve the above problems, the utility model discloses a power semiconductor device resistance and capacitance integrated stand-alone tester, which realizes multi-channel power semiconductor input resistance Rg, input capacitance Ciss, output capacitance Coss, and reverse capacitance Crss under bias conditions Scan test.

The utility model provides a stand-alone integrated tester for resistance and capacitance of power semiconductor devices, which is used to realize multi-channel scanning tests of input resistance, input capacitance, output capacitance and reverse capacitance of power semiconductor devices under different DC bias voltage conditions. Including control circuit, LCR test circuit, gate bias circuit, drain bias circuit and multi-channel isolation switch matrix circuit;

The control circuit is respectively connected with the LCR test circuit, the gate bias circuit, the drain bias circuit, and the multi-channel isolation switch matrix circuit, and the multi-channel isolation switch matrix circuit is respectively connected with the LCR test circuit, the grid bias circuit, and the drain bias circuit. The voltage circuit and the power component under test are connected.

Wherein, the LCR test circuit is used to realize the parameter test of the input resistance, input capacitance, output capacitance and reverse capacitance of the power semiconductor device under the set test level, test frequency and bias voltage.

Wherein, the gate bias circuit is used to provide a set of wide-range adjustable positive and negative DC power supplies to adapt to different types of power devices, and is applied between the gate and source of power semiconductor devices to realize the control of semiconductor power Device on-off control.

Wherein, the drain DC voltage bias circuit is used to provide a set of wide-range adjustable DC power, which is applied between the drain and the source of the power semiconductor device, as the power device between the drain and the source bias voltage.

Wherein, the multi-channel isolating switch matrix circuit realizes circuit switching of different resistance and capacitance parameters of power semiconductor devices through relay matrix switching, and simultaneously realizes multi-channel scanning test of multiple semiconductor power devices through relay matrix.

Wherein, the control circuit implements the setting of the parameters of the LCR test circuit, the control of the gate bias circuit and the drain bias circuit, the switching of the channels and parameters of the multi-channel isolation switch matrix circuit, and completes the test of the parameters of the power semiconductor device.

The beneficial effects of the utility model are: the power semiconductor device resistance and capacitance integrated stand-alone tester integrates the control circuit, LCR test circuit, gate bias circuit, drain bias circuit and multi-channel isolation switch matrix circuit into a single instrument Among them, the operation is simple, the maintenance is convenient, the production cost is lower, and the test accuracy and test efficiency are greatly improved.

Description of drawings

Fig. 1 is the system block diagram of the power semiconductor device resistance-capacitance integrated stand-alone tester of the utility model;

Fig. 2 is a schematic circuit diagram of the integrated stand-alone tester for resistance and capacitance of power semiconductor devices of the present invention.

Detailed ways

The preferred embodiments of the utility model will be described in detail below in conjunction with the accompanying drawings, so that the advantages and features of the utility model can be more easily understood by those skilled in the art, so as to make a clearer definition of the protection scope of the utility model.

As shown in Figure 1, a power semiconductor device resistance and capacitance integrated stand-alone tester includes a control circuit, an LCR test circuit, a gate bias circuit, a drain bias circuit and a multi-channel isolation switch matrix circuit. The LCR test circuit, the gate bias circuit, the drain bias circuit, and the multi-channel isolation switch matrix circuit are connected, and the multi-channel isolation switch matrix circuit is connected with the LCR test circuit, the gate bias circuit, the drain bias circuit, and the connected to the power measuring device.

The utility model can realize the multi-channel scanning test of MOSFET and IGBT modules, including single-channel test application. The utility model is described by taking MOSFET as an example, and is also applicable to IGBT and power triode, without limiting the scope of application of the utility model.

The control circuit is composed of MCU, FPGA and CPLD, and is used to control each module and perform calculation and analysis of data. The control circuit is connected with an LCR test circuit, a gate bias circuit, a drain bias circuit, and a multi-channel isolation switch matrix circuit.

As shown in Figure 2, the LCR test circuit is used to generate the signal source and sample the voltage signal, so as to send it to the control circuit for impedance calculation. The LCR test circuit is composed of an AC signal source Vs, a current limiting resistor R4, a balanced operational amplifier U1, a variable resistor R3, a voltage sampling circuit Vu, and a voltage sampling circuit Vi. The AC signal source Vs produces a sinusoidal AC signal whose amplitude and frequency are determined by the panel settings. The AC signal source Vs is connected to the current limiting resistor R4. The current limiting resistor R4 limits the upper limit of the output current of the signal source to prevent the external short circuit from burning out the signal source circuit or the DUT. One end of the current limiting resistor R4 is connected to the AC signal source Vs, and the other end is connected to the relay matrix (such as S14 of channel 1). Pin 2 of the balanced op amp U1 is connected to the relay matrix (such as S11 of channel 1), and also connected to the variable resistor R3; pin 3 of the balanced op amp U1 is connected to the ground; pin 6 of the balanced op amp U1 is connected to the variable resistor R3 another side. According to the working principle of the operational amplifier, it can be seen that all the current flowing through the DUT flows through the variable resistor R3. The variable resistor R3 can adjust the size of the resistor according to the difference of the flowing current, so that the voltage across the variable resistor R3 is within a certain range, which is beneficial to improve the measurement accuracy. Both ends of the voltage sampling circuit Vu are connected to the relay matrix (as shown in channel 1, one end is connected to S12 and the other end is connected to S13), which is used to sample the voltage at both ends of the DUT and send it to the control circuit for processing. Both ends of the voltage sampling circuit Vi are respectively connected to both ends of the variable resistor R3 for sampling the voltage at both ends of the variable resistor R3 and sending it to the control circuit for processing.

The gate bias circuit is used to provide bias voltage to the gate of the power semiconductor device, so that the power semiconductor is in different degrees of conduction state. As shown in Figure 2, the gate bias circuit is connected to the signal source. The gate bias circuit is a DC voltage source.

The drain bias circuit is used to provide a bias voltage to the power semiconductor drain. As shown in Figure 2, the drain bias circuit consists of a high-voltage DC power supply circuit and a current-limiting resistor R1. The high voltage DC power supply circuit is connected to one end of the current limiting resistor R1. A high voltage power supply circuit generates a DC voltage. The other end of the current-limiting resistor R1 is connected to the relay matrix (such as S18 of channel 1), which is used to limit the maximum output current of the high-voltage DC power supply and to protect the instrument.

The multi-channel isolating switch matrix circuit is used for signal switching when different channels and different parameters are tested. Take the Ciss of channel 1 as an example: one end of S18 is connected to the current limiting resistor R1, and the other end is connected to the test point D to control the access of DC voltage; one end of S14 is connected to the current limiting resistor R4, and the other end is connected to the test point G. One end is connected to pin 2 of the balanced operational amplifier U1, and the other end is connected to pin 2 of S16 to control whether the AC signal source is connected to channel 1; one end of S13 is connected to the voltage sampling circuit Vu, the other end is connected to the test point G, and the other end of S12 is connected to The voltage sampling circuit Vu is connected, and one end is connected to the 2-pin of S15. S12 and S13 are used to control whether the voltage sampling circuit Vu is connected to channel 1; S15 and S16 are single-pole double-throw relays. Their 2-pin connection is as mentioned above. Pin 1 is connected to test point S, pin 3 is connected to DC blocking capacitor C13, pin 1 of S16 is connected to test point S, pin 3 is connected to DC blocking capacitor C12, S15 and S16 are used to control whether test point D or S is connected to the LCR test circuit; One end of the straight capacitors C12 and C13 is connected as mentioned above, and the other end is connected to the test point D, which is used to prevent the drain bias voltage from being applied to the LCR test circuit and affect the test of the LCR test circuit; one end of S17 is connected to the test point D, One end is connected to the short-circuit capacitor S17, and the other end of the short-circuit capacitor S17 is connected to the test point S, and the short-circuit capacitor short-circuits DS.

The following is an example to illustrate, as shown in Figure 2, the test is 1 channel, the test parameter is Ciss, the test frequency is 1MHz, the test level is 100mV, the drain bias Vds is 1500V, and the gate bias voltage is 0V;

The test steps are as follows:

Step 1: Turn on the switches S11, S12, S13, S14, S18 and connect to channel 1;

Step 2: Connect the 1 and 2 interfaces of S15, connect the 1 and 2 interfaces of S16, connect S17, and prepare for the Ciss parameter test of DUT1;

Step 3: Control the test frequency of the AC signal source to 1MHz;

Step 4: Control the AC signal source test level to 100mV;

Step 5: Control the gate bias power supply to output 0V, and apply it between the gate and source of the DUT1;

Step 6: Control the drain bias power supply to output 1500V, and apply it between the drain and source of the DUT1;

Step 7: After waiting for the bias voltage to stabilize, control the LCR to test the capacitance parameter Ciss;

Step 8: Send the test results to the instrument for display or send them to the host computer through the interface according to customer needs;

Repeat the above steps 1 to 8 until the other tests for setting the channel DUT parameters are completed.

Finally, it should be noted that the above examples are only specific implementations of the utility model, used to illustrate the technical solutions of the utility model, rather than limiting it, and the scope of protection of the utility model is not limited thereto, although referring to The aforementioned embodiments have described the utility model in detail, and those of ordinary skill in the art should understand that: any person familiar with the technical field can still use the technology described in the aforementioned embodiments within the technical scope disclosed in the utility model Modifications or changes can be easily imagined in the scheme, or equivalent replacement of some of the technical features; and these modifications, changes or replacements do not make the essence of the corresponding technical solution deviate from the spirit and scope of the technical solution of the embodiment of the utility model. Covered within the protection scope of the present utility model. Therefore, the protection scope of the present utility model should be based on the protection scope of the claims.

Claims (6)

1. A resistance-capacitance integrated single-machine tester for a power semiconductor device is characterized in that: the multi-channel scan test circuit is used for realizing multi-channel scan test of an input resistor, an input capacitor, an output capacitor and a reverse capacitor of a power semiconductor device under different direct-current bias voltage conditions, and comprises a control circuit, an LCR test circuit, a grid bias circuit, a drain bias circuit and a multi-channel isolating switch matrix circuit;

the control circuit is respectively connected with the LCR test circuit, the grid bias circuit, the drain bias circuit and the multichannel isolating switch matrix circuit, and the multichannel isolating switch matrix circuit is respectively connected with the LCR test circuit, the grid bias circuit, the drain bias circuit and the tested power device.

2. The resistance-capacitance integrated single-machine tester for the power semiconductor device according to claim 1, characterized in that: the LCR test circuit is used for realizing parameter test of the input resistor, the input capacitor, the output capacitor and the reverse capacitor of the power semiconductor device under the set test level, test frequency and bias voltage.

3. The resistance-capacitance integrated single-machine tester for the power semiconductor device according to claim 1, characterized in that: the grid bias circuit is used for providing a group of positive and negative direct current power supplies with adjustable wide range, and the positive and negative direct current power supplies are applied between the grid and the source of the power semiconductor device to realize on-off control of the semiconductor power device.

4. The resistance-capacitance integrated single-machine tester for the power semiconductor device according to claim 1, characterized in that: the drain direct-current voltage bias circuit is used for providing a group of wide-range adjustable direct-current power supplies, is applied between the drain and the source of the power semiconductor device and is used as bias voltage between the drain and the source of the power device.

5. The resistance-capacitance integrated single-machine tester for the power semiconductor device according to claim 1, characterized in that: the multi-channel isolating switch matrix circuit realizes the circuit switching of different resistance and capacitance parameters of the power semiconductor devices through the relay matrix switching, and simultaneously realizes the multi-channel scanning test of a plurality of semiconductor power devices through the relay matrix.

6. The resistance-capacitance integrated single-machine tester for the power semiconductor device according to claim 1, characterized in that: the control circuit realizes the setting of LCR test circuit parameters, the control of the grid bias circuit and the drain bias circuit, the switching of the channels and the parameters of the multichannel isolating switch matrix circuit and completes the test of the parameters of the power semiconductor device.

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