CN218630071U - Power semiconductor device resistance and capacitance integrated stand-alone tester - Google Patents

Power semiconductor device resistance and capacitance integrated stand-alone tester Download PDF

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CN218630071U
CN218630071U CN202222929579.2U CN202222929579U CN218630071U CN 218630071 U CN218630071 U CN 218630071U CN 202222929579 U CN202222929579 U CN 202222929579U CN 218630071 U CN218630071 U CN 218630071U
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circuit
power semiconductor
test
semiconductor device
capacitance
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高志齐
武胜强
李春生
周剑
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Changzhou Tonghui Electronics Co ltd
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Abstract

The utility model relates to a power semiconductor device resistance-capacitance integration unit tester for realize power semiconductor device's input resistance, input capacitance, output capacitance, reverse capacitance multichannel scan test under different direct current bias voltage conditions, including control circuit, LCR test circuit, grid bias voltage circuit, drain electrode bias voltage circuit and multichannel isolator matrix circuit. The resistance-capacitance integrated single tester for the power semiconductor device integrates the control circuit, the LCR test circuit, the grid bias circuit, the drain bias circuit and the multi-channel isolating switch matrix circuit into a single tester, is simple to operate and convenient to maintain, has lower manufacturing cost, and greatly improves the test precision and the test efficiency.

Description

功率半导体器件电阻电容一体化单机测试仪Power semiconductor device resistance and capacitance integrated stand-alone tester

技术领域technical field

本实用新型主要应用于功率半导体器件(例如MOSFET、IGBT等)的输入电阻Rg、输入电容Ciss、输出电容Coss、反向电容Crss在直流偏置电压下多通道扫描测试,尤其涉及一种功率半导体器件电阻电容一体化单机测试仪。The utility model is mainly applied to the multi-channel scanning test of the input resistance Rg, the input capacitance Ciss, the output capacitance Coss and the reverse capacitance Crss of power semiconductor devices (such as MOSFET, IGBT, etc.) under the DC bias voltage, and particularly relates to a power semiconductor Device resistance and capacitance integrated stand-alone tester.

背景技术Background technique

随着我国新能源汽车、光伏发电储能行业的飞速发展,功率半导体器件(MOSFET,IGBT等)的应用越来越广,需求越来越大,性能越来越高。功率半导体器件的小型化和高功率密度是发展的主要方向,要求功率半导体器件工作在更高的频率上。由于功率半导体器件的电阻电容参数会影响到产品的频率特性,因此越来越受到重视。以MOSFET为例,输入电阻Rg、输入电容Ciss、输出电容Coss、反向电容Crss会直接影响到功率半导体器件的开关特性。With the rapid development of my country's new energy vehicles and photovoltaic power generation and energy storage industries, power semiconductor devices (MOSFET, IGBT, etc.) are more and more widely used, with increasing demand and higher performance. The miniaturization and high power density of power semiconductor devices are the main directions of development, requiring power semiconductor devices to work at higher frequencies. Since the resistance and capacitance parameters of power semiconductor devices will affect the frequency characteristics of the product, more and more attention has been paid to them. Taking MOSFET as an example, the input resistance Rg, input capacitance Ciss, output capacitance Coss, and reverse capacitance Crss will directly affect the switching characteristics of the power semiconductor device.

目前市场上的电阻电容测试设备均由独立功能单机通过上位机软件进行系统集成。功能单机主要包括:LCR测试仪、栅极偏压电源、漏极偏压电源,隔离开关矩阵、工业电脑等。系统集成方案的缺点是:精度差,效率低,成本高,体积大,操作复杂,维护困难,无法满足客户对功率器件电阻电容参数精确测量。At present, the resistance and capacitance test equipment on the market is integrated by the independent function stand-alone through the host computer software. The functional stand-alone mainly includes: LCR tester, grid bias power supply, drain bias power supply, isolation switch matrix, industrial computer, etc. The disadvantages of the system integration scheme are: poor precision, low efficiency, high cost, large volume, complicated operation, difficult maintenance, and unable to meet customers' accurate measurement of resistance and capacitance parameters of power devices.

实用新型内容Utility model content

为了解决上述问题,本实用新型公开了一种功率半导体器件电阻电容一体化单机测试仪,实现了功率半导体输入电阻Rg、输入电容Ciss、输出电容Coss、反向电容Crss在偏压条件下多通道扫描测试。In order to solve the above problems, the utility model discloses a power semiconductor device resistance and capacitance integrated stand-alone tester, which realizes multi-channel power semiconductor input resistance Rg, input capacitance Ciss, output capacitance Coss, and reverse capacitance Crss under bias conditions Scan test.

本实用新型提供一种功率半导体器件电阻电容一体化单机测试仪,用于实现功率半导体器件的输入电阻、输入电容、输出电容、反向电容在不同直流偏置电压条件下的多通道扫描测试,包括控制电路、LCR测试电路、栅极偏压电路、漏极偏压电路及多通道隔离开关矩阵电路;The utility model provides a stand-alone integrated tester for resistance and capacitance of power semiconductor devices, which is used to realize multi-channel scanning tests of input resistance, input capacitance, output capacitance and reverse capacitance of power semiconductor devices under different DC bias voltage conditions. Including control circuit, LCR test circuit, gate bias circuit, drain bias circuit and multi-channel isolation switch matrix circuit;

控制电路分别与LCR测试电路、栅极偏压电路、漏极偏压电路、多通道隔离开关矩阵电路相连接,多通道隔离开关矩阵电路分别与LCR测试电路、栅极偏压电路、漏极偏压电路、被测功率件相连接。The control circuit is respectively connected with the LCR test circuit, the gate bias circuit, the drain bias circuit, and the multi-channel isolation switch matrix circuit, and the multi-channel isolation switch matrix circuit is respectively connected with the LCR test circuit, the grid bias circuit, and the drain bias circuit. The voltage circuit and the power component under test are connected.

其中,所述LCR测试电路用于在设定的测试电平、测试频率、偏置电压下实现功率半导体器件输入电阻、输入电容、输出电容、反向电容的参数测试。Wherein, the LCR test circuit is used to realize the parameter test of the input resistance, input capacitance, output capacitance and reverse capacitance of the power semiconductor device under the set test level, test frequency and bias voltage.

其中,所述栅极偏压电路用于提供一组宽范围可调的正负直流电源,以适应不同类型的功率器件,施加于功率半导体器件的栅极和源极之间,实现对半导体功率器件的通断控制。Wherein, the gate bias circuit is used to provide a set of wide-range adjustable positive and negative DC power supplies to adapt to different types of power devices, and is applied between the gate and source of power semiconductor devices to realize the control of semiconductor power Device on-off control.

其中,所述漏极直流电压偏置电路用于提供一组宽范围可调的直流电源,施加于功率半导体器件的漏极和源极之间,作为功率器件的漏极和源极之间的偏置电压。Wherein, the drain DC voltage bias circuit is used to provide a set of wide-range adjustable DC power, which is applied between the drain and the source of the power semiconductor device, as the power device between the drain and the source bias voltage.

其中,所述多通道隔离开关矩阵电路通过继电器矩阵切换,实现对功率半导体器件不同电阻电容参数的电路切换,同时通过继电器矩阵实现多个半导体功率器件的多通道扫描测试。Wherein, the multi-channel isolating switch matrix circuit realizes circuit switching of different resistance and capacitance parameters of power semiconductor devices through relay matrix switching, and simultaneously realizes multi-channel scanning test of multiple semiconductor power devices through relay matrix.

其中,所述控制电路实现LCR测试电路参数的设置,栅极偏压电路和漏极偏压电路的控制,多通道隔离开关矩阵电路的通道和参数的切换,并完成功率半导体器件参数的测试。Wherein, the control circuit implements the setting of the parameters of the LCR test circuit, the control of the gate bias circuit and the drain bias circuit, the switching of the channels and parameters of the multi-channel isolation switch matrix circuit, and completes the test of the parameters of the power semiconductor device.

本实用新型的有益效果是:该功率半导体器件电阻电容一体化单机测试仪将控制电路、LCR测试电路、栅极偏压电路、漏极偏压电路及多通道隔离开关矩阵电路集成于单台仪器中,操作简单、维护方便,制作成本更低,大大提高了测试精度及测试效率。The beneficial effects of the utility model are: the power semiconductor device resistance and capacitance integrated stand-alone tester integrates the control circuit, LCR test circuit, gate bias circuit, drain bias circuit and multi-channel isolation switch matrix circuit into a single instrument Among them, the operation is simple, the maintenance is convenient, the production cost is lower, and the test accuracy and test efficiency are greatly improved.

附图说明Description of drawings

图1为本实用新型的功率半导体器件电阻电容一体化单机测试仪的系统框图;Fig. 1 is the system block diagram of the power semiconductor device resistance-capacitance integrated stand-alone tester of the utility model;

图2为本实用新型的功率半导体器件电阻电容一体化单机测试仪的电路原理图。Fig. 2 is a schematic circuit diagram of the integrated stand-alone tester for resistance and capacitance of power semiconductor devices of the present invention.

具体实施方式Detailed ways

下面结合附图对本实用新型的较佳实施例进行详细阐述,以使本实用新型的优点和特征能更易被本领域人员理解,从而对本实用新型的保护范围做出更为清楚明确的界定。The preferred embodiments of the utility model will be described in detail below in conjunction with the accompanying drawings, so that the advantages and features of the utility model can be more easily understood by those skilled in the art, so as to make a clearer definition of the protection scope of the utility model.

如图1所示的一种功率半导体器件电阻电容一体化单机测试仪,包括控制电路、LCR测试电路、栅极偏压电路、漏极偏压电路及多通道隔离开关矩阵电路,控制电路分别与LCR测试电路、栅极偏压电路、漏极偏压电路、多通道隔离开关矩阵电路相连接,多通道隔离开关矩阵电路分别与LCR测试电路、栅极偏压电路、漏极偏压电路、被测功率件相连接。As shown in Figure 1, a power semiconductor device resistance and capacitance integrated stand-alone tester includes a control circuit, an LCR test circuit, a gate bias circuit, a drain bias circuit and a multi-channel isolation switch matrix circuit. The LCR test circuit, the gate bias circuit, the drain bias circuit, and the multi-channel isolation switch matrix circuit are connected, and the multi-channel isolation switch matrix circuit is connected with the LCR test circuit, the gate bias circuit, the drain bias circuit, and the connected to the power measuring device.

本实用新型可以实现MOSFET、IGBT模块多通道扫描测试,包含单通道测试应用。本实用新型以MOSFET为例进行说明,同样也适用于IGBT和功率三极管,不限制本实用新型的应用范围。The utility model can realize the multi-channel scanning test of MOSFET and IGBT modules, including single-channel test application. The utility model is described by taking MOSFET as an example, and is also applicable to IGBT and power triode, without limiting the scope of application of the utility model.

所述的控制电路由MCU、FPGA、CPLD构成,用于对各个模块进行控制和进行数据的计算分析。控制电路连接有LCR测试电路、栅极偏压电路、漏极偏压电路、多通道隔离开关矩阵电路。The control circuit is composed of MCU, FPGA and CPLD, and is used to control each module and perform calculation and analysis of data. The control circuit is connected with an LCR test circuit, a gate bias circuit, a drain bias circuit, and a multi-channel isolation switch matrix circuit.

如图2所示,LCR测试电路用于信号源的产生、电压信号的采样,以便送给控制电路进行阻抗的计算。LCR测试电路由交流信号源Vs、限流电阻R4、平衡运放U1、可变电阻R3、电压采样电路Vu、电压采样电路Vi组成。交流信号源Vs产生正弦交流信号,它的幅值和频率由面板设置决定。交流信号源Vs与限流电阻R4连接。限流电阻R4限制信号源输出的电流上限,防止外部短路烧坏信号源电路或被测件。限流电阻R4一端与交流信号源Vs连接,另外一端与继电器矩阵连接(如通道1的S14)。平衡运放U1的2脚与继电器矩阵(如通道1的S11)连接,也与可变电阻R3连接;平衡运放U1的3脚与地连接;平衡运放U1的6脚与可变电阻R3另一端。根据运算放大器的工作原理可知流过被测件的电流全部从可变电阻R3流过。可变电阻R3可根据流过电流的不同调节电阻大小,使可变电阻R3两端的电压在一定范围内,有利于提高测量精度。电压采样电路Vu两端都与继电器矩阵连接(如通道1所示,一端接S12,一端接S13),用于采样被测件两端的电压送给控制电路处理。电压采样电路Vi两端分别与可变电阻R3两端连接,用于采样可变电阻R3两端电压送给控制电路处理。As shown in Figure 2, the LCR test circuit is used to generate the signal source and sample the voltage signal, so as to send it to the control circuit for impedance calculation. The LCR test circuit is composed of an AC signal source Vs, a current limiting resistor R4, a balanced operational amplifier U1, a variable resistor R3, a voltage sampling circuit Vu, and a voltage sampling circuit Vi. The AC signal source Vs produces a sinusoidal AC signal whose amplitude and frequency are determined by the panel settings. The AC signal source Vs is connected to the current limiting resistor R4. The current limiting resistor R4 limits the upper limit of the output current of the signal source to prevent the external short circuit from burning out the signal source circuit or the DUT. One end of the current limiting resistor R4 is connected to the AC signal source Vs, and the other end is connected to the relay matrix (such as S14 of channel 1). Pin 2 of the balanced op amp U1 is connected to the relay matrix (such as S11 of channel 1), and also connected to the variable resistor R3; pin 3 of the balanced op amp U1 is connected to the ground; pin 6 of the balanced op amp U1 is connected to the variable resistor R3 another side. According to the working principle of the operational amplifier, it can be seen that all the current flowing through the DUT flows through the variable resistor R3. The variable resistor R3 can adjust the size of the resistor according to the difference of the flowing current, so that the voltage across the variable resistor R3 is within a certain range, which is beneficial to improve the measurement accuracy. Both ends of the voltage sampling circuit Vu are connected to the relay matrix (as shown in channel 1, one end is connected to S12 and the other end is connected to S13), which is used to sample the voltage at both ends of the DUT and send it to the control circuit for processing. Both ends of the voltage sampling circuit Vi are respectively connected to both ends of the variable resistor R3 for sampling the voltage at both ends of the variable resistor R3 and sending it to the control circuit for processing.

栅极偏压电路用于给功率半导体器件栅极提供偏置电压,使功率半导体处于不同程度的导通状态。如图2所示,栅极偏压电路与信号源连接。栅极偏压电路是一个直流电压源。The gate bias circuit is used to provide bias voltage to the gate of the power semiconductor device, so that the power semiconductor is in different degrees of conduction state. As shown in Figure 2, the gate bias circuit is connected to the signal source. The gate bias circuit is a DC voltage source.

漏极偏压电路用于给功率半导体漏极提供偏置电压。如图2所示,漏极偏压电路由高压直流电源电路和限流电阻R1组成。高压直流电源电路与限流电阻R1一端连接。高压电源电路产生直流电电压。限流电阻R1另一端与继电器矩阵(如通道1的S18)连接,用于限制高压直流电源的最大输出电流,用于保护仪器。The drain bias circuit is used to provide a bias voltage to the power semiconductor drain. As shown in Figure 2, the drain bias circuit consists of a high-voltage DC power supply circuit and a current-limiting resistor R1. The high voltage DC power supply circuit is connected to one end of the current limiting resistor R1. A high voltage power supply circuit generates a DC voltage. The other end of the current-limiting resistor R1 is connected to the relay matrix (such as S18 of channel 1), which is used to limit the maximum output current of the high-voltage DC power supply and to protect the instrument.

多通道隔离开关矩阵电路用于不同通道、不同参数测试时的信号切换。以通道1的Ciss为例:S18一端与限流电阻R1连接,一端与测试点D连接,用于控制直流电压的接入;S14一端接限流电阻R4连接,一端与测试点G连接,S11一端与平衡运放U1的2脚连接,一端与S16的2脚连接,用于控制交流信号源是否接入通道1;S13一端与电压采样电路Vu连接,一端与测试点G连接,S12一端与电压采样电路Vu连接,一端与S15的2脚连接,S12、S13用于控制电压采样电路Vu是否接入通道1;S15、S16是单刀双掷继电器,它们2脚连接如前所述,S15的1脚连接测试点S,3脚连接隔直电容C13,S16的1脚连接测试点S,3脚连接隔直电容C12,S15、S16用于控制测试点D还是S接入LCR测试电路;隔直电容C12、C13一端连接如前所述,另一端连接为测试点D上,用于防止漏极偏置电压施加到LCR测试电路中,影响LCR测试电路测试;S17一端与测试点D连接,一端与短路电容S17连接,短路电容S17另一端与测试点S连接,短路电容是使DS短路。The multi-channel isolating switch matrix circuit is used for signal switching when different channels and different parameters are tested. Take the Ciss of channel 1 as an example: one end of S18 is connected to the current limiting resistor R1, and the other end is connected to the test point D to control the access of DC voltage; one end of S14 is connected to the current limiting resistor R4, and the other end is connected to the test point G. One end is connected to pin 2 of the balanced operational amplifier U1, and the other end is connected to pin 2 of S16 to control whether the AC signal source is connected to channel 1; one end of S13 is connected to the voltage sampling circuit Vu, the other end is connected to the test point G, and the other end of S12 is connected to The voltage sampling circuit Vu is connected, and one end is connected to the 2-pin of S15. S12 and S13 are used to control whether the voltage sampling circuit Vu is connected to channel 1; S15 and S16 are single-pole double-throw relays. Their 2-pin connection is as mentioned above. Pin 1 is connected to test point S, pin 3 is connected to DC blocking capacitor C13, pin 1 of S16 is connected to test point S, pin 3 is connected to DC blocking capacitor C12, S15 and S16 are used to control whether test point D or S is connected to the LCR test circuit; One end of the straight capacitors C12 and C13 is connected as mentioned above, and the other end is connected to the test point D, which is used to prevent the drain bias voltage from being applied to the LCR test circuit and affect the test of the LCR test circuit; one end of S17 is connected to the test point D, One end is connected to the short-circuit capacitor S17, and the other end of the short-circuit capacitor S17 is connected to the test point S, and the short-circuit capacitor short-circuits DS.

下面举例进行说明,如图2所示,测试为1通道,测试参数为Ciss,测试频率为1MHz,测试电平为100mV,漏极偏压Vds为1500V,栅极偏置电压为0V;The following is an example to illustrate, as shown in Figure 2, the test is 1 channel, the test parameter is Ciss, the test frequency is 1MHz, the test level is 100mV, the drain bias Vds is 1500V, and the gate bias voltage is 0V;

测试步骤如下:The test steps are as follows:

步骤1:接通开关S11、S12、S13、S14、S18,连接通道1;Step 1: Turn on the switches S11, S12, S13, S14, S18 and connect to channel 1;

步骤2:接通S15的1和2接口,接通S16的1和2接口,S17接通,对被测件DUT1的Ciss参数测试做好准备;Step 2: Connect the 1 and 2 interfaces of S15, connect the 1 and 2 interfaces of S16, connect S17, and prepare for the Ciss parameter test of DUT1;

步骤3:控制交流信号源测试频率为1MHz;Step 3: Control the test frequency of the AC signal source to 1MHz;

步骤4:控制交流信号源测试电平为100mV;Step 4: Control the AC signal source test level to 100mV;

步骤5:控制栅极偏压电源输出0V,施加到被测件DUT1的栅极和源极之间;Step 5: Control the gate bias power supply to output 0V, and apply it between the gate and source of the DUT1;

步骤6:控制漏极偏压电源输出1500V,施加到被测件DUT1的漏极和源极之间;Step 6: Control the drain bias power supply to output 1500V, and apply it between the drain and source of the DUT1;

步骤7:等待偏置电压稳定后,控制LCR测试电容参数Ciss;Step 7: After waiting for the bias voltage to stabilize, control the LCR to test the capacitance parameter Ciss;

步骤8:测试结果送仪器显示或者根据客户需要通过接口发送到上位机;Step 8: Send the test results to the instrument for display or send them to the host computer through the interface according to customer needs;

重复上述步骤1到步骤8直到完成其他设定通道被测件参数的测试。Repeat the above steps 1 to 8 until the other tests for setting the channel DUT parameters are completed.

最后应说明的是:以上实施例,仅为本实用新型的具体实施方式,用以说明本实用新型的技术方案,而非对其限制,本实用新型的保护范围并不局限于此,尽管参照前述实施例对本实用新型进行了详细的说明,本领域的普通技术人员应当理解:任何熟悉本技术领域的技术人员在本实用新型揭露的技术范围内,其依然可以对前述实施例所记载的技术方案进行修改或可轻易想到变化,或者对其中部分技术特征进行等同替换;而这些修改、变化或者替换,并不使相应技术方案的本质脱离本实用新型实施例技术方案的精神和范围,都应涵盖在本实用新型的保护范围之内。因此,本实用新型的保护范围应以权利要求的保护范围为准。Finally, it should be noted that the above examples are only specific implementations of the utility model, used to illustrate the technical solutions of the utility model, rather than limiting it, and the scope of protection of the utility model is not limited thereto, although referring to The aforementioned embodiments have described the utility model in detail, and those of ordinary skill in the art should understand that: any person familiar with the technical field can still use the technology described in the aforementioned embodiments within the technical scope disclosed in the utility model Modifications or changes can be easily imagined in the scheme, or equivalent replacement of some of the technical features; and these modifications, changes or replacements do not make the essence of the corresponding technical solution deviate from the spirit and scope of the technical solution of the embodiment of the utility model. Covered within the protection scope of the present utility model. Therefore, the protection scope of the present utility model should be based on the protection scope of the claims.

Claims (6)

1. A resistance-capacitance integrated single-machine tester for a power semiconductor device is characterized in that: the multi-channel scan test circuit is used for realizing multi-channel scan test of an input resistor, an input capacitor, an output capacitor and a reverse capacitor of a power semiconductor device under different direct-current bias voltage conditions, and comprises a control circuit, an LCR test circuit, a grid bias circuit, a drain bias circuit and a multi-channel isolating switch matrix circuit;
the control circuit is respectively connected with the LCR test circuit, the grid bias circuit, the drain bias circuit and the multichannel isolating switch matrix circuit, and the multichannel isolating switch matrix circuit is respectively connected with the LCR test circuit, the grid bias circuit, the drain bias circuit and the tested power device.
2. The resistance-capacitance integrated single-machine tester for the power semiconductor device according to claim 1, characterized in that: the LCR test circuit is used for realizing parameter test of the input resistor, the input capacitor, the output capacitor and the reverse capacitor of the power semiconductor device under the set test level, test frequency and bias voltage.
3. The resistance-capacitance integrated single-machine tester for the power semiconductor device according to claim 1, characterized in that: the grid bias circuit is used for providing a group of positive and negative direct current power supplies with adjustable wide range, and the positive and negative direct current power supplies are applied between the grid and the source of the power semiconductor device to realize on-off control of the semiconductor power device.
4. The resistance-capacitance integrated single-machine tester for the power semiconductor device according to claim 1, characterized in that: the drain direct-current voltage bias circuit is used for providing a group of wide-range adjustable direct-current power supplies, is applied between the drain and the source of the power semiconductor device and is used as bias voltage between the drain and the source of the power device.
5. The resistance-capacitance integrated single-machine tester for the power semiconductor device according to claim 1, characterized in that: the multi-channel isolating switch matrix circuit realizes the circuit switching of different resistance and capacitance parameters of the power semiconductor devices through the relay matrix switching, and simultaneously realizes the multi-channel scanning test of a plurality of semiconductor power devices through the relay matrix.
6. The resistance-capacitance integrated single-machine tester for the power semiconductor device according to claim 1, characterized in that: the control circuit realizes the setting of LCR test circuit parameters, the control of the grid bias circuit and the drain bias circuit, the switching of the channels and the parameters of the multichannel isolating switch matrix circuit and completes the test of the parameters of the power semiconductor device.
CN202222929579.2U 2023-01-30 2023-01-30 Power semiconductor device resistance and capacitance integrated stand-alone tester Ceased CN218630071U (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117805593A (en) * 2024-01-08 2024-04-02 永耀实业(深圳)有限公司 Integrated circuit scan test method and system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117805593A (en) * 2024-01-08 2024-04-02 永耀实业(深圳)有限公司 Integrated circuit scan test method and system

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