CN218630071U - Resistance-capacitance integrated single-machine tester for power semiconductor device - Google Patents
Resistance-capacitance integrated single-machine tester for power semiconductor device Download PDFInfo
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- CN218630071U CN218630071U CN202222929579.2U CN202222929579U CN218630071U CN 218630071 U CN218630071 U CN 218630071U CN 202222929579 U CN202222929579 U CN 202222929579U CN 218630071 U CN218630071 U CN 218630071U
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Abstract
The utility model relates to a power semiconductor device resistance-capacitance integration unit tester for realize power semiconductor device's input resistance, input capacitance, output capacitance, reverse capacitance multichannel scan test under different direct current bias voltage conditions, including control circuit, LCR test circuit, grid bias voltage circuit, drain electrode bias voltage circuit and multichannel isolator matrix circuit. The resistance-capacitance integrated single tester for the power semiconductor device integrates the control circuit, the LCR test circuit, the grid bias circuit, the drain bias circuit and the multi-channel isolating switch matrix circuit into a single tester, is simple to operate and convenient to maintain, has lower manufacturing cost, and greatly improves the test precision and the test efficiency.
Description
Technical Field
The utility model discloses mainly be applied to power semiconductor device's (for example MOSFET, IGBT etc.) input resistance Rg, input capacitance Ciss, output capacitance Coss, reverse capacitance Crss multichannel scan test under DC bias voltage, especially relate to a power semiconductor device resistance-capacitance integration unit tester.
Background
With the rapid development of new energy automobiles and photovoltaic power generation and energy storage industries in China, power semiconductor devices (MOSFET, IGBT and the like) are more and more widely applied, the demand is more and more high, and the performance is more and more high. Miniaturization and high power density of power semiconductor devices are the main direction of development, requiring power semiconductor devices to operate at higher frequencies. The resistance-capacitance parameters of the power semiconductor device affect the frequency characteristics of the product, and therefore, the power semiconductor device is increasingly emphasized. Taking MOSFET as an example, the input resistor Rg, the input capacitor Ciss, the output capacitor Coss, and the reverse capacitor Crss directly affect the switching characteristics of the power semiconductor device.
At present, resistance and capacitance test equipment in the market is subjected to system integration by an independent function single machine through upper computer software. The single function unit mainly comprises: LCR tester, grid bias power supply, drain bias power supply, isolating switch matrix, industrial computer, etc. The disadvantages of the system integration scheme are: the method has the advantages of poor precision, low efficiency, high cost, large volume, complex operation and difficult maintenance, and cannot meet the requirement of customers on the accurate measurement of the resistance and capacitance parameters of the power device.
SUMMERY OF THE UTILITY MODEL
In order to solve the problem, the utility model discloses a power semiconductor device resistance-capacitance integration unit tester has realized power semiconductor input resistance Rg, input capacitance Ciss, output capacitance Coss, reverse capacitance Crss multichannel scan test under the bias voltage condition.
The utility model provides a resistance-capacitance integrated single-machine tester for power semiconductor devices, which is used for realizing multi-channel scanning test of input resistance, input capacitance, output capacitance and reverse capacitance of the power semiconductor devices under different DC bias voltage conditions, and comprises a control circuit, an LCR test circuit, a grid bias circuit, a drain bias circuit and a multi-channel isolating switch matrix circuit;
the control circuit is respectively connected with the LCR test circuit, the grid bias circuit, the drain bias circuit and the multichannel isolating switch matrix circuit, and the multichannel isolating switch matrix circuit is respectively connected with the LCR test circuit, the grid bias circuit, the drain bias circuit and the power piece to be tested.
The LCR test circuit is used for realizing parameter test of the input resistance, the input capacitance, the output capacitance and the reverse capacitance of the power semiconductor device under the set test level, test frequency and bias voltage.
The grid bias circuit is used for providing a group of positive and negative direct current power supplies with adjustable wide range to adapt to different types of power devices, and the positive and negative direct current power supplies are applied between the grid and the source of the power semiconductor device to realize on-off control of the semiconductor power device.
The drain direct-current voltage bias circuit is used for providing a group of wide-range adjustable direct-current power supplies, is applied between the drain and the source of the power semiconductor device and is used as bias voltage between the drain and the source of the power device.
The multi-channel isolating switch matrix circuit realizes circuit switching of different resistance and capacitance parameters of the power semiconductor devices through relay matrix switching, and simultaneously realizes multi-channel scanning test of a plurality of semiconductor power devices through the relay matrix.
The control circuit realizes the setting of LCR test circuit parameters, the control of the grid bias circuit and the drain bias circuit, the switching of channels and parameters of the multichannel isolating switch matrix circuit and the test of the parameters of the power semiconductor device.
The utility model has the advantages that: the resistance-capacitance integrated single tester for the power semiconductor device integrates the control circuit, the LCR test circuit, the grid bias circuit, the drain bias circuit and the multi-channel isolating switch matrix circuit into a single tester, is simple to operate and convenient to maintain, has lower manufacturing cost, and greatly improves the test precision and the test efficiency.
Drawings
Fig. 1 is a system block diagram of the resistance-capacitance integrated single-machine tester for power semiconductor devices of the present invention;
fig. 2 is a schematic circuit diagram of the resistance-capacitance integrated single tester for power semiconductor devices of the present invention.
Detailed Description
The following description of the preferred embodiments of the present invention will be provided with reference to the accompanying drawings, so that the advantages and features of the present invention can be easily understood by those skilled in the art, and the scope of the present invention can be clearly and clearly defined.
As shown in fig. 1, the resistance-capacitance integrated single tester for the power semiconductor device includes a control circuit, an LCR test circuit, a gate bias circuit, a drain bias circuit, and a multi-channel isolation switch matrix circuit, where the control circuit is connected to the LCR test circuit, the gate bias circuit, the drain bias circuit, and the multi-channel isolation switch matrix circuit is connected to the LCR test circuit, the gate bias circuit, the drain bias circuit, and the power device to be tested.
The utility model discloses can realize MOSFET, IGBT module multichannel scan test, contain the single channel test and use. The present invention is explained by taking MOSFET as an example, and is also applicable to IGBT and power transistor, without limiting the application scope of the present invention.
The control circuit is composed of an MCU, an FPGA and a CPLD and is used for controlling each module and carrying out data calculation and analysis. The control circuit is connected with an LCR test circuit, a grid bias circuit, a drain bias circuit and a multi-channel isolating switch matrix circuit.
As shown in FIG. 2, the LCR test circuit is used for signal source generation, voltage signal sampling, and impedance calculation for the control circuit. The LCR test circuit consists of an alternating current signal source Vs, a current limiting resistor R4, a balanced operational amplifier U1, a variable resistor R3, a voltage sampling circuit Vu and a voltage sampling circuit Vi. The ac signal source Vs generates a sinusoidal ac signal whose amplitude and frequency are determined by the panel settings. The alternating current signal source Vs is connected with the current limiting resistor R4. The current limiting resistor R4 limits the upper limit of the current output by the signal source, and prevents an external short circuit from burning out a signal source circuit or a tested piece. One end of the current limiting resistor R4 is connected with an alternating current signal source Vs, and the other end is connected with a relay matrix (such as S14 of the channel 1). The pin 2 of the balanced operational amplifier U1 is connected with a relay matrix (such as S11 of a channel 1) and also connected with a variable resistor R3; the 3 feet of the balance operational amplifier U1 are connected with the ground; and 6 pins of the balance operational amplifier U1 and the other end of the variable resistor R3. According to the operation principle of the operational amplifier, the current flowing through the tested piece flows through the variable resistor R3. The variable resistor R3 can adjust the size of the resistor according to different flowing currents, so that the voltages at two ends of the variable resistor R3 are in a certain range, and the measurement precision is improved. Both ends of the voltage sampling circuit Vu are connected with the relay matrix (as shown in a channel 1, one end is connected with S12, and the other end is connected with S13) and used for sampling voltages at both ends of the tested piece and sending the voltages to the control circuit for processing. Two ends of a voltage sampling circuit Vi are respectively connected with two ends of the variable resistor R3 and used for sampling voltages at two ends of the variable resistor R3 and sending the voltages to the control circuit for processing.
The grid bias circuit is used for providing bias voltage for the grid of the power semiconductor device so as to enable the power semiconductor to be in conduction states of different degrees. As shown in fig. 2, the gate bias circuit is connected to a signal source. The gate bias circuit is a dc voltage source.
The drain bias circuit is used for providing bias voltage for the drain of the power semiconductor. As shown in fig. 2, the drain bias circuit is composed of a high voltage dc power supply circuit and a current limiting resistor R1. The high-voltage direct-current power circuit is connected with one end of a current-limiting resistor R1. The high voltage power supply circuit generates a direct current voltage. The other end of the current limiting resistor R1 is connected with a relay matrix (such as S18 of a channel 1) and used for limiting the maximum output current of the high-voltage direct-current power supply and protecting instruments.
The multi-channel isolating switch matrix circuit is used for signal switching in different channels and different parameter tests. Take Ciss for channel 1 as an example: s18, one end of the S is connected with the current-limiting resistor R1, and the other end of the S is connected with the test point D and used for controlling the access of direct-current voltage; one end of the S14 is connected with the current limiting resistor R4, the other end of the S11 is connected with the test point G, one end of the S11 is connected with the pin 2 of the balanced operational amplifier U1, and the other end of the S16 is connected with the pin 2 for controlling whether the alternating current signal source is connected to the channel 1 or not; one end of S13 is connected with the voltage sampling circuit Vu, the other end is connected with the test point G, one end of S12 is connected with the voltage sampling circuit Vu, the other end is connected with the pin 2 of S15, and S12 and S13 are used for controlling whether the voltage sampling circuit Vu is connected to the channel 1 or not; s15 and S16 are single-pole double-throw relays, and the pins 2 are connected as described above, the pin 1 of the S15 is connected with the test point S, the pin 3 is connected with the blocking capacitor C13, the pin 1 of the S16 is connected with the test point S, the pin 3 is connected with the blocking capacitor C12, and the S15 and S16 are used for controlling whether the test point D or S is connected into the LCR test circuit; one ends of the blocking capacitors C12 and C13 are connected as described above, and the other ends are connected to the test point D, so as to prevent the drain bias voltage from being applied to the LCR test circuit to influence the test of the LCR test circuit; one end of S17 is connected with the test point D, the other end is connected with a short-circuit capacitor S17, the other end of the short-circuit capacitor S17 is connected with the test point S, and the short-circuit capacitor enables the DS to be in short circuit.
For example, as shown in fig. 2, the test is performed for 1 channel, the test parameter is Ciss, the test frequency is 1MHz, the test level is 100mV, the drain bias voltage Vds is 1500V, and the gate bias voltage is 0V;
the test procedure was as follows:
step 1: switches S11, S12, S13, S14 and S18 are switched on, and the channel 1 is connected;
step 2: connecting the interfaces 1 and 2 of the S15, connecting the interfaces 1 and 2 of the S16, connecting the S17, and preparing for testing the CISS parameters of the DUT1 to be tested;
and 3, step 3: controlling the test frequency of the alternating current signal source to be 1MHz;
and 4, step 4: controlling the test level of an alternating current signal source to be 100mV;
and 5: controlling a gate bias power supply output 0V, applied between the gate and the source of the DUT 1;
step 6: controlling a drain bias power supply output 1500V to be applied between the drain and source of the DUT 1;
and 7: after the bias voltage is stabilized, controlling LCR to test the capacitance parameter Ciss;
and 8: the test result is sent to an instrument for display or is sent to an upper computer through an interface according to the requirement of a client;
and repeating the steps 1 to 8 until the test of the parameters of the tested piece of other set channels is completed.
Finally, it should be noted that: the above embodiments are only specific embodiments of the present invention, and are not intended to limit the technical solution of the present invention, and the protection scope of the present invention is not limited thereto, although the present invention is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: those skilled in the art can still make modifications or changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some technical features, within the technical scope of the present disclosure; such modifications, changes or substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (6)
1. A resistance-capacitance integrated single-machine tester for a power semiconductor device is characterized in that: the multi-channel scan test circuit is used for realizing multi-channel scan test of an input resistor, an input capacitor, an output capacitor and a reverse capacitor of a power semiconductor device under different direct-current bias voltage conditions, and comprises a control circuit, an LCR test circuit, a grid bias circuit, a drain bias circuit and a multi-channel isolating switch matrix circuit;
the control circuit is respectively connected with the LCR test circuit, the grid bias circuit, the drain bias circuit and the multichannel isolating switch matrix circuit, and the multichannel isolating switch matrix circuit is respectively connected with the LCR test circuit, the grid bias circuit, the drain bias circuit and the tested power device.
2. The resistance-capacitance integrated single-machine tester for the power semiconductor device according to claim 1, characterized in that: the LCR test circuit is used for realizing parameter test of the input resistor, the input capacitor, the output capacitor and the reverse capacitor of the power semiconductor device under the set test level, test frequency and bias voltage.
3. The resistance-capacitance integrated single-machine tester for the power semiconductor device according to claim 1, characterized in that: the grid bias circuit is used for providing a group of positive and negative direct current power supplies with adjustable wide range, and the positive and negative direct current power supplies are applied between the grid and the source of the power semiconductor device to realize on-off control of the semiconductor power device.
4. The resistance-capacitance integrated single-machine tester for the power semiconductor device according to claim 1, characterized in that: the drain direct-current voltage bias circuit is used for providing a group of wide-range adjustable direct-current power supplies, is applied between the drain and the source of the power semiconductor device and is used as bias voltage between the drain and the source of the power device.
5. The resistance-capacitance integrated single-machine tester for the power semiconductor device according to claim 1, characterized in that: the multi-channel isolating switch matrix circuit realizes the circuit switching of different resistance and capacitance parameters of the power semiconductor devices through the relay matrix switching, and simultaneously realizes the multi-channel scanning test of a plurality of semiconductor power devices through the relay matrix.
6. The resistance-capacitance integrated single-machine tester for the power semiconductor device according to claim 1, characterized in that: the control circuit realizes the setting of LCR test circuit parameters, the control of the grid bias circuit and the drain bias circuit, the switching of the channels and the parameters of the multichannel isolating switch matrix circuit and completes the test of the parameters of the power semiconductor device.
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| CN202222929579.2U CN218630071U (en) | 2023-01-30 | 2023-01-30 | Resistance-capacitance integrated single-machine tester for power semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117805593A (en) * | 2024-01-08 | 2024-04-02 | 永耀实业(深圳)有限公司 | Method and system for scanning and testing integrated circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117805593A (en) * | 2024-01-08 | 2024-04-02 | 永耀实业(深圳)有限公司 | Method and system for scanning and testing integrated circuit |
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