CN218570197U - Broadband high-frequency low-frequency-multiplication-loss high-harmonic-suppression frequency doubler chip - Google Patents
Broadband high-frequency low-frequency-multiplication-loss high-harmonic-suppression frequency doubler chip Download PDFInfo
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Abstract
The utility model provides a low doubling of frequency loss of broadband high frequency, high harmonic suppression frequency doubler chip belongs to the radio frequency microwave integrated circuit technical field of microelectronics and solid electronics, including frequency doubling module, first power filter circuit, second power filter circuit and output matching module, frequency doubling module's input constitutes the input port and the single-ended signal of receiving of chip, and frequency doubling module's output is connected with output matching network's input, and output matching network's output constitutes the output port of chip, and the output only contains the single-ended signal of even harmonic. The utility model provides a frequency multiplier chip has realized higher harmonic suppression and lower doubling of frequency loss in less chip size to have good linearity and dynamic range.
Description
Technical Field
The utility model belongs to the radio frequency microwave integrated circuit technology of microelectronics and solid electronics, especially a broadband high frequency hangs down doubling of frequency loss, high harmonic suppression frequency doubler chip.
Background
In recent years, millimeter wave systems have wide application in high-end equipment such as high-speed communication and high-resolution imaging radar, and for such systems, the key core is to design a local oscillation signal source with high power, broadband and low phase noise. Because the millimeter wave oscillator is sensitive to process fluctuation and has a narrow tuning range, a frequency multiplier with a broadband and low frequency multiplication loss is usually adopted as a key core circuit of a signal source in the design of a millimeter wave signal source.
For a frequency doubling circuit, frequency doubling can be realized by any nonlinear semiconductor device, such as common nonlinear variable-resistance diodes, step diodes, field-effect transistors and the like, which can be used for frequency doubling, and with the continuous efforts of researchers, millimeter-wave frequency doubler chips are greatly improved in frequency doubling efficiency and frequency suppression, basic circuit architectures and implementation modes are relatively mature, but the following problems still exist at present:
1. for nonlinear resistance type frequency multiplication, the required input power is higher, and the frequency multiplication loss is large;
2. higher harmonic suppression is difficult to realize in the millimeter wave frequency band;
3. the adjacent harmonic waves of the broadband frequency multiplier chip are overlapped with the working frequency band, and the suppression degree is poor.
Based on the problems, on the premise of not influencing the harmonic suppression degree, the optimal input power of the frequency multiplier is reduced by changing the pressure difference between two sides of the transistor, and the frequency multiplication loss of the circuit is effectively reduced.
SUMMERY OF THE UTILITY MODEL
In view of this, the embodiment of the present invention provides a wideband high-frequency low-frequency-multiplication loss and high-harmonic suppression frequency doubler chip to solve or alleviate the technical problems existing in the prior art, and at least provide a useful choice.
Realize the utility model discloses the technical solution of purpose does: a broadband high-frequency low-frequency multiplication loss and high-harmonic suppression frequency doubler chip mainly comprises a frequency doubling module, a first power supply filter circuit, a second power supply filter circuit and an output matching module; the input end of the frequency doubling module forms an input port of the chip and is used for receiving a single-ended signal; the output end of the frequency doubling module is connected with the input end of the output matching network and is used for outputting a group of odd harmonics with opposite phases and equal amplitudes and a group of even harmonics with the same phases and equal amplitudes; the output end of the output matching network forms an output port of the chip and is used for outputting a single-ended signal only containing even harmonics.
The input end of the first power supply filter circuit is externally connected with a preset power supply positive end, the output end of the first power supply filter circuit is connected with an external positive end of the frequency doubling module, the output end of the second power supply filter circuit is externally connected with a preset power supply negative end, the input end of the second power supply filter circuit is connected with an external negative end of the frequency doubling module, and the first power supply filter circuit and the second power supply filter circuit are used for restraining fundamental wave power of a chip output port and outputting corresponding single-ended signals from the chip output port.
Specifically, the frequency doubling module comprises a microstrip transmission line TL1, a base-emitter short-circuit transistor D2, a transmission line balun Tb1, a balun transmission line Tb2 and a balun transmission line Tb3; one end of a microstrip transmission line TL1 forms an input end of the frequency doubling module, the other end of the microstrip transmission line TL1 is connected with a collector of a base-emitter short-circuit transistor D1 and an emitter of a base-emitter short-circuit transistor D2, the emitter of the base-emitter short-circuit transistor D1 is connected with one end of the microstrip transmission line TL2, the other end of the microstrip transmission line TL2, one end of a balun transmission line Tb3 and one end of the microstrip transmission line TL2 are connected, and the other end of the balun transmission line Tb3 forms an external positive end of the frequency doubling module; the collector of the base-emitter short-circuit transistor D2 is connected with one end of the balun transmission line Tb1 through a microstrip transmission line TL3, and the other end of the balun transmission line Tb1 is connected with an external negative end of the frequency doubling module; the other end of the microstrip transmission line TL2 constitutes the output of the frequency doubling module.
The first power supply filter circuit comprises a resistor R1, a resistor R2, a resistor R3, a resistor R4 and a capacitor C1; one end of the resistor R1 forms an input end of the first power supply filter circuit, the other end of the resistor R1, one end of the resistor R2 and one end of the capacitor C1 are connected to form an output end of the first power supply filter circuit, the other end of the capacitor C1 is grounded, and the other end of the resistor R2 is grounded.
The second power supply filter circuit comprises a resistor R3, a resistor R4, a capacitor C2 and a capacitor C3; one end of the resistor R3 forms an output end of the second power supply filter circuit, the other end of the resistor R3 is connected with one end of the resistor R4 and one end of the capacitor C2 to form an input end of the second power supply filter circuit, the other end of the capacitor C2 is grounded, and the other end of the resistor R4 is grounded.
The output matching module comprises a capacitor C3 and a fifth microstrip transmission line TL5; one end of the fifth microstrip transmission line TL5 forms an input end of the output matching network, the other end of the fifth microstrip transmission line TL5 is connected to one end of the capacitor C3, and the other end of the capacitor C3 forms an output end of the output matching module.
Preferably, the transmission line type balun has a Ruthroff structure.
Specifically, the single-ended signal generates a series of reversed-phase odd harmonics and in-phase even harmonics after passing through the diode, then the odd harmonics of the two paths of signals are offset through the balun transmission line, and finally a high-power second-order frequency multiplication signal is output.
Specifically, two power supply voltages of the frequency doubler chip are divided by resistors and then loaded to two sides of a transistor with a short-circuited base electrode and an emitter electrode, and direct current voltage drops on two sides of the transistor are indirectly adjusted by adjusting the power supply voltages, so that the range of an input power window required by a circuit is reduced. Under the condition that the injection power is not changed, along with the improvement of the power supply voltage, the larger the voltage drop of two sides of the transistor with the short-circuited base electrode and emitter electrode is, the smaller the required injection power is, so that the frequency conversion loss under the current power is increased, and the frequency conversion efficiency is lowered. The method can effectively reduce the driving power of the frequency multiplier chip, but the required power supply voltage is increased.
Specifically, the power supply filter circuit can remove ripples in a power supply to a certain extent, prevent the influence caused by power supply noise, and the filter capacitor to the ground is used as an alternating current ground, so that the fundamental wave power of the output port of the frequency multiplier chip can be effectively inhibited, and the fundamental wave inhibition ratio of the frequency multiplier chip is improved.
Has the advantages that: compared with the prior art, the utility model discloses an advantage reaches and is showing the effect:
(1) The circuit structure is simple.
(2) The operating frequency range is wide to can suitably adjust mains voltage and realize lower power injection, compare with the frequency multiplier of the same type, the utility model discloses realized lower frequency multiplication loss and higher fundamental wave and third harmonic suppression in less chip size.
The foregoing summary is provided for the purpose of description only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present invention will be readily apparent by reference to the drawings and following detailed description.
Drawings
In the drawings, like reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily to scale. It is appreciated that these drawings depict only some embodiments in accordance with the disclosure and are not to be considered limiting of its scope.
Fig. 1 is a circuit structure diagram of the present invention.
Fig. 2 is a circuit layout of a wideband high-frequency low-frequency-multiplication loss and high-harmonic suppression frequency doubler chip in the embodiment of the present invention;
fig. 3 is a curve of fundamental wave, second harmonic and third harmonic output power under the power supply voltage ± 1.5V and the input signal power of 15dBm in the embodiment of the present invention;
fig. 4 is an output power curve of the embodiment of the present invention under the power supply voltage ± 1.5V, the input signal power of 11dBm, 13dBm, 15dBm, 17dBm, 19 dBm;
fig. 5 is a fundamental wave output power curve under the power supply voltage ± 1.5V, the input signal power of 11dBm, 13dBm, 15dBm, 17dBm, 19dBm in the embodiment of the present invention;
fig. 6 is a third harmonic output power curve under the power supply voltage ± 1.5V and the input signal power of 11dBm, 13dBm, 15dBm, 17dBm, 19dBm in the embodiment of the present invention;
fig. 7 is an input standing wave curve under the power supply voltage ± 1.5V and the input signal power of 11dBm, 13dBm, 15dBm, 17dBm, 19dBm in the embodiment of the present invention;
FIG. 8 is a graph of output power of an embodiment of the present invention under the conditions that the input signal power is 15dBm and the power supply voltage is + -0.5V, + -1V, + -1.5V, + -2V, + -2.5V;
fig. 9 is a variation curve of the down-conversion loss with the input power under the condition of ± 1.5V of the supply voltage in the embodiment of the present invention.
Wherein, in the figures, the respective reference numerals:
1-chip input port; 2-common terminal of the diode; the output port of the 3-diode D1; 4-the output port of diode D2; 5-one-way signal; 6-chip output port; 7-positive powered port; 8-negative electrically powered port.
Detailed Description
The present invention will be further described with reference to the accompanying drawings and specific embodiments.
In the following, only certain exemplary embodiments are briefly described. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", and the like, indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or component referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore, should not be construed as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically limited otherwise.
In the present invention, unless otherwise explicitly specified or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly, e.g., as being fixedly connected, detachably connected, or integrated; the connection can be mechanical connection, electrical connection or communication; they may be connected directly or indirectly through intervening media, or they may be connected through any combination of two or more components or their mutual relationships. The specific meaning of the above terms in the present invention can be understood according to specific situations by those of ordinary skill in the art.
In the present application, unless expressly stated or limited otherwise, the recitation of a first feature "on" or "under" a second feature may include the recitation of the first and second features being in direct contact, and may also include the recitation of the first and second features not being in direct contact, but being in contact with another feature between them. Also, the first feature being "on," "square," and "over" the second feature includes the first feature being directly above and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly above and obliquely above the second feature, or simply meaning that the first feature is at a lesser level than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the invention. In order to simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present disclosure may repeat reference numerals and/or reference letters in the various examples for purposes of simplicity and clarity and do not in itself dictate a relationship between the various embodiments and/or arrangements discussed. In addition, the present disclosure provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize the application of other processes and/or the use of other materials.
As shown in fig. 1, the embodiment of the utility model provides a broadband high frequency hangs down doubling of frequency loss, high harmonic suppression frequency doubler chip includes:
the frequency multiplier comprises a frequency doubling module, a first power supply filter circuit, a second power supply filter circuit and an output matching module; the input end of the frequency doubling module forms an input port of the chip and is used for receiving a single-ended signal; the output end of the frequency doubling module is connected with the input end of the output matching network and is used for outputting a group of odd harmonics with opposite phases and equal amplitude and a group of even harmonics with the same phases and equal amplitudes; the output end of the output matching network forms an output port of the chip and is used for outputting a single-ended signal only containing even harmonics.
In one embodiment, the input terminal of the first power filter circuit is externally connected with the positive terminal of the preset power supply, the output terminal of the first power filter circuit is connected with the external positive terminal of the frequency doubling module, the output terminal of the second power filter circuit is externally connected with the negative terminal of the preset power supply, the input terminal of the second power filter circuit is connected with the external negative terminal of the frequency doubling module, and the first power filter circuit and the second power filter circuit are used for suppressing the fundamental wave power of the chip output port and outputting a corresponding single-ended signal from the chip output port.
In one embodiment, the single-ended signal generates a series of inverse odd harmonics and in-phase even harmonics after passing through the diode, then the odd harmonics of the two paths of signals are counteracted through the balun transmission line, and finally a high-power second-order frequency-doubled signal is output.
In one embodiment, two power supply voltages of the frequency doubler chip are divided by resistors and then loaded to two sides of a transistor with a base electrode and an emitter electrode in short circuit, and the direct current voltage drop on the two sides of the transistor is indirectly adjusted by adjusting the power supply voltages, so that the input power window range required by the circuit is reduced. Under the condition that the injection power is not changed, along with the improvement of the power supply voltage, the larger the voltage drop of two sides of the transistor with the short-circuited base electrode and emitter electrode is, the smaller the required injection power is, so that the frequency conversion loss under the current power is increased, and the frequency conversion efficiency is lowered. The method can effectively reduce the driving power of the frequency multiplier chip, but the required power supply voltage is increased.
In a specific embodiment, the frequency doubling module includes a microstrip transmission line TL1, a base-emitter short-circuit transistor D2, a transmission line balun Tb1, a balun transmission line Tb2, and a balun transmission line Tb3; one end of a microstrip transmission line TL1 forms an input end of the frequency doubling module, the other end of the microstrip transmission line TL1 is connected with a collector of a base-emitter short-circuit transistor D1 and an emitter of a base-emitter short-circuit transistor D2, the emitter of the base-emitter short-circuit transistor D1 is connected with one end of the microstrip transmission line TL2, the other end of the microstrip transmission line TL2, one end of a balun transmission line Tb3 and one end of the microstrip transmission line TL2 are connected, and the other end of the balun transmission line Tb3 forms an external positive end of the frequency doubling module; the collector of the base-emitter short-circuit transistor D2 is connected with one end of the balun transmission line Tb1 through a microstrip transmission line TL3, and the other end of the balun transmission line Tb1 is connected with an external negative end of the frequency doubling module; the other end of the microstrip transmission line TL2 constitutes the output of the frequency doubling module.
In a specific embodiment, the first power filter circuit includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, and a capacitor C1; one end of the resistor R1 forms an input end of the first power supply filter circuit, the other end of the resistor R1, one end of the resistor R2 and one end of the capacitor C1 are connected to form an output end of the first power supply filter circuit, the other end of the capacitor C1 is grounded, and the other end of the resistor R2 is grounded.
In a specific embodiment, the second power supply filter circuit comprises a resistor R3, a resistor R4, a capacitor C2 and a capacitor C3; one end of the resistor R3 forms an output end of the second power supply filter circuit, the other end of the resistor R3 is connected with one end of the resistor R4 and one end of the capacitor C2 to form an input end of the second power supply filter circuit, the other end of the capacitor C2 is grounded, and the other end of the resistor R4 is grounded.
In a specific embodiment, the output matching module includes a capacitor C3, a fifth microstrip transmission line TL5; one end of the fifth microstrip transmission line TL5 forms an input end of the output matching network, the other end of the fifth microstrip transmission line TL5 is connected to one end of the capacitor C3, and the other end of the capacitor C3 forms an output end of the output matching module.
In a preferred embodiment, the balun transmission line is a Ruthroff structure.
Example 1
The embodiment is a frequency doubler chip with 40 to 80GHz broadband, high frequency, low frequency multiplication loss and high harmonic suppression. The circuit structure diagram is shown in fig. 1, and the whole circuit mainly comprises a frequency doubling module, a first power supply filter circuit, a second power supply filter circuit and an output matching module.
In order to maximize the nonlinearity of the circuit and improve the output power, a transistor in a base-emitter short circuit form is used as a nonlinear core device. In addition, because the frequency doubler chip operating band can be from Ka wave band to W wave band, in order to avoid the influence that the high-frequency parasitism of transistor brought, the utility model discloses a two small-size diodes have improved the operating bandwidth and the odd harmonic suppression of chip effectively through the form of single balanced structure; the balun adopts a broadside coupled Ruthroff type structure, and has the advantages of simple structure, strong coupling degree, small metal parasitic capacitance and good broadband characteristic; the filter capacitor is used as an alternating current ground, and can effectively suppress fundamental wave power at an output port of the frequency multiplier chip, so that the fundamental wave suppression degree of the chip is improved.
The embodiment of the utility model provides a low doubling of frequency loss of broadband high frequency, high harmonic suppression frequency doubler chip circuit territory 2 are shown, and the circuit territory is mainly by the public end 2 of chip input port 1, diode D1's output port 3, diode D2's output port 4, one way signal 5, chip output port 6, positive electricity add electric port 7, the negative electricity adds electric port 8 and constitutes. A low-frequency input signal enters from an input port 1, passes through microstrip lines of an input matching network and then respectively enters a common end 2 of two diodes, two paths of odd harmonic opposite-phase and even harmonic in-phase multi-tone signals can be generated at ports 3 and 4 due to the nonlinear action of the diodes, then the two paths of signals are synthesized into a single-path signal 5 by a balun transmission line, odd harmonic cancellation and even harmonic power are mutually superposed, finally the single-path signal sequentially enters an output matching microstrip line and a capacitor, and a secondary signal is output by a port 6. Two power-on ports 7 and 8 exist in the layout, and +1.5V voltage and-1.5V voltage are applied during testing respectively.
Fig. 3 to 8 are actual measurement curves of the wideband high-frequency low-frequency-multiplication loss and high-harmonic suppression frequency doubler chip of the present invention, respectively, and fig. 3 is a fundamental wave, second harmonic and third harmonic output power curve under the condition of power supply voltage ± 1.5V and input signal power of 15 dBm; FIG. 4 is an output power curve of a supply voltage of + -1.5V, and input signal powers of 11dBm, 13dBm, 15dBm, 17dBm, and 19 dBm; fig. 5 is a fundamental wave output power curve under the power supply voltage ± 1.5V, the input signal power of 11dBm, 13dBm, 15dBm, 17dBm, 19dBm in the embodiment of the present invention; fig. 6 is a third harmonic output power curve under the power supply voltage ± 1.5V and the input signal power of 11dBm, 13dBm, 15dBm, 17dBm, 19dBm in the embodiment of the present invention; FIG. 7 is a graph of input standing waves at a supply voltage of + -1.5V and input signal powers of 11dBm, 13dBm, 15dBm, 17dBm, and 19 dBm; FIG. 8 is a graph of output power at 15dBm input signal power and + -0.5V, + -1V, + -1.5V, + -2V, + -2.5V supply voltage; fig. 9 is a frequency multiplication loss curve of the power supply voltage ± 1.5V and different input signal powers. It can be seen from the actual measurement curve that under the voltage of ± 1.5V and the input signal power of 15dBm, the frequency range can cover 40 to 80ghz, the flatness in the band is better, the frequency multiplication loss is less than 10dB, the harmonic suppression is all greater than 20dBc, the input standing wave is less than 2, the chip area is 0.77mm × 0.88mm, the input power has a lower window range, and the lower frequency multiplication loss and the higher harmonic suppression degree are realized compared with the domestic similar design.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of various changes or substitutions within the technical scope of the present invention, and these should be covered by the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (6)
1. A broadband high-frequency low-frequency-multiplication-loss high-harmonic-suppression frequency doubler chip is characterized by comprising a frequency doubling module, a first power supply filter circuit, a second power supply filter circuit and an output matching module; the input end of the frequency doubling module forms an input port of the chip and is used for receiving a single-ended signal; the output end of the frequency doubling module is connected with the input end of the output matching network and is used for outputting a group of odd harmonics with opposite phases and equal amplitude and a group of even harmonics with the same phases and equal amplitudes; the output end of the output matching network forms an output port of the chip and is used for outputting a single-ended signal only containing even harmonic waves;
the input end of the first power supply filter circuit is externally connected with a preset power supply positive end, the output end of the first power supply filter circuit is connected with an external positive end of the frequency doubling module, the output end of the second power supply filter circuit is externally connected with a preset power supply negative end, the input end of the second power supply filter circuit is connected with an external negative end of the frequency doubling module, and the first power supply filter circuit and the second power supply filter circuit are used for restraining fundamental wave power of a chip output port and outputting corresponding single-ended signals from the chip output port.
2. The wideband high-frequency low-frequency-multiplication-loss high-harmonic-rejection frequency doubler chip according to claim 1, wherein: the frequency doubling module comprises a microstrip transmission line TL1, a base-emitter short-circuit transistor D2, a transmission line balun Tb1, a balun transmission line Tb2 and a balun transmission line Tb3; one end of a microstrip transmission line TL1 forms an input end of the frequency doubling module, the other end of the microstrip transmission line TL1 is connected with a collector of a base-emitter short-circuit transistor D1 and an emitter of a base-emitter short-circuit transistor D2, the emitter of the base-emitter short-circuit transistor D1 is connected with one end of the microstrip transmission line TL2, the other end of the microstrip transmission line TL2, one end of a balun transmission line Tb3 and one end of the microstrip transmission line TL2 are connected, and the other end of the balun transmission line Tb3 forms an external positive end of the frequency doubling module; the collector of the base-emitter short-circuit transistor D2 is connected with one end of the balun transmission line Tb1 through a microstrip transmission line TL3, and the other end of the balun transmission line Tb1 is connected with an external negative end of the frequency doubling module; the other end of the microstrip transmission line TL2 constitutes the output of the frequency doubling module.
3. The wideband high-frequency low-doubling-loss high-harmonic-rejection frequency doubler chip according to claim 1, wherein: the first power supply filter circuit comprises a resistor R1, a resistor R2, a resistor R3, a resistor R4 and a capacitor C1; one end of the resistor R1 forms an input end of the first power supply filter circuit, the other end of the resistor R1, one end of the resistor R2 and one end of the capacitor C1 are connected to form an output end of the first power supply filter circuit, the other end of the capacitor C1 is grounded, and the other end of the resistor R2 is grounded.
4. The wideband high-frequency low-doubling-loss high-harmonic-rejection frequency doubler chip according to claim 1, wherein: the second power supply filter circuit comprises a resistor R3, a resistor R4, a capacitor C2 and a capacitor C3; one end of the resistor R3 forms an output end of the second power supply filter circuit, the other end of the resistor R3 is connected with one end of the resistor R4 and one end of the capacitor C2 to form an input end of the second power supply filter circuit, the other end of the capacitor C2 is grounded, and the other end of the resistor R4 is grounded.
5. The wideband high-frequency low-frequency-multiplication-loss high-harmonic-rejection frequency doubler chip according to claim 1, wherein: the output matching module comprises a capacitor C3 and a fifth microstrip transmission line TL5; one end of the fifth microstrip transmission line TL5 constitutes an input end of the output matching network, the other end of the fifth microstrip transmission line TL5 is connected to one end of the capacitor C3, and the other end of the capacitor C3 constitutes an output end of the output matching module.
6. The wideband high-frequency low-frequency-multiplication-loss high-harmonic-rejection frequency doubler chip according to claim 2, wherein the balun transmission line has a Ruthroff structure.
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