CN218498056U - Integrated circuit package - Google Patents
Integrated circuit package Download PDFInfo
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- CN218498056U CN218498056U CN202222261598.2U CN202222261598U CN218498056U CN 218498056 U CN218498056 U CN 218498056U CN 202222261598 U CN202222261598 U CN 202222261598U CN 218498056 U CN218498056 U CN 218498056U
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Abstract
Embodiments of the present disclosure relate to integrated circuit packages. An integrated circuit package comprising: a base substrate electronic chip mounted on a face of the base substrate; a coating encapsulating the electronic chip, the coating having a bottom surface mounted on the face of the base substrate, and the coating also having a contoured top surface; wherein the portion of the contoured top surface is configured to locally reduce the volume of the area of the coating; and a heat sink mounted on the profiled top surface of the coating using a mounting layer.
Description
Technical Field
Embodiments and examples relate to the field of microelectronics, particularly to the field of integrated circuit packages, and more particularly to heat dissipation of integrated circuit packages.
Background
Conventionally, one type of integrated circuit package comprises at least one electronic integrated circuit chip disposed on one face of a base substrate and protected by a coating, usually a resin, which is molded around the chip and rigidly connected to the base substrate. The other side of the base substrate may include electrical connection structures, such as balls, for mounting on a Printed Circuit Board (PCB).
Such a coating resin not only protects the chip but also contributes to the robustness of the package.
There is a need in the art to enhance the heat dissipation of such packages.
SUMMERY OF THE UTILITY MODEL
According to the utility model discloses, can overcome technical problem: the resin is a weak link in the heat dissipation capability of the package, especially when the heat released during operation of the chip is dissipated to the top of the package (i.e., opposite the substrate).
It is therefore proposed to reduce the thickness of the coating resin locally in suitable places to reduce the thermal chain of the encapsulation, contributing to the following advantages: the maximum junction temperature that does not degrade the integrated circuit is maintained while the electronic chip is in operation, while the package is robust.
According to one aspect, an integrated circuit package is presented, comprising a base substrate, at least one electronic chip mounted on a face of the base substrate and configured to have, in operation, a hot spot emitting heat in a thermal volume (e.g., a volume separated by a truncated type surface).
The package also includes a coating covering at least the at least one electronic chip and optionally electrical connection wires ("wire bonds") soldered between the chip and the base substrate.
The coating has a bottom surface mounted on the face of the base substrate and a profiled top surface having a profiled portion thereof configured to reduce the volume of the coated region.
The portion of the contour is at least partially located in the thermal volume.
The package further comprises a heat sink, typically of metal, mounted on the profiled top surface of the coating by means of a mounting layer, preferably thermally conductive, for example by means of an adhesive layer or an interface material layer, as is well known to the person skilled in the art.
Thus, by reducing the thickness of the coating resin in the thermal volume space, heat dissipation from the package can be enhanced by reducing the amount of resin that is a weak point of the thermal link, while retaining the robustness of the package, since the thickness of the resin is maintained where heat dissipation is low or even negligible.
In one embodiment, a circuit-forming package includes: a base substrate; an electronic chip mounted on a face of the base substrate; a coating encapsulating the electronic chip, the coating having a bottom surface mounted on the face of the base substrate and the coating further having a contoured top surface; wherein a portion of the contoured top surface is configured to locally reduce the volume of a region of the coating; and a heat sink mounted on the profiled top surface of the coating using a mounting layer.
According to one possible alternative embodiment, the mounting layer has a profile that molds (i.e., conforms to) the profiled top surface of the coating, and the heat spreader includes a profiled bottom surface that molds (i.e., conforms to) the profile of the mounting layer and a flat top surface.
According to some embodiments, the mounting layer has a profile molded to the contoured top surface of the coating layer, and wherein the heat spreader has a contoured bottom surface molded to the profile of the mounting layer, and the heat spreader further comprises a flat top surface.
According to another possible alternative embodiment, the mounting layer has a shaped bottom surface and a flat top surface that mold (i.e., conform to) the coating shaped top surface, and the heat spreader has a flat bottom surface front surface and a flat top surface that are mounted on the flat top surface of the mounting layer.
According to some embodiments, the mounting layer has a contoured bottom surface molded to the contoured top surface of the coating layer, and the mounting layer further includes a flat top surface, and wherein the heat spreader has a flat bottom surface and a flat top surface mounted on the flat top surface of the mounting layer.
The size of the thermal volume varies depending on the size of the chip.
One skilled in the art will know how to adjust the profile of the top surface of the coating according to the size of the chip, its operating hot spot, and the heat dissipation enhancement sought.
Thus, according to one embodiment, the contoured portion of the profiled top face for the coating comprises at least one first hollow zone extending in the direction of the base substrate and delimiting at least a first part of the reduced area of the coating, which first part at least partially covers the electronic chip.
It is also possible that the profiled section of the profiled top face for the coating comprises at least a second hollow zone which extends in the direction of the base substrate and delimits at least a second part of the reduced area of the coating, which second part is located laterally with respect to the first part of the reduced area of the coating.
The package may be of the type that uses "wire bonding" techniques. In this case, the at least one chip includes a bottom surface mounted on the base substrate face by a layer of adhesive and a top surface including contact pads electrically connected to the base substrate face by connection lines.
According to some embodiments, an electronic chip comprises: a bottom surface mounted on the face of the base substrate by an adhesive layer; and a top surface comprising contact pads electrically connected to contact pads of the face of the base substrate by connecting lines, and wherein the coating further encapsulates the contact pads and the connecting lines.
The coating then also covers the contact pads and the connection lines.
Alternatively, the package may be of the type using so-called "flip-chip" technology. In this case, the chip comprises a bottom surface provided with electrically conductive connection balls mounted on said surface of the substrate and embedded in an "underfill" layer.
According to some embodiments, the electronic chip comprises a bottom surface provided with electrically conductive connection balls mounted on said face of said substrate.
According to some embodiments, the profiled top surface is defined by: a first hollow region extending in a direction of the base substrate and positioned vertically above the electronic chip; and a second hollow region extending in a direction of the base substrate and laterally away from and surrounding the first hollow region.
According to some embodiments, the first hollow zone has a first depth from an upper surface of the coating and the second hollow zone has a second depth from the upper surface of the coating, and wherein the first depth is greater than the second depth.
According to some embodiments, the first hollow zone has a first depth from an upper surface of the coating and the second hollow zone has a second depth from the upper surface of the coating, and wherein the second depth is greater than the first depth.
According to some embodiments, an integrated circuit package comprises: a base substrate; an electronic chip mounted on a face of the base substrate; a coating encapsulating the electronic chip and mounted to the face of the base substrate, and further having a contoured top surface defined by a plurality of hollow regions that locally reduce the volume of corresponding regions of the coating; a mounting layer filling the plurality of hollow areas and covering the coating to provide a flat top surface; and a heat sink having a flat bottom surface mounted on the flat top surface of the mounting layer.
According to some embodiments, the plurality of hollow regions comprises a first hollow region extending in the direction of the base substrate and providing a first locally reduced volume of the coating layer, the first locally reduced volume extending directly over the electronic chip.
According to some embodiments, the plurality of hollow regions further comprises a second hollow region extending in the direction of the base substrate and providing a second locally reduced volume of the coating, the second locally reduced volume being located laterally with respect to the first locally reduced volume.
According to some embodiments, the second locally reduced volume of coating extends partially over the electronic chip and partially beyond an outer perimeter of the electronic chip.
According to some embodiments, the depth of the first hollow zone is deeper than the depth of the second hollow zone.
According to some embodiments, the second locally reduced volume of coating extends completely laterally beyond an outer perimeter of the electronic chip.
According to some embodiments, the depth of the second hollow zone is deeper than the depth of the first hollow zone.
According to some embodiments, an integrated circuit package comprises: a base substrate; an electronic chip mounted on a face of the base substrate; a coating encapsulating the electronic chip and mounted to the face of the base substrate, and further having a contoured top surface defined by a plurality of hollow regions that locally reduce the volume of corresponding regions of the coating; wherein the plurality of hollow regions comprises: a first hollow region extending in a direction of the base substrate and providing a first locally reduced volume of the coating layer, the first locally reduced volume extending directly over the electronic chip; and a second hollow region extending in the direction of the base substrate and providing a second locally reduced volume of the coating, the second locally reduced volume being located laterally with respect to the first locally reduced volume; and a heat sink mounted on the profiled top surface of the coating using a mounting layer.
Drawings
Further advantages and features of the invention will become apparent upon studying the detailed description of the examples and embodiments (without limiting the description) and the accompanying drawings, in which:
FIG. 1 schematically illustrates a cross-sectional view of an integrated circuit package;
FIG. 2 is a representation of the coating of FIG. 1 in particular;
FIG. 3 schematically illustrates the dimensions of the package of FIG. 1; and
fig. 4-5 illustrate alternative implementations.
Detailed Description
Fig. 1 schematically shows a cross-sectional view of an integrated circuit package BT according to an embodiment. The package BT includes a base substrate 1 and at least one electronic integrated circuit chip 2 mounted on a top mounting face FS of the base substrate 1. The packaged BT may also include several other electronic chips.
However, for the sake of simplicity, in the embodiment described herein, a single chip 2 is shown.
In operation, the electronic chip 2 has a hot spot. These hot spots generate heat in the hot volume space.
The hot spots may be more or less appreciable and/or spaced apart, depending in particular on the size of the chip 2, so that the size of the thermal volume space may vary.
As an example, two thermal volume spaces ESPV1 and ESPV2 are shown. The volume space ESPV1 more specifically represents a larger space than the space ESPV2, corresponding to a larger scale of heat generation. For example, the thermal volumes ESPV1 and ESPV2 may be defined by truncated surfaces TRC1 and TRC2, respectively, which widen from the chip in the direction of heat exhaust. In this case, heat is discharged at the top of the package, opposite the base substrate 1.
In the following, the reference thermal volume space will be the space ESPV1.
The package is of the type that uses "wire bonding" technology in this embodiment. In this case, the electronic chip 2 includes a bottom surface mounted on the face FS of the base substrate 1 through the adhesive layer 3, and also includes a top surface.
The upper surface of the electronic chip 2 includes contact pads PD1 which are electrically connected to contact pads PD2 of the face FS of the base substrate 1 by connection lines WB soldered on these pads.
The integrated circuit package BT further comprises a coating 4. The coating 4 coats (embeds or encapsulates) at least the electronic chip 2 and here also the electrically conductive connection lines WB and the different contact pads PD1, PD2.
The coating 4 may also coat any other electronic chip encapsulating the BT.
The coating 4 may be a resin, for example. The resin has advantageous mechanical properties that enable the encapsulation BT to withstand mechanical stresses liable to be exerted thereon. The use of such a coating 4 contributes in particular to the robustness of the encapsulated BT.
Furthermore, the coating 4 has a bottom surface 40 and a profiled top surface 41. The bottom surface 40 and the profiled top surface 41 thus define the thickness of the coating 4.
The bottom surface 40 of the coating 4 is rigidly connected to the face FS of the base substrate 1.
The packaged BT further includes a heat spreader 5 and a bonding layer 6, such as, but not limited to, a thermally conductive adhesive layer 6.
The heat sink 5 is generally formed of a heat conductive material such as metal. For example, a copper heat sink 5 having a thermal conductivity of 385W/mK may be provided. The heat sink 5 is mounted on the profiled top surface 41 of the coating 4 using a thermally conductive adhesive layer 6.
The adhesive layer 6 thus makes it possible in particular to achieve a heat transfer from the coating 4 to the heat sink 5.
As shown more particularly in fig. 2, which particularly represents the coating 4 of fig. 1, the contoured top surface 41 has a contoured portion 410 thereof configured to locally reduce the volume of the region of the coating 4. In other words, the volume may reduce the thickness of the regions of coating 4 at discrete intervals according to the profile of top surface 41 of coating 4. In particular, the contoured portion 410 is configured to reduce the thickness of the coated region 4.
The contour portion 410 is here at least partially located in the thermal volume spaces ESPV1 and ESPV2. By locally reducing the thickness of the areas of the coating 4, the thermal chain of the encapsulated BT is reduced, while maintaining the overall thickness of the coating 4 required to obtain the robustness sought by the encapsulated BT. This therefore makes it possible to maintain a maximum junction temperature that does not degrade the integrated circuit when the electronic chip 2 is in operation.
As shown in the cross-sectional view in fig. 2, the contoured portion 410 of the contoured top surface 41 of the coating 4 includes a first hollow region 4101. The first hollow region 4101 extends in the direction of the base substrate 1 and defines a first portion 42 of the reduced area of the coating 4.
The first hollow region 4101 may be a groove. A first portion 42 of the reduced area of the coating 4 at least partially covers the electronic chip 2. In particular, the portion of the electronic chip 2 covered by the first portion 42 comprises at least some hot spots that generate heat in the thermal volume ESPV1 when the electronic chip 2 is in operation. In this case, the first portion 42 and the first hollow region 4101 may be located in the thermal volume space ESPV1.
The contoured portion 410 of the contoured top surface 41 of the coating 4 here also includes a second hollow region 4102. The second hollow zone 4102 extends in the direction of the base substrate 1 and delimits at least a second portion 43 of the reduced area of the coating 4. For example, the second hollow region 4102 may form a groove surrounding the first portion 42. The second portion 43 is positioned laterally with respect to the first portion 42 of reduced area of the coating 4. In particular, at least a portion of the second portion 43 and of the second hollow zone may be located in the thermal volume space ESPV1.
The reduced area second portion 43 of the coating 4 also helps to reduce the thermal link of the encapsulated BT in the thermal volume space ESPV1.
The contoured portion 410 of the contoured top surface 41 of the coating 4 here also includes a third hollow region 4103. The third hollow zone 4103 extends in the direction of the base substrate 1 and delimits at least a third portion 44 of the reduced area of the coating 4. The third hollow region 4103 may form a groove surrounding the second portion 43, for example. The third portion 44 is positioned laterally with respect to the second portion 43 of reduced area of the coating 4. In particular, at least a portion of the third hollow zone may be located in the thermal volume space ESPV1.
The reduced area third portion 44 of the coating 4 also helps to reduce the thermal link of the encapsulated BT in the thermal volume space ESPV1.
In case the package contains a smaller electronic chip 2 that generates heat in the narrower thermal volume space ESPV2, the hollow region 4103 can be avoided.
One skilled in the art will know how to define the coating profile based on the hot spots of the chip in operation and the robustness of the package sought.
By way of illustration, fig. 3 schematically shows the dimensions of the package in fig. 1. The first dimension C corresponds to the thickness of the coating 4. The second dimension D and the third dimension E correspond to the width and depth of the first hollow region 4101 of the outline portion 410, respectively. The fourth dimension F and the fifth dimension G correspond to the width and depth, respectively, of the third hollow region 4103 of the contoured portion 410.
Those skilled in the art will know how to define the dimensions of C, D, E, F and G in order to obtain a package BT capable of dissipating heat and maintaining a maximum junction temperature that does not degrade the integrated circuit when the chip 2 is in operation, while maintaining the robustness sought by the package BT.
For example, a person skilled in the art can define a dimension C of 800 μm, a dimension D having a value corresponding to 90% of the surface area of the electronic chip 2, a dimension E of 400 μm, a dimension F having a value between 2mm and 3mm, and a dimension G of 400 μm.
Heat dissipation enhancement of about 20% or more can be observed according to local reduction on the resin and according to hot spots on the electronic chip. In the embodiment of fig. 1, adhesive layer 6 has a contour that molds (i.e., conforms to) the contoured top surface 41 of coating 4. The heat sink 5 then comprises a shaped bottom surface 50 and a flat top surface 51. The contoured bottom surface of the heat sink 5 molds (i.e., conforms to) the contours of the adhesive layer 6. In particular, the shaped bottom surface 50 of the heat sink 5 forms fins suitable for inserting into the hollow zones 4101, 4102 and 4103 of the contoured portion 410 of the coating 4.
The fins formed by the profiled bottom surface 50 make it possible to increase the surface area of the heat sink 5 at the location where the portions 42, 43 and 44 of reduced area of the coating 4 are located, and thus enable the heat sink 5 to reject more heat out of the package BT.
Alternatively, as shown in fig. 4, the adhesive layer 6 has a contoured bottom surface 60 and a flat top surface 61. The contoured bottom surface 60 of the adhesive layer 6 then molds (i.e., conforms to) the contoured top surface 41 of the coating 4. In particular, the adhesive layer 6 fills the hollow regions 4101, 4102, and 4103 so that the top surface 61 of the adhesive layer 6 remains flat. In the same alternative embodiment, the heat sink 5 has a flat bottom surface 50 and a flat top surface 51. The flat bottom surface 50 of the heat sink 5 is mounted on the flat top surface 61 of the adhesive layer 6.
It is therefore possible to envisage the heat sink 5 with a simple geometry, which makes it possible in particular to simplify the manufacture of the package BT.
As shown in the above figures, BT packages employ "wire bonding" techniques.
Alternatively, however, the package may be of the type that uses a so-called "flip-chip" technique, as shown in fig. 5. In this case, the chip comprises a bottom surface provided with electrically conductive connection balls 10, as is well known. These connection balls 10 are mounted on the face FS of the base substrate 1.
In addition, the connection balls 10 are typically embedded in the "underfill" layer 8. The underfill layer 8 may be formed of a resin similar to that used for the coating layer 4.
The characteristics of the coating 4, mounting layer 6 and heat sink described with reference to the above figures are applicable to the embodiment of the package in fig. 5.
Claims (22)
1. An integrated circuit package, the integrated circuit package comprising:
a base substrate;
an electronic chip mounted on a face of the base substrate;
a coating encapsulating the electronic chip, the coating having a bottom surface mounted on the face of the base substrate, and the coating further having a contoured top surface;
wherein a portion of the contoured top surface is configured to locally reduce the volume of an area of the coating; and
a heat sink mounted on the profiled top surface of the coating using a mounting layer.
2. The integrated circuit package of claim 1, wherein the mounting layer has a contour molded to the contoured top surface of the coating, and wherein the heat spreader has a contoured bottom surface molded to the contour of the mounting layer, and the heat spreader further comprises a flat top surface.
3. The integrated circuit package of claim 1, wherein the mounting layer has a contoured bottom surface molded to the contoured top surface of the coating, and the mounting layer further comprises a flat top surface, and wherein the heat spreader has a flat bottom surface and a flat top surface mounted on the flat top surface of the mounting layer.
4. The integrated circuit package of claim 1, wherein the portion of the contoured top surface of the coating includes a first hollow region extending in a direction of the base substrate and defining a corresponding first locally reduced volume of the coating that at least partially covers the electronic chip.
5. The integrated circuit package of claim 4, wherein the portion of the contoured top surface of the coating further comprises a second hollow region extending in the direction of the base substrate and defining a corresponding second locally reduced volume of the coating, the second locally reduced volume being laterally positioned relative to the first locally reduced volume of the coating.
6. The integrated circuit package of claim 1, wherein the electronic chip comprises: a bottom surface mounted on the face of the base substrate by an adhesive layer; and a top surface comprising contact pads electrically connected to contact pads of the face of the base substrate by connecting lines, and wherein the coating further encapsulates the contact pads and the connecting lines.
7. The integrated circuit package of claim 1, wherein the electronic chip includes a bottom surface equipped with conductive connection balls mounted on the face of the substrate.
8. The integrated circuit package of claim 1, wherein the contoured top surface is defined by:
a first hollow region extending in a direction of the base substrate and positioned vertically above the electronic chip; and
a second hollow region extending in a direction of the base substrate and laterally away from and surrounding the first hollow region.
9. The integrated circuit package of claim 8, wherein the first hollow region has a first depth from an upper surface of the coating and the second hollow region has a second depth from the upper surface of the coating, and wherein the first depth is greater than the second depth.
10. The integrated circuit package of claim 8, wherein the first hollow region has a first depth from an upper surface of the coating and the second hollow region has a second depth from the upper surface of the coating, and wherein the second depth is greater than the first depth.
11. An integrated circuit package, the integrated circuit package comprising:
a base substrate;
an electronic chip mounted on a face of the base substrate;
a coating encapsulating the electronic chip and mounted to the face of the base substrate, and further having a contoured top surface defined by a plurality of hollow regions that locally reduce the volume of corresponding regions of the coating;
a mounting layer filling the plurality of hollow areas and covering the coating to provide a flat top surface; and
a heat sink having a flat bottom surface mounted on the flat top surface of the mounting layer.
12. The integrated circuit package of claim 11, wherein the plurality of hollowed regions comprises a first hollowed region that extends in a direction of the base substrate and provides a first partially reduced volume of the coating that extends directly over the electronic chip.
13. The integrated circuit package of claim 12, wherein the plurality of hollow regions further comprises a second hollow region extending in a direction of the base substrate and providing a second locally reduced volume of the coating layer, the second locally reduced volume positioned laterally relative to the first locally reduced volume.
14. The integrated circuit package of claim 13, wherein the second locally reduced volume of the coating extends partially over the electronic chip and partially beyond an outer perimeter of the electronic chip.
15. The integrated circuit package of claim 14, wherein a depth of the first hollow region is deeper than a depth of the second hollow region.
16. The integrated circuit package of claim 13, wherein the second locally reduced volume of the coating extends completely laterally beyond an outer perimeter of the electronic chip.
17. The integrated circuit package of claim 16, wherein a depth of the second hollow region is deeper than a depth of the first hollow region.
18. An integrated circuit package, the integrated circuit package comprising:
a base substrate;
an electronic chip mounted on a face of the base substrate;
a coating encapsulating the electronic chip and mounted to the face of the base substrate, and further having a contoured top surface defined by a plurality of hollow regions that locally reduce the volume of corresponding regions of the coating;
wherein the plurality of hollow areas comprises:
a first hollow region extending in the direction of the base substrate and providing a first locally reduced volume of the coating layer, the first locally reduced volume extending directly over the electronic chip; and
a second hollow region extending in the direction of the base substrate and providing a second locally reduced volume of the coating, the second locally reduced volume being laterally positioned relative to the first locally reduced volume; and
a heat sink mounted on the profiled top surface of the coating using a mounting layer.
19. The integrated circuit package of claim 18, wherein the second locally reduced volume of the coating extends partially over the electronic chip and partially beyond an outer perimeter of the electronic chip.
20. The integrated circuit package of claim 19, wherein a depth of the first hollow region is deeper than a depth of the second hollow region.
21. The integrated circuit package of claim 18, wherein the second locally reduced volume of the coating extends completely laterally beyond an outer perimeter of the electronic chip.
22. The integrated circuit package of claim 21, wherein a depth of the second hollow region is deeper than a depth of the first hollow region.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR2108970 | 2021-08-27 | ||
| FR2108970A FR3126543B1 (en) | 2021-08-27 | 2021-08-27 | INTEGRATED CIRCUIT PACKAGE |
| US17/884,980 US20230060870A1 (en) | 2021-08-27 | 2022-08-10 | Integrated circuit package |
| US17/884,980 | 2022-08-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN218498056U true CN218498056U (en) | 2023-02-17 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211035799.9A Pending CN115910948A (en) | 2021-08-27 | 2022-08-26 | Integrated circuit package |
| CN202222261598.2U Active CN218498056U (en) | 2021-08-27 | 2022-08-26 | Integrated circuit package |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211035799.9A Pending CN115910948A (en) | 2021-08-27 | 2022-08-26 | Integrated circuit package |
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| CN (2) | CN115910948A (en) |
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2022
- 2022-08-26 CN CN202211035799.9A patent/CN115910948A/en active Pending
- 2022-08-26 CN CN202222261598.2U patent/CN218498056U/en active Active
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| CN115910948A (en) | 2023-04-04 |
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