CN218497188U - Double-layer optical chip and coupling interface structure for coupling optical chip and optical fiber - Google Patents
Double-layer optical chip and coupling interface structure for coupling optical chip and optical fiber Download PDFInfo
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- CN218497188U CN218497188U CN202223037755.8U CN202223037755U CN218497188U CN 218497188 U CN218497188 U CN 218497188U CN 202223037755 U CN202223037755 U CN 202223037755U CN 218497188 U CN218497188 U CN 218497188U
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- 230000003287 optical effect Effects 0.000 title claims abstract description 113
- 238000010168 coupling process Methods 0.000 title claims abstract description 75
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- 239000013307 optical fiber Substances 0.000 title claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 39
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- 230000000694 effects Effects 0.000 claims abstract description 14
- 239000010410 layer Substances 0.000 claims description 144
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 26
- 229910052710 silicon Inorganic materials 0.000 claims description 26
- 239000010703 silicon Substances 0.000 claims description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 22
- 239000000835 fiber Substances 0.000 claims description 14
- 239000012792 core layer Substances 0.000 claims description 11
- 239000000377 silicon dioxide Substances 0.000 claims description 11
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Abstract
The utility model provides a double-deck optical chip and optical fiber coupling's coupling interface structure, double-deck optical chip is the lamellar structure, and double-deck optical chip includes first substrate layer, second substrate layer, lower floor's waveguide, first isolation layer, upper waveguide, second isolation layer and the on-chip heat source that sets up from bottom to top in proper order; the first substrate layer is used for supporting the structural strength of the whole optical chip and isolating external optical signals; the second substrate layer provides support for the lower layer waveguide, and meanwhile, light fields in the upper layer waveguide and the lower layer waveguide are prevented from leaking into the first substrate layer; the on-chip heat source is used for applying heat effect to the upper layer waveguide and the lower layer waveguide. The utility model discloses can realize the effect that the coupling light field switches as required between the upper and lower optical waveguide layer to improve the holistic working property of 3D integrated optical chip, and can reach the purpose that promotes optical chip coupling efficiency when realizing that the coupling light field switches the effect as required between the upper and lower optical waveguide layer.
Description
Technical Field
The utility model relates to an optoelectronic device field specifically relates to a double-deck optical chip and optical fiber coupling's coupling interface structure, especially relates to a double-deck changeable integrated optical coupling interface on piece, especially relates to a double-deck adjustable coupling interface that is used for optical chip and optical fiber coupling.
Background
With the rapid increase of communication data capacity in human society, the demand of bandwidth increase is more and more prominent. While the traditional data transmission using electricity as a medium has the limitations of limited bandwidth and large energy consumption, the silicon-based optical chip with the advantages of large bandwidth potential, low energy consumption, compatibility with the CMOS processing technology and the like gradually becomes a solution for breaking through the performance limit of the traditional electrical chip with the development of the silicon optical technology, and is also paid attention by more and more researchers. On the other hand, not satisfying the existing single-layer optical chip, many researchers have proposed and processed 3D integrated optical chips with double-layer or even multi-layer structure by improving related processes, and further improve the upper limit of data processing and signal transmission of optical chips by improving physical structure.
In order to promote the practical application of the double-layer optical chip, the coupling efficiency between the optical chip and the optical fiber needs to be improved as much as possible, so that more optical field energy in the optical fiber can be coupled into the optical chip, and the utilization efficiency of the energy is improved.
Meanwhile, a structure capable of realizing optical field switching is also needed, so that the path selection of the optical field between the double-layer optical waveguides can be directly regulated and controlled through a related control method, and the application range of the double-layer optical chip is expanded.
Patent document CN114967004a discloses a coupling method of an optical fiber array and a silicon optical chip, which includes the following steps: s1, fixing a silicon optical chip on a substrate, wherein four end face coupling waveguides of the silicon optical chip can be matched with an optical fiber array in a mode field, and S2, after the silicon optical chip is fixed, mounting the substrate on a PCB (printed circuit board); s3, respectively connecting the two coupling reference single-mode fibers of the fiber array with a tunable laser light source and a photoelectric detector; and S4, coating optical glue on the PCB, adjusting the alignment of the optical fiber array and the end face coupling waveguide of the silicon optical chip, stopping moving the optical fiber array when the power on the photoelectric detector reaches the maximum, and adhering the optical fiber array at the position to the PCB. However, the coupling efficiency between the optical chip and the optical fiber is still low, and the optical chip does not have the function of optical field switching.
SUMMERY OF THE UTILITY MODEL
To the defect among the prior art, the utility model aims at providing a coupling interface structure of double-deck optical chip and fiber coupling.
According to the utility model, the double-layer optical chip has a layered structure, the double-layer optical core comprises a first substrate layer, a second substrate layer, a lower-layer waveguide, a first isolation layer, an upper-layer waveguide, a second isolation layer and an on-chip heat source which are arranged from bottom to top in sequence;
the first substrate layer is used for supporting the structural strength of the whole optical chip and isolating external optical signals;
the second substrate layer provides support for the lower layer waveguide, and meanwhile, light fields in the upper layer waveguide and the lower layer waveguide are prevented from leaking into the first substrate layer;
the first isolation layer is used for isolating the lower layer waveguide from the upper layer waveguide; the second isolating layer is used for isolating the upper waveguide from the on-chip heat source;
the on-chip heat source is used for applying heat effect to the upper layer waveguide and the lower layer waveguide.
Preferably, the on-chip heat source comprises a heat source layer, a hot electrode and an electric wire; the hot electrode and the electric wire are both arranged on the hot source layer;
the thermode is used for controlling the heat source layer, and the temperature of the heat source layer is changed through the change of the applied voltage.
Preferably, the upper layer waveguide has a first ridge waveguide structure.
Preferably, the lower layer waveguide has a second ridge waveguide structure;
the first ridge waveguide structure and the second ridge waveguide structure can generate a coupling effect.
Preferably, the first substrate layer is a silicon substrate.
The second substrate layer is a silicon dioxide substrate layer;
the first isolation layer is a silicon dioxide layer;
the second isolation layer is a silicon dioxide layer.
Preferably, the lower waveguide layer is a silicon waveguide layer; the upper waveguide layer is a silicon waveguide layer;
preferably, the first ridge waveguide structure is identical to the second ridge waveguide structure.
Preferably, the second ridge waveguide structure includes a central region and a ridge region.
Preferably, the height of the central region is greater than the height of the ridge region, the width of the ridge type waveguide in the central region is 450nm, the height of the ridge type waveguide in the central region is 150nm, and the height of the ridge region is 70nm.
According to the utility model provides a coupling interface structure of optical chip and optical fiber coupling, which comprises an optical fiber and a double-layer optical chip;
the optical fiber comprises an optical fiber cladding and an optical fiber core layer; the optical fiber cladding is coated on the outer side of the optical fiber core layer;
the second substrate layer, the lower layer waveguide, the first isolation layer, the upper layer waveguide, the second isolation layer and the heat source layer are coupled with the optical fiber core layer.
Compared with the prior art, the utility model discloses following beneficial effect has:
the utility model provides a double-deck optical chip through the design of upper waveguide and the double-deck waveguide of lower floor's waveguide, can realize the effect that the coupling light field switches as required between the upper and lower optical waveguide layer to improve the holistic workability of 3D integrated optical chip, and can reach the purpose that promotes optical chip coupling efficiency when realizing that the coupling light field switches the effect as required between the upper and lower optical waveguide layer.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
fig. 1 is a schematic structural view of a double-layer optical chip of the present invention;
FIG. 2 is a schematic view of the structure of the lower waveguide;
FIG. 3 is a detailed structural diagram of a dual-layer optical chip;
FIG. 4 is a schematic structural diagram of a coupling interface structure for fiber coupling;
FIG. 5 is a view of the optical field distribution of the optical chip at high temperature;
FIG. 6 is a view of the optical field distribution of the optical chip at a low temperature;
fig. 7 is a mode field diagram of the cross section of the coupling interface structure for coupling the optical chip and the optical fiber according to the present invention;
fig. 8 is a structural diagram illustrating a mode field diagram of a cross section of a coupling interface structure for coupling a conventional single-layer optical chip and an optical fiber.
The figures show that:
Detailed Description
The present invention will be described in detail with reference to the following embodiments. The following examples will assist those skilled in the art in further understanding the present invention, but are not intended to limit the invention in any way. It should be noted that various changes and modifications can be made by one skilled in the art without departing from the spirit of the invention. These all belong to the protection scope of the present invention.
The utility model provides a double-deck optical chip, as shown in figure 1, the double-deck optical chip is a laminated structure, and the double-deck optical chip comprises a first substrate layer 101, a second substrate layer 102, a lower layer waveguide 103, a first isolation layer 104, an upper layer waveguide 105, a second isolation layer 106 and an on-chip heat source which are arranged from bottom to top in sequence;
the first substrate layer 101 is mainly used for supporting the structural strength of the whole optical chip and isolating external optical signals; the second substrate layer 102 provides support for the lower waveguide 103, and meanwhile, optical fields in the upper waveguide 105 and the lower waveguide 103 are prevented from leaking into the first substrate layer 101; the first isolation layer 104 is mainly used for separating the lower waveguide 103 from the upper waveguide 105; a second isolation layer 106 for isolating the upper waveguide 105 from the on-chip heat source; the on-chip heat source is primarily used to apply thermal effects to the upper waveguide 105 and the lower waveguide 103. The upper waveguide 105 and the lower waveguide 103 form a main part of a dual-layer optical chip, and are used for forming a specific optical waveguide structure so as to realize optical field transmission of a specific function.
The on-chip heat source includes a heat source layer 107, a hot electrode 1071, and electrical traces 1072; a hot electrode 1071 and electrical traces 1072 are both mounted on the hot source layer 107; the thermode is used to control the heat source layer 107, and the temperature of the heat source layer 107 is changed by the change of the applied voltage. The heat source layer 107 is used for exerting the influence of the heat effect on the two layers of silicon waveguides, so that the refractive indexes of the waveguides are correspondingly changed, the coupling conditions between the two layers of waveguides are further influenced, and the effect of adjustable optical field coupling is achieved. The light field distribution in the upper layer waveguide 105 and the lower layer waveguide 103 can be effectively regulated and controlled by regulating the heat source on the sheet, so that the purpose of switchable double-layer waveguide light fields is achieved.
The upper waveguide 105 and the lower waveguide 103 are processed into waveguide shapes corresponding to each other by a semiconductor process. The upper layer waveguide 105 has a first ridge waveguide structure, and the lower layer waveguide 103 has a second ridge waveguide structure; the first ridge waveguide structure and the second ridge waveguide structure can generate a coupling effect, and a coupling interface design capable of reducing mismatch of an effective mode field surface between the first ridge waveguide structure and the optical fiber end surface is formed.
As shown in fig. 2 and 3, the second ridge waveguide structure includes a central region 1032 and a ridge region 1033; the height of the central region 1032 is greater than the height of the ridge region 1033, the width of the ridge waveguide of the central region 1032 is 450nm, the height of the ridge waveguide is 150nm, and the height of the ridge region 1033 is 70nm. The ridge waveguide structure of the upper silicon waveguide is consistent with that of the lower silicon waveguide.
In a preferred embodiment, the first substrate layer 101 is a silicon substrate in a silicon wafer. Second substrate layer 102 is a silicon dioxide substrate layer; the first isolation layer 104 is a silicon dioxide layer; the second isolation layer 106 is a silicon dioxide layer. The lower waveguide 103 is a silicon waveguide layer; the upper waveguide 105 is a silicon waveguide layer; the thicknesses of the first substrate layer 101, the second substrate layer 102, the lower waveguide 103, the first isolation layer 104, the upper waveguide 105, and the second isolation layer 106 are 500 μm,3 μm,220nm,120nm,220nm, and 850nm, respectively.
The utility model also provides a coupling interface structure for coupling the optical chip and the optical fiber, which comprises the optical fiber and the double-layer optical chip; the optical fiber comprises a fiber cladding 402 and a fiber core 403; the optical fiber cladding 402 is coated outside the optical fiber core layer 403; the second substrate layer 102, the lower waveguide 103, the first isolation layer 104, the upper waveguide 105, the second isolation layer 106, and the heat source layer 107 are coupled to the optical fiber core layer 403.
As shown in fig. 4, a coupling alignment region 401 of an optical fiber and a chip is shown, specifically, when an optical chip is coupled with an optical fiber, the center of an optical fiber core layer 403 is aligned with the centers of upper and lower waveguide layers of the optical chip, and an optical field in the optical fiber is coupled into two layers of waveguides on the optical chip. Since the refractive index of the optical fiber core layer 403 is smaller than that of the silicon waveguide, and the optical fiber core layer 403 has weaker optical field constraint capability, the diameter of the optical fiber core layer 403 is generally much larger than the size of the silicon waveguide of the optical chip, and the mode area of the optical field propagating in the fiber core is also much larger than the mode area of the optical field in the waveguide. This results in a large difference in effective mode field area between the optical field in the fiber and the optical field in the waveguide, which results in additional coupled optical energy loss, and thus affects the coupling efficiency between the fiber and the chip. And through the utility model provides a coupling interface structure of optical chip and optical fiber coupling, this kind of double-deck coupling structure can effectively improve the light field mode area of interface terminal surface, and then reduces the loss that the coupling brought between optic fibre and the optical chip. Fig. 7 is a mode field diagram of a coupling interface structure of an optical chip and an optical fiber coupling provided by the present invention, and fig. 8 is a mode field diagram of a coupling interface section of a conventional single-layer waveguide. The utility model discloses an among the double-deck optical waveguide coupling structure, because there is certain coupling between the waveguide, and the light field has certain diffusion, leads to its effective mode field area to be greater than the effective mode field area of individual layer waveguide coupling interface. Taking the structures mentioned in fig. 2 and 3 as examples, the effective mode field area of the double-layer waveguide coupling interface is nearly three times (23.7 × 10) that of the single-layer waveguide coupling interface -14 m 2 And 8.7X 10 -14 m 2 ). Based on the structure, the effective mode field area between the optical fiber and the chipMismatch is effectively improved, thereby increasing coupling efficiency.
As shown in fig. 5-6, when the heat source is adjusted to produce thermal effects at different temperatures, the refractive index of the waveguide will change accordingly due to the temperature change. Fig. 5 is a view of the optical field distribution of the optical chip at a high temperature, and fig. 6 is a view of the optical field distribution of the optical chip at a low temperature. The unit coupling length of two adjacent waveguides, i.e. the propagation length required for coupling the optical field from one waveguide into the other waveguide, is related to the refractive index of the waveguides, so that changing the temperature changes the refractive index of the two waveguides, thereby affecting the unit coupling length. When the length of the coupling region of the chip waveguide is fixed, the light field distribution in the waveguide can be adjusted by adjusting the heat source, so that the purpose of adjusting the light field is achieved.
The working principle of the utility model is as follows:
based on the closer distance between the double-layer silicon waveguides, the light field is coupled and diffused between the two layers of silicon waveguides, so that the effective mode field area of the coupling end face light field is enlarged, the mismatching between the mode field area and the optical fiber end face mode field area is reduced, and the coupling efficiency of the chip and the optical fiber is improved. On the other hand, based on the principle that the change of the refractive index of the waveguide is caused by the change of the temperature, the purpose of controlling the temperature by using the on-chip heat source is realized, so that the refractive index of the waveguide is influenced, the coupling condition of the optical field between the upper layer of adjacent silicon waveguide and the lower layer of adjacent silicon waveguide is further influenced, and the effect of switching the optical field transmission in the upper layer of waveguide and the lower layer of waveguide is realized.
The utility model provides an optical chip and optical fiber coupling's coupling interface structure is a coupling interface structure based on silica-based optical chip and optical fiber coupling or the piece on integrated coupling interface based on other material platforms of similar structure, does not confine to silica-based platform. The utility model provides an optical chip can effectively improve the coupling efficiency between chip and the optic fibre with the coupling interface structure of fiber coupling, realizes the changeable function of light field between the waveguide layer simultaneously.
The utility model provides a novel double-deck optical chip and optical fiber coupling's coupling interface structure, double-deck optical chip can realize the effect that the coupling light field switches as required between the upper and lower optical waveguide layer to improve the holistic workability of 3D integrated optical chip, and can reach the purpose that promotes optical chip coupling efficiency when realizing that the coupling light field switches the effect as required between the upper and lower optical waveguide layer.
In the description of the present application, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present application.
The foregoing descriptions have been directed to embodiments of the present invention. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by those skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.
Claims (8)
1. A double-layer optical chip is characterized in that the double-layer optical chip is of a layered structure and comprises a first substrate layer (101), a second substrate layer (102), a lower-layer waveguide (103), a first isolation layer (104), an upper-layer waveguide (105), a second isolation layer (106) and an on-chip heat source which are sequentially arranged from bottom to top;
the first substrate layer (101) is used for supporting the structural strength of the whole optical chip and isolating external optical signals;
the second substrate layer (102) provides support for the lower waveguide (103) and simultaneously avoids optical fields in the upper waveguide (105) and the lower waveguide (103) from leaking into the first substrate layer (101);
a first isolation layer (104) for isolating the lower waveguide (103) from the upper waveguide (105); a second isolation layer (106) for isolating the upper waveguide (105) from the on-chip heat source;
the on-chip heat source is used for applying heat effect to the upper layer waveguide (105) and the lower layer waveguide (103);
the upper layer waveguide (105) has a first ridge waveguide structure;
the lower layer waveguide (103) has a second ridge waveguide structure.
2. The dual-layer optical chip of claim 1, wherein the on-chip heat source comprises a heat source layer (107), a hot electrode (1071), and electrical traces (1072); a thermode (1071) and electrical traces (1072) are both mounted on the heat source layer (107);
the thermode (1071) is used for controlling the heat source layer (107), the temperature of the heat source layer (107) is changed by the change of the applied voltage,
the first ridge waveguide structure and the second ridge waveguide structure can generate coupling effect.
3. The dual-layer photonic chip of claim 1, wherein the first substrate layer (101) is a silicon substrate;
the second substrate layer (102) is a silicon dioxide substrate layer;
the first isolation layer (104) is a silicon dioxide layer;
the second isolation layer (106) is a silicon dioxide layer.
4. The dual-layer optical chip of claim 1, wherein the lower waveguide (103) is a silicon waveguide layer; the upper waveguide (105) is a silicon waveguide layer.
5. The dual-layer optical chip of claim 1, wherein the first ridge waveguide structure is identical to the second ridge waveguide structure.
6. The dual-layer optical chip of claim 1, wherein the second ridge waveguide structure comprises a central region (1032) and a ridge region (1033).
7. The dual layer optical chip of claim 6, wherein the height of the central region (1032) is greater than the height of the ridge region (1033), the width of the ridge waveguide of the central region (1032) is 450nm, the height is 150nm, and the height of the ridge region (1033) is 70nm.
8. A coupling interface structure for coupling an optical chip and an optical fiber, comprising the optical fiber and the double-layer optical chip according to any one of claims 1 to 7;
the optical fiber comprises a fiber cladding (402) and a fiber core (403); the optical fiber cladding (402) is coated outside the optical fiber core layer (403);
the second substrate layer (102), the lower layer waveguide (103), the first isolation layer (104), the upper layer waveguide (105), the second isolation layer (106) and the heat source layer (107) are coupled with the optical fiber core layer (403).
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Effective date of registration: 20230915 Address after: 200240 No. 800, Dongchuan Road, Shanghai, Minhang District Patentee after: Du Jiangbing Address before: 200240 No. 800, Dongchuan Road, Shanghai, Minhang District Patentee before: SHANGHAI JIAO TONG University |
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Effective date of registration: 20240430 Address after: 200241, Room 3868, Building C, No. 555 Dongchuan Road, Minhang District, Shanghai Patentee after: Shanghai Weilande Technology Co.,Ltd. Country or region after: China Address before: 200240 No. 800, Dongchuan Road, Shanghai, Minhang District Patentee before: Du Jiangbing Country or region before: China |