CN218456649U - Electronic element and electronic equipment - Google Patents

Abstract

The utility model relates to an electronic component, electronic equipment, wherein the electronic component includes the capacitor bank that a plurality of capacitor units pile up, each capacitor unit all includes the laminated structure of conducting layer/dielectric layer/conducting layer; a step-shaped structure is formed on one side of the capacitor unit, and partial surfaces of the conductive layer and the dielectric layer in the laminated structure are exposed to form a step surface; on the other side of the capacitor unit, the dielectric layer in the laminated structure is arranged to protrude from the side wall of the adjacent upper and lower conductive layers; one side of the capacitor units adjacent up and down to form a stepped structure is distributed in a staggered manner; forming an insulating material on each side of the capacitor unit; the width of the insulating material formed on the side wall of the dielectric layer is less than or equal to the width of the insulating material formed on the side wall of the conductive layer.

Description

Electronic element and electronic equipment

Technical Field

The present invention relates to integrated circuits, and more particularly, to an electronic component.

Background

With the development of integrated circuit manufacturing technology, the integrated circuit manufacturing technology has been applied to the production and manufacture of micro capacitive elements in the prior art. A common micro capacitor element in the market at present is a Y-type three-dimensional capacitor represented mainly by japan village.

As shown in fig. 1, the Y-shaped three-dimensional capacitor is engraved into a Y-shaped three-dimensional structure on a single substrate, such as a wafer 1, by using a photolithography technique, and then is deposited and grown into a three-layer composite structure of an electrode/an insulating layer/an electrode, and a micro structure is used to increase a surface area, thereby realizing a large capacitance value. However, the Y-shaped three-dimensional capacitor 2 is generally completed by deep trench etching, and the depth of the deep trench is limited by the capability of the existing integrated circuit manufacturing process and cannot be etched too deeply, so that the requirement of high capacitance value in unit area is limited; moreover, if the deep trench is too deep, the thickness of the top and the bottom of the deep trench is not uniform, and the periphery and the center of the wafer are not uniform, so that the product quality is influenced; in addition, the thickness of the dielectric layer of the deep trench structure is limited, so that the requirement of high voltage is difficult to meet; in addition, the corners of the structure are more, so that the deposition growth of the thickness of the electrode plate is uneven, the accuracy of the capacitance value of the capacitor is influenced, in addition, the structure of the groove-type capacitor is complex, the manufacture is complicated, the individual Y-shaped body collapses during the processing, the yield of finished products is influenced, and the cost is greatly increased.

Fig. 2 shows another prior art. There is also a technique of forming a capacitor having a plurality of conductive films 120 and dielectric films 121 alternately stacked on a wafer 110 by an integrated circuit process, forming an insulating layer 190 on a sidewall of the capacitor, electrically connected through a conductive material layer 150, a conductive via 170 and an external electrode 130, and further electrically connected through a conductive material layer 160, a conductive via 180 and another external electrode 140, wherein the conductive material layer 150, the conductive material layer 160, the conductive via 170 and the conductive via 180 are formed in a dielectric layer 210. The capacitor of the prior art is manufactured with a smaller volume and higher density, and the manufacturing cost of the capacitor can be reduced. However, the external electrodes of the capacitor are prepared only on a single surface, which is inconvenient for three-dimensional expansion packaging, and in a semiconductor capacitor having a three-dimensional structure in which a plurality of conductive films and dielectric films are alternately stacked, there is a problem in that adjustment of withstand voltage is difficult. Therefore, there is a need to further improve the high voltage endurance of the semiconductor capacitor and improve the flexibility of the packaging application thereof on the basis of reducing the volume, increasing the capacity and reducing the cost.

The utility model provides an above-mentioned technical problem designs a novel capacitor structure, can enough compatible current integrated circuit technology, avoids the condenser exists if there are defects such as bubble, pinhole in the current piece formula multilayer ceramic capacitor (MLCC) dielectric film, can further improve on the basis that reduces the condenser volume, improves capacity, reliability and reduce cost again the high pressure resistant ability of condenser and the flexibility that improves its encapsulation and use.

Disclosure of Invention

A brief summary of the present invention will be given below to provide a basic understanding of some aspects of the invention. It should be understood that this summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.

According to an aspect of the present invention, there is provided an electronic component, including: a capacitor group in which a plurality of capacitor units are stacked, each of the capacitor units including a laminated structure of a conductive layer/a dielectric layer/a conductive layer; forming a stepped structure on one side of the capacitor unit, and exposing partial surfaces of the conductive layer and the dielectric layer in the laminated structure to form a stepped surface; on the other side of the capacitor unit, the dielectric layer in the laminated structure is arranged to protrude from the side wall of the adjacent upper and lower conductive layers; one side of the adjacent capacitor units forming the step-type structure is distributed in a staggered mode; forming an insulating material on each side of the capacitor unit; the width of the insulating material formed on the side wall of the dielectric layer is smaller than or equal to the width of the insulating material formed on the side wall of the conductive layer.

Further wherein the width of the insulating material formed on the sidewalls of the dielectric layer is 0-300nm less than the width of the insulating material formed on the sidewalls of the conductive layer.

Further, the structural arrangement of the opposite side walls between the adjacent capacitor banks is mirror symmetry.

Further, positive and negative electrode structures formed on the upper surface of the capacitor bank and/or positive and negative electrode structures formed on the lower surface of the capacitor bank are included.

Further, the positive and negative electrode structures formed on the lower surface are formed on a surface of the substrate facing away from the capacitor bank.

Further, a conductive structure is formed on the two side walls of the capacitor group to respectively connect all or part of the partial surfaces of the conductive layers exposed at the corresponding sides of the capacitor units.

Further wherein the conductive structure fills between opposing sides of adjacent capacitor banks and has a planar upper surface to integrate with positive and negative electrode structures of the upper surface.

Further, when the positive and negative electrode structures are formed on the upper and lower surfaces of the capacitor bank, the positive and negative electrode structures formed on the upper and lower surfaces of the capacitor bank are correspondingly connected through the conductive structure.

According to another aspect of the present invention, there is provided an electronic device including the electronic component of any one of the above aspects.

The utility model discloses a scheme can help realizing one of following effect at least: the manufacturing process is simple, the pressure resistance is easy to adjust, the product uniformity is easy to control, the capacity value is precise, the service life of the device is long, the reliability is good, the device is suitable for various severe environments, the production cost is low, and the packaging convenience is good.

Drawings

The above and other objects, features and advantages of the present invention will be more readily understood from the following description of the specific embodiments thereof with reference to the accompanying drawings. The drawings are only for the purpose of illustrating the principles of the invention. The dimensions and relative positioning of the elements in the figures are not necessarily drawn to scale.

FIGS. 1-2 show schematic diagrams of prior art capacitor structures;

figures 3-5 illustrate a first embodiment of the capacitor structure of the present invention;

fig. 6 shows a second embodiment of the method for fabricating a capacitor structure of the present invention.

Detailed Description

Exemplary disclosures of the present invention will be described hereinafter with reference to the accompanying drawings. In the interest of clarity and conciseness, not all features of an implementation of the present invention are described in the specification. It will be appreciated, however, that in the development of any such actual embodiment, numerous implementation-specific decisions may be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another.

Here, it should be noted that, in order to avoid obscuring the present invention due to unnecessary details, only the device structure closely related to the solution according to the present invention is shown in the drawings, and other details not closely related to the present invention are omitted.

It is to be understood that the invention is not limited to the described embodiments, since the following description refers to the accompanying drawings. Herein, features between different embodiments may be replaced or borrowed where feasible, and one or more features may be omitted in one embodiment.

First embodiment

Fig. 3-5 illustrate a first embodiment of the capacitor structure of the present invention, wherein like reference numerals refer to like parts.

Fig. 3 is a plan view of the structure of this embodiment. As can be seen from fig. 3, N capacitor groups 20 (two capacitor groups are exemplarily shown in the figure) are formed on one substrate 10 at intervals, where N is a natural number. For example, N may be set to 5000 groups, but it should be understood by those skilled in the art that the number of the capacitor groups may be flexibly set according to actual needs, and is not particularly limited in the present disclosure. The substrate may exemplarily be: a single crystal/polycrystalline silicon substrate (Si), a silicon-on-insulator Substrate (SOI), a compound substrate of a III-V element, a glass substrate, a ceramic substrate, or the like may be used as a substrate material compatible with the semiconductor process, and a silicon substrate will be described below as an example.

Fig. 4 isbase:Sub>A sectional view taken alongbase:Sub>A-base:Sub>A direction in fig. 3. As can be seen from fig. 4, a plurality of through holes 11 are formed in the silicon substrate, and the through holes are filled with a conductive material, which may be selected from one or more alloys of heavily doped polysilicon, titanium/titanium nitride, aluminum, tungsten, copper, nickel, gold, palladium, silver, platinum, rhodium, cobalt, tin, and lead. A plurality of first electrodes 12 and second electrodes 13 are formed on the lower surface of the silicon substrate, which will serve as the positive and negative electrodes of the capacitor, respectively. An isolation layer (not shown) may be deposited on the upper surface of the substrate. The isolation layer may be a silicon oxide layer, a silicon oxide/silicon nitride/silicon oxide layer, hafnium oxide, aluminum oxide, zirconium oxide, titanium oxide, ruthenium oxide, or the like having a high dielectric constant, and the thickness of the isolation layer may be illustratively between 100nm and 500 nm.

Each of the capacitor banks 20 includes M stacked capacitor units, where M is a natural number. For example, M may be set to 128, but it should be understood by those skilled in the art that the number of the capacitor units may be flexibly set according to actual needs, and is not particularly limited in the present disclosure. Each capacitor unit is a laminated structure composed of a conductive layer/a dielectric layer/a conductive layer, and a common conductive layer is arranged between adjacent capacitor units.

Specifically, the capacitor unit stacked in the capacitor bank is defined as a first capacitor unit C1 closest to the substrate, a second capacitor unit C2 next closest to the substrate, and an mth capacitor unit Cm farthest from the substrate. The first capacitor unit is composed of a first conductive layer LC 1/a first dielectric layer LD 1/a second conductive layer LC 2. The first side wall of the first conducting layer is superposed with the projection of the first side wall of the second conducting layer on the upper surface of the substrate, and the second side wall of the first conducting layer is not superposed with the projection of the second side wall of the second conducting layer on the upper surface of the substrate. Specifically, a projection of the second sidewall of the second conductive layer falls within a projection of the first conductive layer on the upper surface of the substrate.

The projection of the first sidewall of the first conductive layer on the upper surface of the substrate falls within the projection of the first dielectric layer on the upper surface of the substrate. The projection of the second side wall of the first dielectric layer on the upper surface of the substrate is within the projection range of the first conductive layer on the upper surface of the substrate.

The projections of the first and second sidewalls of the second conductive layer on the upper surface of the substrate are both within the projection of the first dielectric layer on the upper surface of the substrate. Such that the first capacitor cell forms a step-like shape on the second side thereof, the step faces of the step-like shape being formed by the portion of the upper surface of the first conductive layer protruding beyond the second sidewall of the first dielectric layer and by the portion of the upper surface of the first dielectric layer protruding beyond the second sidewall of the second conductive layer, respectively.

The second capacitor unit is composed of second conductive layer LC 2/second dielectric layer LD 2/third conductive layer LC 2. The second side wall of the second conducting layer is coincident with the projection of the second side wall of the third conducting layer on the upper surface of the substrate, and the first side wall of the second conducting layer is not coincident with the projection of the first side wall of the third conducting layer on the upper surface of the substrate. Specifically, a projection of the first sidewall of the third conductive layer falls within a projection of the second conductive layer on the upper surface of the substrate, and a projection of the first sidewall of the second dielectric layer falls within a projection of the second conductive layer on the upper surface of the substrate.

The projection of the second sidewall of the second conductive layer on the upper surface of the substrate falls within the projection of the second dielectric layer on the upper surface of the substrate. The projection of the first side wall of the second dielectric layer on the upper surface of the substrate is in the range of the projection of the second conductive layer on the upper surface of the substrate.

The projections of the first and second sidewalls of the third conductive layer onto the upper surface of the substrate are within the projection of the second dielectric layer onto the upper surface of the substrate. Thereby forming the second capacitor cell in a step-like fashion on the first side thereof, the step surfaces of the step-like fashion being formed by the portion of the upper surface of the second conductive layer protruding from the first sidewall of the second dielectric layer and by the portion of the upper surface of the second dielectric layer protruding from the first sidewall of the third conductive layer, respectively.

The third capacitor unit is composed of a third conductive layer/a third dielectric layer/a fourth conductive layer. The conductive layer/dielectric layer/conductive layer of the third capacitor unit is arranged in the same manner as the first capacitor unit. The first side wall of the third conducting layer is superposed with the projection of the first side wall of the fourth conducting layer on the upper surface of the substrate, and the second side wall of the third conducting layer is not superposed with the projection of the second side wall of the fourth conducting layer on the upper surface of the substrate. Specifically, a projection of the second sidewall of the fourth conductive layer falls within a projection of the third conductive layer on the upper surface of the substrate.

The projection of the first side wall of the third conducting layer on the upper surface of the substrate is within the projection range of the third dielectric layer on the upper surface of the substrate. The projection of the second side wall of the third dielectric layer on the upper surface of the substrate is in the projection range of the third conducting layer on the upper surface of the substrate.

The projections of the first and second sidewalls of the fourth conductive layer onto the upper surface of the substrate are both within the projection of the third dielectric layer onto the upper surface of the substrate.

The fourth capacitor unit is composed of a fourth conductive layer/a fourth dielectric layer/a fifth conductive layer. The conductive layer/dielectric layer/conductive layer of the fourth capacitor unit is arranged in the same manner as the second capacitor unit.

The second side wall of the fourth conducting layer coincides with the projection of the second side wall of the fifth conducting layer on the upper surface of the substrate, and the first side wall of the fourth conducting layer does not coincide with the projection of the first side wall of the fifth conducting layer on the upper surface of the substrate. Specifically, a projection of the first sidewall of the fifth conductive layer falls within a projection of the fourth conductive layer on the upper surface of the substrate, and a projection of the first sidewall of the fourth dielectric layer falls within a projection of the fourth conductive layer on the upper surface of the substrate.

The projection of the second sidewall of the fourth conductive layer on the upper surface of the substrate falls within the projection of the fourth dielectric layer on the upper surface of the substrate. The projection of the first side wall of the fourth dielectric layer on the upper surface of the substrate is within the projection range of the fourth conductive layer on the upper surface of the substrate.

The projections of the first and second sidewalls of the fifth conductive layer onto the upper surface of the substrate are both within the projection of the fourth dielectric layer onto the upper surface of the substrate.

In this way, the subsequent capacitor units are arranged in the same manner as the first and third capacitor units when the capacitor units are arranged in the singular number, and in the same manner as the second and fourth capacitor units when the capacitor units are arranged in the even number. So that the first capacitor unit C1 to the mth capacitor unit Cm, one side of the laminated structure including the conductive layer/dielectric layer/conductive layer in each capacitor unit is formed in a stepped shape, and the other side of the laminated structure is formed in a shape like a ninety-degree rotated "convex", i.e., the side wall of the dielectric layer protrudes from the side walls of the upper and lower conductive layers thereof, at the other side of the laminated structure. The sides of adjacent capacitor cells forming the ladder shape are staggered. The conductive layer is selected from one or more alloys of doped polysilicon, titanium/titanium nitride, aluminum, tungsten, copper, nickel, gold, palladium, silver, platinum, rhodium, cobalt, tin and lead, the thickness of the conductive layer is between 1nm and 90000nm, and the specific thickness can be selected according to the actual requirement of a capacitor product so as to adjust characteristic parameters such as resistance, impedance, capacitive reactance, inductive reactance, frequency and the like. The dielectric layer is made of a material having a high dielectric constant, such as silicon dioxide, silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide, titanium oxide, or ruthenium oxide. The thickness of the dielectric layer is between 1nm and 90000nm, and the specific thickness can be selected according to the actual needs of the capacitor product and is used for adjusting voltage-withstanding parameters, leakage parameters, capacitance values and frequency parameters. Wherein the thicknesses of the dielectric layer and the conductive layer may be the same or different, and the materials of the dielectric layer and the conductive layer may have a high etching selectivity ratio.

Further, the structure of the opposite side walls between the adjacent capacitor banks is set to be mirror symmetric.

An insulating material 14 is formed on each side of each capacitor cell so that the insulating material is filled on the side wall of each conductive layer and also filled on the side wall of each dielectric layer, and since the projections of the side walls of the upper and lower conductive layers on the upper surface of the substrate overlap in the stacked structure on the capacitor cell side, the width of the insulating material is uniform on the side wall of the conductive layer on the capacitor cell side. The insulating material may be selected from materials having a high dielectric constant, such as silicon dioxide, silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide, titanium oxide, or ruthenium oxide. Wherein the width of the insulating material on each sidewall of the conductive layer is set between 10-300 nanometers and the width of the insulating material on each sidewall of the dielectric layer is set between 10-300 nanometers. The width of the insulating material on each sidewall of the conductive layer is greater than the width of the insulating material on each sidewall of the dielectric layer by a value in the range of 0-300. And the part of the dielectric layer, which protrudes out of the conductive layer, is coated by the insulating material. The insulation between adjacent capacitor cells may be increased by providing the insulating material on the dielectric and conductive layers. And a step surface formed by the upper surface of the part of the conducting layer, which is formed on one side of the step shape and is closer to the substrate, of the capacitor unit is not coated by an insulating material, so that an exposed step surface is formed.

It will be appreciated that the insulating material may be provided at the sidewalls of the conductive layer and at the sidewalls of the dielectric layer with the same width. It is preferred in the present disclosure to provide a greater width of insulating material at the sidewalls of the conductive layer than at the sidewalls of the dielectric layer. The setting of the bigger width of insulating material of lateral wall department of conducting layer more can improve the high voltage resistance ability of capacitor bank, and according to the high voltage resistant demand of capacitor bank, the numerical value setting of the width of insulating material of conducting layer department can carry out corresponding adjustment in the device manufacturing.

A dielectric layer is formed on the stacked structure, and the first and second planarized conductive structures 15 and 16 are filled between the adjacent capacitor banks. The first conductive structure 15 and the second conductive structure 16 are electrically connected to the surface of all or part of the conductive layer exposed at both sides of the capacitor bank and the first lower electrode and the second lower electrode formed on the lower surface of the silicon substrate, respectively. Through the connection of mode, the mode that the surface can all carry out the electricity and connect about constituting makes things convenient for the capacitor bank to carry out three-dimensional installation simultaneously, also will first and second conductive structure and the dielectric layer of the superiors, distance the nearest conducting layer of dielectric layer of the superiors constitutes the condenser together, and first and second bottom electrode, substrate, isolation layer, and distance the nearest conducting layer of substrate constitutes the condenser together. Through the arrangement of the first and second conductive structures, the positive and negative electrodes on the upper surface of the capacitor bank are integrated, so that the positive and negative electrodes do not need to be additionally prepared on the capacitor bank, and the process steps are simplified.

It will be understood by those skilled in the art that it is also possible to deposit a thin conductive material 17 only on the two side walls of the capacitor bank, separate and etch the conductive material so that the conductive material is electrically connected to the exposed surfaces of all or part of the conductive layer on the two sides of the capacitor bank, the first and second lower electrodes 12 and 13 formed on the lower surface of the silicon substrate, and the through holes 11 without filling the space between the adjacent capacitor banks, thereby depositing a planarized interlayer dielectric layer 18 between the adjacent capacitor banks, and forming through holes 19 on the interlayer dielectric layer and fabricating thereon a first upper electrode 21 and a second upper electrode 22, which serve as positive and negative electrodes, respectively, as shown in fig. 5.

It is understood by those skilled in the art that the first and second lower electrodes may not be formed on the lower surface of the substrate, and the substrate may be further peeled off to facilitate recycling of the substrate.

It is to be understood that the selection of the materials of the conductive layers, the materials of the dielectric layers and the insulating materials, and the thickness are specifically selected according to the specific parameter requirements of the capacitor, and the disclosure, although schematically illustrating the materials and thicknesses thereof, is not meant to be specifically limited thereto. The capacitor structure is arranged to realize easy voltage-resistant adjustment, easy control of product uniformity, low production cost and good packaging convenience. The capacitor structure can be widely applied to microcircuits with high reliability requirements, such as multi-chip packaging, communication base stations, electric automobiles, high-end medical treatment, optical communication, aerospace and the like, and has a very wide application market.

Second embodiment

Fig. 6 shows a second embodiment of the method for fabricating a semiconductor capacitor according to the present invention.

As shown in fig. 6, a silicon substrate is first provided, in which a plurality of through holes may be formed through, for example, a TSV process, and a conductive material is formed in the through holes by, for example, electroplating, physical vapor deposition, or chemical vapor deposition.

Forming a plurality of first lower electrodes and second lower electrodes on the lower surface of the silicon substrate, wherein the lower electrode material and the conductive material can be formed on the lower surface of the substrate through an etching process after being formed through an electroplating process; or the first and second lower electrodes may be formed by depositing a conductive material on the lower surface of the substrate and then forming the first and second lower electrodes through an etching process. The conductive material of the lower electrode may be the same as or different from the conductive material in the via.

It is understood that the above-mentioned fabrication of the through hole and the first and second lower electrodes in the substrate may not be performed.

Then, a step of forming an alternate stack is performed. Specifically, an isolation layer is deposited on the upper surface of the substrate, and then alternating stacks of conductive layers and dielectric layers are formed on the isolation layer, wherein the uppermost layer in the alternating stacks is the dielectric layer. The number of the conducting layers is M +1, the number of the dielectric layers is M +1, and M is the number of the capacitor units.

Then, a step of forming a stepwise alternate stack is performed. Specifically, a first photoresist layer is formed on the (M + 1) th dielectric layer farthest from the substrate, a part of the first photoresist layer is removed, then the alternating stack is etched by using the patterned photoresist layer to expose the (M) th conductive layer on one side and the (M + 1) th conductive layer on the other side, then the first photoresist layer is completely removed, and then a second photoresist layer is deposited, wherein the thickness of the second photoresist layer is thicker, and the coverage area of the alternating stack by the second photoresist layer is gradually reduced by gradually and transversely retracting the second photoresist layer toward the center of the second photoresist layer. And etching the alternating stack by using the second photoresist layer which is gradually reduced to form a stepped alternating stack, wherein partial upper surfaces of the conductive layers of the odd number layers are exposed at one side of the stepped alternating stack, and partial upper surfaces of the conductive layers of the even number layers are exposed at the other side of the stepped alternating stack.

Then, a step of forming a shaped alternating stack is performed. Specifically, the stepped alternating stack is then etched by wet etching, and since the materials of the conductive layer and the dielectric layer have a high etching selectivity, for example, the ratio of the etching selectivity is 2-1000 (2-1000), the conductive layer in the stepped alternating stack is laterally recessed but has little effect on the lateral direction of the dielectric layer in the wet etching process, thereby forming the shaped alternating stack. The shaped alternating lamination starts from the isolation layer, takes a conducting layer/a dielectric layer/a conducting layer as a group of capacitor units, one side of the capacitor units is in a step shape, and the other side of the capacitor units is in a convex shape which is formed by protruding the dielectric layer out of the upper conducting layer and the lower conducting layer and rotating by 90 degrees. The stepped shapes of the two sides of the adjacent capacitor units are distributed in a staggered mode.

Then, sidewall insulating the shaped alternating stack. Specifically, an insulating material is deposited on the shaped alternating stack using a thin film process, such as chemical vapor deposition CVD or atomic layer deposition ALD, such that the thickness of the insulating material formed on the sidewalls of the conductive layers is greater than the thickness of the insulating material formed on the sidewalls of the dielectric layers. And then removing the insulating material on the upper surfaces of the dielectric layer and the conducting layer by using a dry etching process.

And then, forming an electrical connection assembly. Specifically, a layer of top electrode material is formed between the plurality of shaped alternating stacks with sidewall insulation by a process such as electroplating or vapor deposition, the layer of top electrode material covering the capacitor banks and filling the voids between the capacitor banks. And then a planarization process planarizes the capacitor bank.

Finally, the first and second separated upper electrodes are formed by photoetching process. Finally, cutting is carried out to separate each capacitor bank, and it can be understood that, during cutting, each capacitor bank is not separated according to specific requirements, but a part of capacitor banks are electrically combined and then used as a module unit to be cut and separated.

It will be appreciated by those skilled in the art that the above-described process of forming electrical connection elements may be replaced by depositing an electrode conductive material layer on the plurality of shaped alternating stacks with insulated sidewalls and then forming discrete first and second electrode conductive material layers by a photolithographic etching process. Depositing an insulating material on the surface of the capacitor group, flattening the insulating material to form an interlayer dielectric layer, then forming a plurality of through holes in the interlayer dielectric layer through photoetching, filling conductive materials in the through holes to form interconnection, then performing separation etching on the capacitor group, depositing a passivation layer on a silicon chip after separation, further forming a plurality of first and second upper connecting electrodes on the passivation layer, further connecting the first upper connecting electrodes to the first electrode conductive material layer through corresponding interconnection, and connecting the second upper connecting electrodes to the second electrode conductive material layer through corresponding interconnection. And finally, cutting the silicon wafer to separate out each capacitor bank.

Third embodiment

An electronic device may include the capacitor in the above embodiments. The electronic devices are illustratively transimpedance amplifiers (TIAs), optical transceiver assemblies (ROSAs/TOSAs), synchronous Optical Networks (SONET), broadband test equipment, and the like.

The present invention has been described in connection with specific embodiments, but it should be clear to a person skilled in the art that these descriptions are intended to be illustrative and not limiting of the scope of the invention. Various modifications and adaptations of the invention will become apparent to those skilled in the art in light of the spirit and principles of the invention and are intended to be included within the scope of the invention.

Claims (9)

1. An electronic component, comprising:

a capacitor group in which a plurality of capacitor units are stacked, each of the capacitor units including a laminated structure of a conductive layer/a dielectric layer/a conductive layer;

a step-shaped structure is formed on one side of the capacitor unit, and partial surfaces of the conductive layer and the dielectric layer in the laminated structure are exposed to form a step surface;

on the other side of the capacitor unit, a structure is arranged in which the dielectric layer in the laminated structure protrudes out of the side walls of the adjacent upper and lower conductive layers;

one side of the capacitor units adjacent up and down to form a stepped structure is distributed in a staggered manner;

forming an insulating material on each sidewall of the capacitor cell; the width of the insulating material formed on the side wall of the dielectric layer is less than or equal to the width of the insulating material formed on the side wall of the conductive layer.

2. The electronic component according to claim 1, wherein a width of the insulating material formed on the side wall of the dielectric layer is smaller than a width of the insulating material formed on the side wall of the conductive layer by 0 to 300nm.

3. The electronic component of claim 1, wherein the structural arrangement of opposing sidewalls between adjacent capacitor banks is mirror symmetric.

4. The electronic component of claim 1, further comprising positive and negative electrode structures formed on an upper surface of the capacitor bank and/or positive and negative electrode structures formed on a lower surface of the capacitor bank.

5. The electronic component of claim 4, wherein the positive and negative electrode structures formed on the lower surface are formed on a surface of the substrate facing away from the capacitor bank.

6. The electronic component according to claim 5, wherein the partial surfaces of the conductive layers exposed at the corresponding sides of the capacitor units are connected in whole or in part by forming a conductive structure on both sidewalls of the capacitor bank.

7. The electronic component of claim 6, wherein the conductive structure fills between opposing sidewalls of adjacent capacitor banks and the conductive structure has a planar upper surface to integrate with positive and negative electrode structures of the upper surface.

8. The electronic component according to claim 6, wherein when positive and negative electrode structures are formed on both the upper and lower surfaces of the capacitor bank, the positive and negative electrode structures formed on the upper and lower surfaces of the capacitor bank are correspondingly connected by the conductive structure.

9. An electronic device comprising the electronic component of any one of claims 1-8.

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