CN117580444A

CN117580444A - Electronic element, electronic equipment and manufacturing method thereof

Info

Publication number: CN117580444A
Application number: CN202210938646.9A
Authority: CN
Inventors: 邵国望
Original assignee: Individual
Current assignee: Individual
Priority date: 2022-08-05
Filing date: 2022-08-05
Publication date: 2024-02-20

Abstract

The present disclosure relates to an electronic component, an electronic device, and a method of manufacturing the same, wherein the electronic component includes a capacitor group in which a plurality of capacitor units are stacked, each of the capacitor units including a stacked structure of a conductive layer/a dielectric layer/a conductive layer; forming a stepped structure on one side of the capacitor unit, and exposing a part of the surface of the conductive layer and a part of the surface of the dielectric layer in the laminated structure to form a stepped surface; on the other side of the capacitor unit, the dielectric layer in the laminated structure is arranged to protrude from the side wall of the adjacent upper and lower conductive layers; the capacitor units which are adjacent up and down form one side of the ladder-shaped structure to be distributed in a staggered way; forming an insulating material on each side of the capacitor unit; the width of the insulating material formed on the side wall of the dielectric layer is smaller than or equal to the width of the insulating material formed on the side wall of the conductive layer.

Description

Electronic element, electronic equipment and manufacturing method thereof

Technical Field

The present disclosure relates to integrated circuits and methods of manufacturing the same, and more particularly, to an electronic component and a method of manufacturing the same.

Background

With the development of integrated circuit manufacturing technology, integrated circuit manufacturing technology has been applied to the production and manufacture of micro-capacitor elements in the prior art. One type of micro-capacitor element commonly used in the market at present is mainly a Y-type three-dimensional capacitor represented by japan village field.

As shown in fig. 1, the Y-type three-dimensional capacitor adopts a photolithography technique to engrave a Y-type three-dimensional structure on a single substrate, for example, a wafer 1, and then a three-layer composite structure of an electrode/an insulating layer/an electrode is deposited and grown, and the surface area is increased by using a microstructure to realize a large capacitance. However, the Y-type three-dimensional capacitor 2 is generally completed by adopting a deep trench etching mode, and the deep trench cannot be etched too deeply due to the limitation of the capability of the existing integrated circuit manufacturing process, so that the requirement of high capacitance value in unit area is further limited; if the depth of the deep trench is too deep, uneven thickness of the top and the bottom of the deep trench and uneven peripheral and central positions of the wafer are caused, and the quality of products is affected; in addition, the thickness of the dielectric layer of the deep trench structure is limited, so that the requirement of high voltage is difficult to meet; in addition, the corners of the structure are more, so that the deposition growth of the thickness of the electrode plate is uneven, the accuracy of capacitance value of the capacitor is affected, in addition, the structure of the groove type capacitor is complex, the manufacture is complicated, individual Y fonts collapse during processing, the yield of finished products is affected, and the cost is greatly increased.

Fig. 2 shows another prior art. There is also a capacitor having a plurality of layers of conductive films 120 and dielectric films 121 alternately stacked on a wafer 110 by an integrated circuit process, an insulating layer 190 is formed on a sidewall of the capacitor, electrically connected through a conductive material layer 150, a conductive via 170 and an external electrode 130, and electrically connected through a conductive material layer 160, a conductive via 180 and another external electrode 140, wherein the conductive material layer 150, the conductive material layer 160, the conductive via 170 and the conductive via 180 are formed in a dielectric layer 210. The capacitor preparation of the prior art has smaller volume and higher density, and can reduce the manufacturing cost of the capacitor. However, the external electrode of the capacitor is prepared only on one side, which is inconvenient for three-dimensional expansion packaging, and in the semiconductor capacitor having a three-dimensional structure in which a plurality of conductive films and dielectric films are alternately stacked, there is also a problem in that withstand voltage adjustment is difficult. There is therefore a need for further improvements in the high voltage resistance of the semiconductor capacitor and in the flexibility of its packaging applications, based on reduced volume, increased capacity and reduced cost.

The present disclosure is directed to the above-mentioned technical problems, and designs a novel capacitor structure and manufacturing method, which not only can be compatible with the existing integrated circuit technology, and avoid the defects of bubbles, pinholes and the like in the existing chip type multilayer ceramic capacitor (MLCC) dielectric film, but also can further improve the high voltage resistance of the capacitor and the flexibility of the packaging application thereof on the basis of reducing the volume, improving the capacity and the reliability of the capacitor and reducing the cost.

Disclosure of Invention

A brief summary of the disclosure is provided below to provide a basic understanding of some aspects of the disclosure. It should be understood that this summary is not an exhaustive overview of the disclosure. It is not intended to identify key or critical elements of the disclosure or to delineate the scope of the disclosure. Its purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.

According to an aspect of the present disclosure, there is provided an electronic component including: a capacitor group formed by stacking a plurality of capacitor units, wherein each capacitor unit comprises a stacked structure of a conductive layer/a dielectric layer/a conductive layer; forming a stepped structure on one side of the capacitor unit, and exposing a part of the surface of the conductive layer and a part of the surface of the dielectric layer in the laminated structure to form a stepped surface; on the other side of the capacitor unit, the dielectric layer in the laminated structure is arranged to protrude from the side wall of the adjacent upper and lower conductive layers; adjacent capacitor units are staggered on one side of the ladder-shaped structure; forming an insulating material on each side of the capacitor unit; the width of the insulating material formed on the side wall of the dielectric layer is smaller than or equal to the width of the insulating material formed on the side wall of the conductive layer.

Further, the width of the insulating material formed on the side wall of the dielectric layer is 0-300nm smaller than the width of the insulating material formed on the side wall of the conductive layer.

Further, wherein the arrangement of opposite sides between adjacent ones of said capacitor banks is mirror symmetrical.

Further, positive and negative electrode structures formed on the upper surface of the capacitor bank and/or positive and negative electrode structures formed on the lower surface of the capacitor bank are included.

Further, wherein positive and negative electrode structures formed on the lower surface are formed on a surface of the substrate facing away from the capacitor bank.

Further, part of the surface of the conductive layer exposed at the corresponding side of all or part of the capacitor cells is connected by forming conductive structures on both sidewalls of the capacitor bank, respectively.

Further, wherein the conductive structure fills between opposite sides of adjacent ones of the capacitor banks and has a planar upper surface to be integral with positive and negative electrode structures of the upper surface.

Further, when positive and negative electrode structures are formed on both upper and lower surfaces of the capacitor bank, the positive and negative electrode structures formed on the upper and lower surfaces of the capacitor bank are correspondingly connected through the conductive structures.

According to another aspect of the present disclosure, there is provided a method of manufacturing an electronic component, including: providing a substrate; alternating stacks of conductive and dielectric layers formed on the substrate; forming a first photoresist layer on the alternating stack, patterning the first photoresist layer and then etching to expose an outermost conductive layer on one side of the alternating stack and a next outermost conductive layer on the other side of the alternating stack; removing the first photoresist layer, then depositing a second photoresist layer, and forming a step-type alternate lamination on the alternate lamination by gradually transversely retracting the second photoresist layer; one side of the step-type alternate lamination exposes part of the upper surface of the conductive layer of the odd layer, and the other side of the step-type alternate lamination exposes part of the upper surface of the conductive layer of the even layer; wet etching is carried out to transversely retract the conductive layers at two sides of the step-type alternate lamination so as to form a shaped alternate lamination; and depositing an insulating material on the shaped alternating stack so that the width of the insulating material formed on the sidewalls of the dielectric layer is less than or equal to the width of the insulating material formed on the sidewalls of the conductive layer.

Further, the method comprises the step of etching to remove insulating materials on the upper surfaces of the dielectric layer and the conductive layer to form a side wall insulating alternating structure.

Further, including forming a discrete planarized conductive material on both sides of the sidewall-insulated alternating structure.

Further, the method also comprises forming a through hole in the substrate and forming positive and negative electrode structures on the lower surface of the substrate.

According to still another aspect of the present disclosure, there is provided an electronic device including the electronic element of any one of the above.

Aspects of the present disclosure can help achieve at least one of the following effects: the manufacturing process is simple, the pressure resistance adjustment is easy, the uniformity of the product is easy to control, the capacitance is precise, the service life of the device is long, the reliability is good, the device is suitable for various severe environments, the production cost is low, and the packaging convenience is good.

Drawings

The above and other objects, features and advantages of the present disclosure will be more readily appreciated by reference to the following description of the specific details of the disclosure taken in conjunction with the accompanying drawings. The drawings are only for the purpose of illustrating the principles of the present disclosure. The dimensions and relative positioning of the elements in the figures are not necessarily drawn to scale.

FIGS. 1-2 show schematic diagrams of prior art capacitor structures;

figures 3-5 illustrate a first embodiment of a capacitor structure of the present disclosure;

fig. 6 shows a second embodiment of a method of fabricating a capacitor structure of the present disclosure

Detailed Description

Exemplary disclosure of the present disclosure will be described hereinafter with reference to the accompanying drawings. In the interest of clarity and conciseness, not all features of an implementation of the present disclosure are described in the specification. However, it will be appreciated that numerous implementation-specific decisions may be made in the development of any such actual implementation of the present disclosure, in order to achieve the developer's specific goals, and that these decisions may vary from one implementation to another.

It should be further noted that, in order to avoid obscuring the present disclosure due to unnecessary details, only device structures closely related to the scheme according to the present disclosure are shown in the drawings, while other details not greatly related to the present disclosure are omitted.

It is to be understood that the present disclosure is not limited to the described embodiments due to the following description with reference to the drawings. Herein, features between different embodiments may be substituted or borrowed where possible, and one or more features may be omitted in one embodiment.

First embodiment

Fig. 3-5 illustrate a first embodiment of a semiconductor capacitor structure of the present disclosure, wherein like reference numerals refer to like parts.

Fig. 3 is a top view of the structure of the present embodiment. As can be seen from fig. 3, N capacitor banks 20 (two capacitor banks are exemplarily shown in the figure) are formed on a substrate 10 in a spaced arrangement, where N is a natural number. For example, N may be set to 5000 groups, but it will be understood by those skilled in the art that the number of the capacitor groups may be flexibly set according to actual needs, which is not particularly limited in the present disclosure. The substrate may be, for example: a single crystal/polycrystalline silicon substrate (Si), a silicon-on-insulator Substrate (SOI), a compound substrate of a group III-V element, a glass substrate, a ceramic substrate, or the like may be used as a substrate material compatible with the semiconductor process, and a silicon substrate will be described below as an example.

Fig. 4 is a cross-sectional view taken along the direction A-A in fig. 3. As can be seen from fig. 4, a plurality of through holes 11 are formed in the silicon substrate, and the through holes are filled with a conductive material, which may be selected from one or more alloys of heavily doped polysilicon, titanium/titanium nitride, aluminum, tungsten, copper, nickel, gold, palladium, silver, platinum, rhodium, cobalt, tin, lead. A plurality of first electrodes 12 and second electrodes 13 are formed on the lower surface of the silicon substrate, which will serve as positive and negative electrodes of the capacitor, respectively. An isolation layer (not shown) may be deposited on the upper surface of the substrate. The isolation layer may be a material having a high dielectric constant, such as a silicon oxide layer, a silicon oxide/silicon nitride/silicon oxide layer, hafnium oxide, aluminum oxide, zirconium oxide, titanium oxide, or ruthenium oxide, and the thickness of the isolation layer may be, for example, between 100nm and 500 nm.

Each of the capacitor groups 20 includes M stacked capacitor cells, where M is a natural number. For example, M may be set to 128, but it will be understood by those skilled in the art that the number of the capacitor units may be flexibly set according to actual needs, which is not particularly limited in the present disclosure. Each capacitor cell is a stacked structure of conductive layers/dielectric layers/conductive layers, with a common conductive layer between adjacent capacitor cells.

Specifically, the capacitor cell stacked in the capacitor group is defined as a first capacitor cell C1 nearest to the substrate, a second capacitor cell C2 next farthest from the substrate, and an mth capacitor cell Cm. The first capacitor unit is composed of a first conductive layer LC 1/a first dielectric layer LD 1/a second conductive layer LC 2. The projection of the first side wall of the first conductive layer and the projection of the first side wall of the second conductive layer on the upper surface of the substrate are overlapped, and the projection of the second side wall of the first conductive layer and the projection of the second side wall of the second conductive layer on the upper surface of the substrate are not overlapped. In particular, the projection of the second sidewall of the second conductive layer falls within the projection of the first conductive layer on the upper surface of the substrate.

The projection of the first side wall of the first conductive layer on the upper surface of the substrate falls within the projection range of the first dielectric layer on the upper surface of the substrate. The projection of the second side wall of the first dielectric layer on the upper surface of the substrate falls within the projection range of the first conductive layer on the upper surface of the substrate.

The projections of the first and second sidewalls of the second conductive layer onto the upper surface of the substrate are within the projection of the first dielectric layer onto the upper surface of the substrate. So that the first capacitor unit is formed in a stepped shape at a second side thereof, a step surface of the stepped shape being formed by a part of an upper surface of the first conductive layer protruding from the second side wall of the first dielectric layer and by a part of an upper surface of the first dielectric layer protruding from the second side wall of the second conductive layer, respectively.

The second capacitor unit is composed of a second conductive layer LC 2/a second dielectric layer LD 2/a third conductive layer LC 2. The second side wall of the second conductive layer is overlapped with the projection of the second side wall of the third conductive layer on the upper surface of the substrate, and the projection of the first side wall of the second conductive layer and the projection of the first side wall of the third conductive layer on the upper surface of the substrate are not overlapped. Specifically, the projection of the first sidewall of the third conductive layer falls within the projection of the second conductive layer on the upper surface of the substrate, and the projection of the first sidewall of the second dielectric layer falls within the projection of the second conductive layer on the upper surface of the substrate.

The projection of the second side wall of the second conductive layer on the upper surface of the substrate falls within the projection range of the second dielectric layer on the upper surface of the substrate. The projection of the first side wall of the second dielectric layer on the upper surface of the substrate falls within the projection range of the second conductive layer on the upper surface of the substrate.

The projections of the first and second sidewalls of the third conductive layer onto the upper surface of the substrate are within the projection of the second dielectric layer onto the upper surface of the substrate. So that the second capacitor unit is formed in a stepped shape at a first side thereof, a step surface of the stepped shape being formed by a part of an upper surface of the second conductive layer protruding from the first side wall of the second dielectric layer and by a part of an upper surface of the second dielectric layer protruding from the first side wall of the third conductive layer, respectively.

The third capacitor unit is composed of a third conductive layer/a third dielectric layer/a fourth conductive layer. The conductive layer/dielectric layer/conductive layer of the third capacitor unit is arranged in the same manner as the first capacitor unit. The projection of the first side wall of the third conductive layer and the projection of the first side wall of the fourth conductive layer on the upper surface of the substrate are overlapped, and the projection of the second side wall of the third conductive layer and the projection of the second side wall of the fourth conductive layer on the upper surface of the substrate are not overlapped. In particular, the projection of the second sidewall of the fourth conductive layer falls within the projection of the third conductive layer on the upper surface of the substrate.

The projection of the first side wall of the third conductive layer on the upper surface of the substrate falls within the projection range of the third dielectric layer on the upper surface of the substrate. The projection of the second side wall of the third dielectric layer on the upper surface of the substrate falls within the projection range of the third conductive layer on the upper surface of the substrate.

The projections of the first and second sidewalls of the fourth conductive layer onto the upper surface of the substrate are within the projection of the third dielectric layer onto the upper surface of the substrate.

The fourth capacitor unit is composed of a fourth conductive layer/a fourth dielectric layer/a fifth conductive layer. The conductive layer/dielectric layer/conductive layer of the fourth capacitor unit is arranged in the same manner as the second capacitor unit.

The second side wall of the fourth conductive layer is overlapped with the projection of the second side wall of the fifth conductive layer on the upper surface of the substrate, and the projection of the first side wall of the fourth conductive layer and the projection of the first side wall of the fifth conductive layer on the upper surface of the substrate are not overlapped. Specifically, the projection of the first sidewall of the fifth conductive layer falls within the projection of the fourth conductive layer on the upper surface of the substrate, and the projection of the first sidewall of the fourth dielectric layer falls within the projection of the fourth conductive layer on the upper surface of the substrate.

The projection of the second side wall of the fourth conductive layer on the upper surface of the substrate falls within the projection range of the fourth dielectric layer on the upper surface of the substrate. The projection of the first side wall of the fourth dielectric layer on the upper surface of the substrate falls within the projection range of the fourth conductive layer on the upper surface of the substrate.

The projections of the first and second sidewalls of the fifth conductive layer on the upper surface of the substrate are within the projection of the fourth dielectric layer on the upper surface of the substrate.

Similarly, the subsequent capacitor units are arranged in the same manner as the first and third capacitor units when they are ordered in the singular, and in the same manner as the second and fourth capacitor units when they are ordered in the even number. So that the first capacitor unit C1 up to the mth capacitor unit Cm, one side of the stacked structure including the conductive layer/dielectric layer/conductive layer in each capacitor unit forms a step shape, and the other side of the stacked structure forms a 'convex' shape similar to a ninety degree rotation, i.e. the side wall of the dielectric layer protrudes from the side walls of the upper and lower conductive layers on the other side of the stacked structure. The sides of adjacent capacitor units forming the steps are staggered. The conductive layer is one or more alloys selected from doped polysilicon, titanium/titanium nitride, aluminum, tungsten, copper, nickel, gold, palladium, silver, platinum, rhodium, cobalt, tin and lead, the thickness of the conductive layer is between 1nm and 90000nm, and the specific thickness can be selected according to the actual requirement of a capacitor product and is used for adjusting characteristic parameters such as resistance, impedance, capacitance, inductance and frequency. The material of the dielectric layer is selected from silicon dioxide, silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide, titanium oxide or ruthenium oxide and other materials with high dielectric constants. The thickness of the dielectric layer is between 1nm and 90000nm, and the specific thickness can be selected according to the actual requirement of a capacitor product and is used for adjusting withstand voltage parameters, leakage parameters, capacitance values and frequency parameters. Wherein the thicknesses of the dielectric layer and the conductive layer may be the same or different, and the materials of the dielectric layer and the conductive layer may have a high etching selectivity.

Further, the structures of the opposite side walls between the adjacent capacitor banks are arranged in mirror symmetry.

An insulating material 14 is formed on each side of each of the capacitor units so that the insulating material is filled in the side wall of each of the conductive layers, and the insulating material is also filled in the side wall of each of the dielectric layers, and since projections of the side walls of the upper and lower conductive layers on the upper surface of the substrate overlap in the laminated structure on one side of the capacitor unit, widths of the insulating material on the side walls of the conductive layers on the one side of the capacitor unit are uniform. The insulating material may be selected from materials having a high dielectric constant such as silicon dioxide, silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide, titanium oxide, or ruthenium oxide. Wherein the width of the insulating material on each sidewall of the conductive layer is set between 10-300 nanometers and the width of the insulating material on each sidewall of the dielectric layer is set between 10-300 nanometers. The width of the insulating material on each side wall of the conductive layer is greater than the width of the insulating material on each side wall of the dielectric layer, and the value range is 0-300. And further, the portions of the dielectric layer protruding from the conductive layer are covered with the insulating material. The insulation between adjacent capacitor cells may be increased by providing the insulating material on the dielectric layer and the conductive layer. The step surface formed on the upper surface of the portion of the conductive layer closer to the substrate forming the step side in the capacitor unit is not covered with the insulating material, and an exposed step surface is formed.

It will be appreciated that insulating material of the same width may be provided at the sidewalls of the conductive layer and at the sidewalls of the dielectric layer. It is preferred in the present disclosure to provide an insulating material at the sidewalls of the conductive layer that is wider than the width at the sidewalls of the dielectric layer. The setting of the larger width of the insulating material at the side wall of the conductive layer can improve the high voltage resistance of the capacitor bank, and according to the high voltage resistance requirement of the capacitor bank, the numerical setting of the width of the insulating material at the conductive layer can be adjusted correspondingly in the device manufacturing.

A dielectric layer is formed over the stacked structure and adjacent capacitor banks are filled with discrete planarized first and second conductive structures 15 and 16. The first and second conductive structures 15 and 16 are electrically connected to all or part of the surface of the conductive layer exposed at both sides of the capacitor bank, and the first and second lower electrodes formed on the lower surface of the silicon substrate, respectively. By the connection, the upper surface and the lower surface can be electrically connected, the three-dimensional installation of the capacitor bank is facilitated, the first conductive structure, the second conductive structure, the uppermost dielectric layer, the conductive layer closest to the uppermost dielectric layer, the first lower electrode, the second lower electrode, the substrate, the isolation layer and the conductive layer closest to the substrate form a capacitor together. By arranging the first conductive structure and the second conductive structure, the positive electrode and the negative electrode on the upper surface of the capacitor bank are integrated, so that the positive electrode and the negative electrode do not need to be additionally prepared on the capacitor bank, and the process steps are simplified.

It will be understood by those skilled in the art that it is also possible to deposit a thinner conductive material 17 on only both sidewalls of the capacitor bank, separate etching, so that the conductive material is electrically connected to all or part of the surface of the conductive layer exposed on both sides of the capacitor bank, the first and second lower electrodes 12 and 13 formed on the lower surface of the silicon substrate, the via 11 without filling the space between the adjacent capacitor banks, thereby depositing a planarized interlayer dielectric layer 18 between the adjacent capacitor banks, and forming a via 19 on the interlayer dielectric layer and forming first and second upper electrodes 21 and 22 serving as positive and negative electrodes thereon, respectively.

It will be appreciated by those skilled in the art that the fabrication of the first and second lower electrodes may not be performed on the lower surface of the substrate, and the substrate may be further peeled off later to facilitate recycling of the substrate.

It will be appreciated that the choice of materials for each conductive layer, the choice of materials for each dielectric layer and the choice of insulating materials, and the arrangement of thicknesses are specifically chosen according to the specific parameter requirements of the capacitor, and the disclosure is not meant to be limited in any way by the schematic illustrations of materials and thicknesses. The capacitor structure is mainly arranged to realize easy voltage resistance adjustment, easy control of product uniformity, low production cost and good packaging convenience. The capacitor structure disclosed by the invention can be widely applied to miniature circuits with high reliability requirements such as multi-chip packaging, communication base stations, electric automobiles, high-end medical treatment, optical communication, aerospace and the like, and has very wide application market.

Second embodiment

Fig. 6 illustrates a second embodiment of a method of fabricating a semiconductor capacitor of the present disclosure.

As shown in fig. 6, a silicon substrate is first provided, in which a plurality of through holes may be formed by, for example, a TSV process, and a conductive material is formed in the through holes by, for example, electroplating, physical vapor phase, or chemical vapor deposition.

Forming a plurality of first lower electrodes and second lower electrodes on the lower surface of the silicon substrate, wherein the lower electrode material and the conductive material can be formed on the lower surface of the substrate through an electroplating process and then through an etching process; or the first and second lower electrodes may be deposited with a conductive material on the lower surface of the substrate, and then the first and second lower electrodes may be formed through an etching process. The conductive material of the lower electrode may be the same as or different from the conductive material in the via hole.

It will be appreciated that the above-described fabrication of the via and the first and second lower electrodes in the substrate may not be performed.

Then, a step of forming an alternate stack is performed. Specifically, an isolation layer is deposited on the upper surface of the substrate, and then an alternating stack of conductive layers and dielectric layers is formed on the isolation layer, wherein the uppermost layer in the alternating stack is the dielectric layer. The number of the conductive layers is M+1, the number of the dielectric layers is M+1, and M is the number of the capacitor units.

Then, a step-type alternate lamination process is performed. Specifically, a first photoresist layer is formed on an M+1th dielectric layer farthest from the substrate, a portion of the first photoresist layer is removed, then the alternating stack is etched by using the patterned photoresist layer to expose the M-th conductive layer on one side and the M+1th conductive layer on the other side, then the first photoresist layer is completely removed, and then a second photoresist layer is deposited, wherein the second photoresist layer is thicker, and the coverage area of the second photoresist layer on the alternating stack is gradually reduced by gradually retracting the second photoresist layer laterally toward the center of the second photoresist layer. And etching the alternate lamination by using the successively reduced second photoresist layers to form a step-shaped alternate lamination, wherein part of the upper surface of the conductive layer of the odd layer is exposed at one side of the step-shaped alternate lamination, and part of the upper surface of the conductive layer of the even layer is exposed at the other side of the step-shaped alternate lamination.

Then, a step of forming a shaped alternating laminate is performed. Specifically, the stepped alternating stack is then etched by wet etching, whereby the conductive layers in the stepped alternating stack are laterally indented but have little lateral influence on the dielectric layers during the wet etching process due to the high etch selectivity of the materials of the conductive layers and the dielectric layers, e.g. the etch selectivity ratio is between 2-1000 (2-1000), thereby forming the shaped alternating stack. The shaped alternating lamination starts from the isolation layer, takes the conductive layer/dielectric layer/conductive layer as a group of capacitor units, has a step shape on one side and has a similar convex shape with the dielectric layer protruding above and below the conductive layer and rotating by 90 degrees on one side. The stepped shapes of the two sides of adjacent capacitor units are staggered.

And then, insulating the side wall to form the shaped alternating lamination. Specifically, an insulating material is deposited on the shaped alternating stack using a thin film process, such as chemical vapor deposition CVD or atomic layer deposition ALD, such that the thickness of the insulating material formed on the sidewalls of the conductive layer is greater than the thickness of the insulating material formed on the sidewalls of the dielectric layer. And then removing insulating materials on the upper surfaces of the dielectric layer and the conducting layer by using a dry etching process.

And then, forming an electrical connection assembly. Specifically, an upper electrode material layer is formed between the plurality of shaped alternating stacks with insulated sidewalls by a process such as electroplating or vapor deposition, the upper electrode material layer covering the capacitor banks and filling the gaps between the capacitor banks. And then planarizing the capacitor bank.

Finally, the first and second upper electrodes are formed separately by a photolithography etching process. Finally, cutting is performed to separate each capacitor bank, and it is understood that when cutting, each capacitor bank can be cut and separated as a module unit after a part of capacitor banks are electrically combined without separating each capacitor bank according to specific requirements.

It will be appreciated by those skilled in the art that the process of forming the electrical connection assembly described above may be replaced by depositing a layer of electrode conductive material on the plurality of shaped alternating stacks of insulated sidewalls and then forming separate layers of first and second electrode conductive material by a photolithographic etching process. Depositing an insulating material on the insulating material and flattening the insulating material to form an interlayer dielectric layer, forming a plurality of through holes in the interlayer dielectric layer through photoetching, filling conductive materials in the through holes to form interconnection, separating and etching the capacitor bank, depositing a passivation layer on the separated silicon wafer, and further forming a plurality of first upper connecting electrodes and second upper connecting electrodes on the passivation layer, wherein the first upper connecting electrodes are connected to the first electrode conductive material layer through corresponding interconnection, and the second upper connecting electrodes are connected to the second electrode conductive material layer through corresponding interconnection. And finally, cutting the silicon wafer, and separating each capacitor group.

Third embodiment

An electronic device may include the capacitor of the above embodiment. The electronic devices are illustratively transimpedance amplifiers (TIAs), optical transceiver components (ROSAs/TOSAs), synchronous Optical Networks (SONET), broadband test equipment, etc.

The present disclosure has been described in connection with specific embodiments, but it should be apparent to those skilled in the art that the description is intended to be exemplary, and not limiting, of the scope of the disclosure. Various modifications and alterations of this disclosure may be made by those skilled in the art in light of the spirit and principles of this disclosure, and such modifications and alterations are also within the scope of this disclosure.

Claims

1. An electronic component, comprising:

a capacitor group formed by stacking a plurality of capacitor units, wherein each capacitor unit comprises a stacked structure of a conductive layer/a dielectric layer/a conductive layer;

forming a stepped structure on one side of the capacitor unit, and exposing a part of the surface of the conductive layer and a part of the surface of the dielectric layer in the laminated structure to form a stepped surface;

on the other side of the capacitor unit, a dielectric layer in the laminated structure protrudes from the side wall of the adjacent upper and lower conductive layers;

the capacitor units which are adjacent up and down form one side of the ladder-shaped structure to be distributed in a staggered way;

forming an insulating material on each sidewall of the capacitor unit; the width of the insulating material formed on the side wall of the dielectric layer is smaller than or equal to the width of the insulating material formed on the side wall of the conductive layer.

2. The electronic component of claim 1, wherein a width of the insulating material formed on the sidewalls of the dielectric layer is 0-300nm smaller than a width of the insulating material formed on the sidewalls of the conductive layer.

3. The electronic component of claim 1, wherein the arrangement of opposing sidewalls between adjacent ones of the capacitor banks is mirror symmetrical.

4. The electronic component of claim 1, further comprising positive and negative electrode structures formed on an upper surface of the capacitor bank and/or positive and negative electrode structures formed on a lower surface of the capacitor bank.

5. The electronic component of claim 4, wherein positive and negative electrode structures formed on the lower surface are formed on a surface of the substrate facing away from the capacitor bank.

6. The electronic component of claim 5, wherein a portion of the surface of the conductive layer exposed at the corresponding side of the capacitor unit is connected in whole or in part, respectively, by forming conductive structures on both sidewalls of the capacitor bank.

7. The electronic component of claim 6, wherein the conductive structures fill between opposing sidewalls of adjacent ones of the capacitor banks and have a planar upper surface to integrate with positive and negative electrode structures of the upper surface.

8. The electronic component as claimed in claim 6, wherein when positive and negative electrode structures are formed on both upper and lower surfaces of the capacitor bank, the positive and negative electrode structures formed on the upper and lower surfaces of the capacitor bank are correspondingly connected by the conductive structure.

9. A method of manufacturing an electronic component, comprising:

providing a substrate;

alternating stacks of conductive and dielectric layers formed on the substrate;

photoetching and etching the alternating lamination to form a stepped alternating lamination;

one side of the step-type alternate lamination exposes part of the upper surface of the conductive layer of the odd layer, and the other side of the step-type alternate lamination exposes part of the upper surface of the conductive layer of the even layer;

etching to transversely retract the conductive layers at both sides of the stepped alternating stack to form a shaped alternating stack;

an insulating material is deposited over the shaped alternating stack such that a width of the insulating material formed on the sidewalls of the dielectric layer is less than or equal to a width of the insulating material formed on the sidewalls of the conductive layer.

10. The method of claim 9, further comprising etching away insulating material from the dielectric layer and the upper surface of the conductive layer to form a sidewall-insulated alternating structure.

11. The method of manufacturing of claim 10, further comprising forming a discrete planarized conductive material on both sides of the sidewall insulated alternating structure.

12. The manufacturing method according to any one of claims 9 to 11, further comprising forming a through hole in the substrate, and forming positive and negative electrode structures on a lower surface of the substrate.

13. An electronic device comprising the electronic component of any one of claims 1-12.