CN218447948U - Semiconductor light emitting element - Google Patents
Semiconductor light emitting element Download PDFInfo
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- CN218447948U CN218447948U CN202222530314.5U CN202222530314U CN218447948U CN 218447948 U CN218447948 U CN 218447948U CN 202222530314 U CN202222530314 U CN 202222530314U CN 218447948 U CN218447948 U CN 218447948U
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Abstract
The utility model provides a semiconductor light-emitting element, it is supreme including in proper order down: the semiconductor device comprises a substrate, an n-type semiconductor layer, a quantum well layer and a p-type semiconductor layer, wherein a part of the n-type semiconductor layer and a part of the quantum well layer form an n-type space charge region, a part of the p-type semiconductor layer forms a p-type space charge region, and the width of the n-type space charge region is larger than that of the p-type space charge region. The utility model discloses a setting that the width in n type space charge district is greater than the width in p type space charge district can improve semiconductor light emitting element's ageing light decay performance.
Description
Technical Field
The utility model relates to the field of semiconductor technology, in particular to semiconductor light-emitting element.
Background
The semiconductor light-emitting element has the advantages of wide wavelength range adjustable range, high light-emitting efficiency, energy conservation, environmental protection, long service life, small size, strong designability and the like, has gradually replaced incandescent lamps and fluorescent lamps to become light sources for common household illumination, and is widely applied to new scenes, such as Mini-LEDs, indoor high-resolution display screens, outdoor display screens, mobile phone backlight, television backlight, notebook computer backlight, household lamps, street lamps, car lamps, flashlights and the like.
However, the conventional nitride semiconductor light emitting device generally uses heteroepitaxy to grow on a sapphire substrate, and the lattice mismatch and thermal mismatch between sapphire and a nitride semiconductor are large, so that high defect density and polarization effect are generated, the lattice quality is poor, and aging light decay is easily caused; further, si element of the quantum well layer and Mg element of the p-type semiconductor layer are likely to be mixed by element migration and diffusion at high temperature or in long-term use, and cause an aging light attenuation phenomenon, and the aging light attenuation of 1000H is generally 30% or more, even 50% or more.
SUMMERY OF THE UTILITY MODEL
An object of the present invention is to provide a semiconductor light emitting device to improve the aging light attenuation performance of the semiconductor light emitting device.
In order to achieve the above objects and other related objects, the present invention provides a semiconductor light emitting device, which comprises: the semiconductor device comprises a substrate, an n-type semiconductor layer, a quantum well layer and a p-type semiconductor layer, wherein a part of the n-type semiconductor layer and a part of the quantum well layer form an n-type space charge region, a part of the p-type semiconductor layer forms a p-type space charge region, and the width of the n-type space charge region is larger than that of the p-type space charge region.
Optionally, in the semiconductor light emitting element, the semiconductor light emitting element further includes an undoped structure layer, and the undoped structure layer is located between the quantum well layer and the p-type semiconductor layer.
Optionally, in the semiconductor light emitting element, the thickness of the undoped structure layer is 0.5nm to 20nm.
Optionally, in the semiconductor light emitting element, the quantum well layer, the undoped structure layer and the p-type semiconductor layer between the p-type space charge region and the n-type space charge region form a pn space charge region, and the increase value of the width of the pn space charge region after aging for 0 hour and 1000 hours is a, and a is less than or equal to 10nm.
Optionally, in the semiconductor light emitting element, the pn space charge region has a width d after aging for 0 hour, and d is less than or equal to 50nm.
Optionally, in the semiconductor light emitting element, the pn space charge region has a width e after aging for 1000 hours, and e is less than or equal to 60nm.
Optionally, in the semiconductor light emitting element, the pn space charge region occupies 5% or less of the quantum well layer.
Alternatively, in the semiconductor light emitting element, the pn space charge region occupies 5% or less of the p-type semiconductor layer.
Optionally, in the semiconductor light emitting element, the n-type space charge region occupies 95% or more of the quantum well layer.
Optionally, in the semiconductor light emitting element, the n-type space charge region occupies 5% or more of the n-type semiconductor layer.
Optionally, in the semiconductor light emitting element, the p-type space charge region occupies 5% or more of the p-type semiconductor layer.
Optionally, in the semiconductor light emitting element, the n-type semiconductor layer, the quantum well layer, and the p-type semiconductor layer are made of one of GaN, alGaN, inGaN, alInGaN, alN, inN, and AlInN.
Compared with the prior art, the technical scheme of the utility model following beneficial effect has:
the utility model provides a semiconductor light emitting component is from supreme including down: the semiconductor device comprises a substrate, an n-type semiconductor layer, a quantum well layer and a p-type semiconductor layer, wherein a part of the n-type semiconductor layer and a part of the quantum well layer form an n-type space charge region, a part of the p-type semiconductor layer forms a p-type space charge region, and the width of the n-type space charge region is larger than that of the p-type space charge region. The utility model discloses a width that sets up n type space charge district is greater than p type space charge district, can reduce the width in pn space charge district and improve semiconductor light emitting element's ageing light decay performance at the increment value of ageing 0 hours and 1000 hours's width.
The utility model discloses a set up the width in n type space charge district is greater than p type space charge district, and through set up the non-doping structural layer between quantum well layer and p type semiconductor layer, can with the width in pn space charge district increases no more than 10nm at ageing 0 hours and 1000 hours's width to guarantee that semiconductor light emitting element is less than 10% at 1000 hours's ageing light attenuation, can be less than 5% even.
Drawings
Fig. 1 is a schematic structural diagram of a semiconductor light emitting device according to an embodiment of the present invention;
fig. 2 is a flowchart illustrating a method for manufacturing a semiconductor light emitting device according to an embodiment of the present invention;
in the figures 1-2 of the drawings,
11-substrate, 12-n type semiconductor layer, 13-quantum well layer, 14-p type semiconductor layer, 101-n type space charge region, 102-pn space charge region, 103-p type space charge region.
Detailed Description
The semiconductor light emitting element according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are not to precise scale, which is only used for the purpose of facilitating and clearly explaining the embodiments of the present invention.
Referring to fig. 1, the present invention provides a semiconductor light emitting device, which comprises from bottom to top in sequence: a substrate 11, an n-type semiconductor layer 12, a quantum well layer 13, and a p-type semiconductor layer 14, wherein a portion of the n-type semiconductor layer and a portion of the quantum well layer form an n-type space charge region 101, and a portion of the p-type semiconductor layer forms a p-type space charge region 103.
In the present embodiment, the width of the n-type space charge region 101 is greater than the width of the p-type space charge region 103 to improve the aged light decay performance of the semiconductor light emitting element. The n-type semiconductor layer 12 and the quantum well layer 13 form an n-type space charge region 101 by doping an n-type doping element. The p-type semiconductor layer 14 forms a p-type space charge region 103 by doping a p-type doping element. This embodiment can realize that the width of the n-type space charge region 101 is larger than that of the p-type space charge region 103 by controlling the activation energy difference of the n-type doping element and the p-type doping element. In order to ensure that the width of the n-type space charge region 101 is greater than the width of the p-type space charge region 103, the activation energy of the n-type doping element in the n-type semiconductor layer 12 is b, preferably b ≤ 25meV, the activation energy of the n-type doping element in the quantum well layer 13 is f, preferably f ≤ 25meV, and the activation energy of the p-type doping element is c, preferably c ≥ 50meV.
In the present embodiment, the n-type space charge region 101 preferably occupies 95% or more of the quantum well layer 13, and preferably occupies 5% or more of the n-type semiconductor layer 12. The p-type space charge region 103 preferably occupies 5% or more of the p-type semiconductor layer 14.
The quantum well layer 13 and the p-type semiconductor layer 14 between the p-type space charge region 103 and the n-type space charge region 101 form a pn space charge region 102. The pn space charge region 102 preferably occupies 5% or less of the quantum well layer 13, and preferably occupies 5% or less of the p-type semiconductor layer 14.
In other embodiments, the semiconductor light emitting element may further include a non-doped structure layer, and the non-doped structure layer is located between the quantum well layer 13 and the p-type semiconductor layer 14. The quantum well layer 13, the undoped structure layer, and the p-type semiconductor layer 14 between the p-type space charge region 103 and the n-type space charge region 101 in this embodiment form a pn space charge region. The arrangement of the undoped structure layer can enable the width of the p-type space charge region 103 to be increased by no more than 10nm before and after aging. The inventors have studied and found that when the width of the p-type space charge region 103 before and after aging increases by not more than 10nm, the semiconductor light emitting element can maintain a good light attenuation level. Therefore, the arrangement of the non-doped structure layer can further improve the aging light attenuation performance of the semiconductor light-emitting element.
Further, the width of the pn space charge region 102 increases by a value of a at 0 hours and 1000 hours of aging, and preferably a.ltoreq.10 nm. Still further, the pn space charge region has a width d after aging for 0 hour, and preferably d.ltoreq.50 nm; the pn space-charge region has a width e after 1000 hours of aging, and preferably e ≦ 60nm. The thickness of the non-doped structural layer is preferably 0.5 nm-20 nm. In this embodiment, by inserting the undoped structure layer between the quantum well layer 13 and the p-type semiconductor layer 14, the p-type doped element and the n-type doped element can be spatially isolated, so that the p-type doped element and the n-type doped element are prevented from being in contact with each other by diffusion in the aging process, and the aging light decay performance of the semiconductor light emitting element is improved; meanwhile, the defect density and defect extension of the n-type semiconductor layer 12 can be reduced, the crystal quality and the steepness of a well barrier interface of the quantum well layer 13 are improved, and the aging light attenuation performance of the semiconductor light-emitting element is further improved.
Referring to fig. 2, the method for manufacturing the semiconductor light emitting device includes the following steps:
step S1: providing a substrate 11;
step S2: an n-type semiconductor layer 12, a quantum well layer 13 and a p-type semiconductor layer 14 are sequentially formed on the substrate 11, wherein a portion of the n-type semiconductor layer 12 and a portion of the quantum well layer 13 form an n-type space charge region 101, a portion of the p-type semiconductor layer 14 forms a p-type space charge region 103, and the width of the n-type space charge region 101 is greater than the width 103 of the p-type space charge region.
Step S1 is performed to provide a substrate 11. As the substrate 11, a substrate which can transmit light emitted from the quantum well layer 13 and emit light from the substrate side is preferably used, and for example, a sapphire substrate, a single crystal AlN substrate, or the like can be used. As the substrate 11, an AlN template substrate in which an undoped AlN structure layer is epitaxially grown on the surface of a sapphire substrate may be used. In order to improve the light extraction efficiency, the light exit side of the substrate 11 or the opposite side thereof, or the surface of the AlN structure layer of the AlN template substrate may be uneven. In order to reduce the dislocation of the AlN structure layer, high-temperature (for example, 1500 ℃ or higher) annealing treatment may be performed.
A buffer layer may be provided between the substrate 11 and the n-type semiconductor layer 12 to mitigate lattice mismatch between the substrate 11 and the n-type semiconductor layer 12. The material of the buffer layer is preferably AlN, but is not limited thereto.
Step S2 is performed to form an n-type semiconductor layer 12, a quantum well layer 13 and a p-type semiconductor layer 14 on the substrate 11, wherein a portion of the n-type semiconductor layer 12 and a portion of the quantum well layer 13 form an n-type space charge region 101, and a portion of the p-type semiconductor layer 14 forms a p-type space charge region 103.
An n-type semiconductor layer 12 is formed on a substrate, and the n-type semiconductor layer 12 may be provided on the substrate 11 via the buffer layer as necessary, or the n-type semiconductor layer 12 may be provided directly on the substrate 11. The material of the n-type semiconductor layer 12 may be at least one of GaN, alGaN, inGaN, alInGaN, alN, inN, and AlInN, but is not limited thereto. For example, the n-type semiconductor layer 12 may be made of n-AlGaN. The n-type semiconductor layer 12 is doped with an n-type doping element, preferably Si. The activation energy of the n-type doping element in the n-type semiconductor layer 12 in this embodiment is b, and preferably b ≦ 25meV. The n-type semiconductor layer 12 may have a single-layer structure or a multi-layer structure, or may have a superlattice structure.
After the step of forming the n-type semiconductor layer 12 on the substrate 11, the quantum well layer 13 is formed on the n-type semiconductor layer 12. The material of the quantum well layer 13 may be at least one of GaN, alGaN, inGaN, alInGaN, alN, inN, and AlInN, but is not limited thereto.
The Quantum Well layer 13 is preferably formed of a Multi Quantum Well (MQW) structure in which a Well layer and a barrier layer are formed. In the case of the multiple quantum well structure, the light-emitting layer is a well layer. The quantum well layer 13 is a conventional structure and is not described in detail herein. The quantum well layer 13 is doped with an n-type doping element, and preferably the barrier layer in the quantum well layer 13 is doped with an n-type doping element. The n-type doping element is preferably Si.
The n-type semiconductor layer 12 and the quantum well layer 13 form an n-type space charge region 101 by doping a specific n-type doping element, for example, the n-type semiconductor layer 12 and the quantum well layer 13 form an n-type space charge region 101 by doping Si. The activation energy of the n-type dopant element in the quantum well layer 13 may be the same as or different from the activation energy of the n-type dopant element in the n-type semiconductor layer 12. In this embodiment, the activation energy of the n-type doping element in the quantum well layer 13 is preferably f, and preferably f ≦ 25meV.
In this embodiment, a portion of the n-type semiconductor layer 12 and a portion of the quantum well layer 13 form an n-type space charge region 101. A portion of the n-type semiconductor layer 12 specifically refers to a portion of the n-type semiconductor layer 12 near the quantum well layer 13. A part of the n-type semiconductor layer 12 is preferably 5% or more of the n-type semiconductor layer, that is, the n-type space charge region 101 preferably occupies 5% or more of the n-type semiconductor layer 12. A part of the quantum well layer 13 is preferably 95% or more of the quantum well layer 13, that is, the n-type space charge region 101 preferably occupies 95% or more of the quantum well layer 13. The n-type space charge region 101 preferably occupies 5% or more of the n-type semiconductor layer 12, and the n-type space charge region 101 preferably occupies 95% or more of the quantum well layer 13, so that the width of the n-type space charge region 101 can be greater than the width of the p-type space charge region 103. Part of the quantum well layer 13 specifically refers to a part of the quantum well layer 13 near the n-type semiconductor layer 12.
After the step of forming the quantum well layer 13 on the n-type semiconductor layer 12, the p-type semiconductor layer 14 is formed on the quantum well layer 13. The material of the p-type semiconductor layer 14 may be at least one of GaN, alGaN, inGaN, alInGaN, alN, inN, and AlInN, but is not limited thereto. For example, the p-type semiconductor layer 14 is made of p-AlGaN.
In addition, the p-type semiconductor layer 14 is doped with a p-type doping element. The p-type doping element is preferably Mg. The p-type semiconductor layer 14 in this embodiment forms a p-type space charge region 103 by doping a specific p-type doping element. The p-type semiconductor layer 14 forms the p-type space charge region 103 by doping Mg, for example.
In order to improve the aged light decay performance of the semiconductor light emitting element, it is preferable that the width of the n-type space charge region 101 is larger than the width of the p-type space charge region 103. This embodiment can realize that the width of the n-type space charge region 101 is larger than that of the p-type space charge region 103 by controlling the activation energy difference between the n-type doping element and the p-type doping element. That is, in this embodiment, the activation energy of the n-type doping element is regulated to be lower than the activation energy of the p-type doping element, so that the n-type carrier concentration is greater than the p-type carrier concentration by more than 1 order of magnitude, and the width of the n-type space charge region is greater than that of the p-type space charge region. Further, the activation energy of the p-type doping element in the p-type semiconductor layer 14 is preferably more than 50meV.
In the present embodiment, a part of the p-type semiconductor layer 14 forms a p-type space charge region 103. Preferably, the p-type space charge region 103 occupies 5% or more of the p-type semiconductor layer 14 to ensure that the width of the n-type space charge region 101 can be greater than the width of the p-type space charge region 103. Part of the p-type semiconductor layer 14 specifically refers to a part of the p-type semiconductor layer 14 away from the quantum well layer 13.
The quantum well layer 13 and the p-type semiconductor layer 14 between the p-type space charge region 103 and the n-type space charge region 101 form a pn space charge region. In the present embodiment, the pn space charge region 102 preferably occupies 5% or less of the quantum well layer 13. The pn space charge region 102 preferably occupies 5% or less of the p-type semiconductor layer 14 to ensure that the width of the n-type space charge region 101 can be larger than the width of the p-type space charge region 103, improving the aged light decay performance of the semiconductor light emitting element.
In other embodiments, before forming the p-type semiconductor layer 14, the method for manufacturing a semiconductor light emitting element further includes: an undoped structure layer is formed on the quantum well layer 13. That is, after the step of forming the quantum well layer 13 on the n-type semiconductor layer 12, an undoped structure layer is formed on the quantum well layer 13, and then the p-type semiconductor layer 14 is formed on the undoped structure layer. The formation of the p-type semiconductor layer 14 can be referred to the above embodiments, and is not described herein.
In this embodiment, the quantum well layer 13, the undoped structure layer, and the p-type semiconductor layer 14 between the p-type space charge region 103 and the n-type space charge region 101 form a pn space charge region. The non-doped structure layer is not doped with any doping element, the thickness of the non-doped structure layer is preferably 0.5nm to 20nm, and the material of the non-doped structure layer can be at least one of GaN, alGaN, inGaN, alInGaN, alN, inN and AlInN, but is not limited thereto. For example, the undoped structure layer is made of AlGaN. The undoped structure layer can increase the point defect density after aging less, so that the defect density of the quantum well layer 13 increases less, the well-barrier interface of the quantum well layer 13 and the interface between the quantum well layer and the p-type semiconductor layer 14 keep a clearer and steeper interface, that is, the quantum well layer can maintain better crystal quality, so that the width of the pn space charge region 102 increases less, that is, the embodiment can increase the width of the pn space charge region 102 before and after aging by not more than 10nm through the arrangement of the undoped structure layer. The inventors have studied and found that the semiconductor light emitting element can maintain a good light attenuation level when the width of the pn space charge region 102 before and after aging increases by not more than 10nm. Therefore, the arrangement of the non-doped structure layer can further improve the aging light attenuation performance of the semiconductor light-emitting element.
In this embodiment, by inserting the undoped structure layer between the quantum well layer 13 and the p-type semiconductor layer 14, the p-type doped element and the n-type doped element can be spatially isolated, so that the p-type doped element and the n-type doped element are prevented from being in contact with each other by diffusion in the aging process, and the aging light decay performance of the semiconductor light emitting element is improved; meanwhile, the defect density and defect extension of the n-type semiconductor layer 12 can be reduced, the crystal quality of the quantum well layer 13 and the steepness of a well barrier interface are improved, and the aging light attenuation performance of the semiconductor light-emitting element is further improved.
Further, the width of the pn space charge region 102 increases by a value of a at 0 hours and 1000 hours of aging, and preferably a.ltoreq.10 nm. Still further, the pn space charge region has a width d after aging for 0 hour, and preferably d is less than or equal to 50nm; the pn space-charge region has a width e after 1000 hours of aging, and preferably e ≦ 60nm. In this embodiment, by interposing a non-doped structure layer between the quantum well layer 13 and the p-type semiconductor layer 14, the width of the pn space charge region 102 can be increased by not more than 10nm in aging for 0 hour and 1000 hours, and the aging light attenuation performance of the semiconductor light emitting element can be improved.
In this embodiment, the n-type space charge region 101 preferably occupies 5% or more of the n-type semiconductor layer 12, the n-type space charge region 101 preferably occupies 95% or more of the quantum well layer 13, the p-type space charge region 103 occupies 5% or more of the p-type semiconductor layer 14, the pn-type space charge region 102 preferably occupies 5% or less of the quantum well layer 13, and the pn-type space charge region 102 preferably occupies 5% or less of the p-type semiconductor layer 14, and it is ensured that not only the width of the n-type space charge region 101 can be larger than the width of the p-type space charge region 103, but also the width of the pn-type space charge region 102 increases by not more than 10nm at 0 hour and 1000 hours of aging, thereby ensuring that the aging light attenuation of the semiconductor light-emitting element at 1000 hours of aging is less than 10%.
The utility model discloses can be through setting up n type space charge district 101's width is greater than p type space charge district 103, can improve semiconductor light emitting element's ageing light decay performance.
The utility model discloses a setting n type space charge district 101's width is greater than p type space charge district 103, and through setting up the undoped structural layer, can with the width in pn space charge district increases no more than 10nm at the width of ageing 0 hours and 1000 hours to guarantee that semiconductor light emitting element is less than 10%, is less than 5% even at 1000 hours's ageing light attenuation.
Note that The widths Of The n-type space charge region, the pn space charge region, and The p-type space charge region can be obtained by a PCS-EQE (The External Quantum Efficiency Of The photovoltaic) test.
The semiconductor light emitting element may be formed by a known thin film forming method such as a Metal Organic Chemical Vapor Deposition (MOCVD) method, a Molecular Beam Epitaxy (MBE) method, an HVPE (Hydride Vapor Phase Epitaxy) method, a Plasma Enhanced Chemical Vapor Deposition (PECVD), a sputtering method, and the n-type semiconductor layer 12, the quantum well layer 13, the undoped structure layer, and the p-type semiconductor layer 14 may be formed by an MOCVD method.
In addition, it is to be understood that while the present invention has been disclosed in terms of the preferred embodiment, it is not intended to limit the invention to the disclosed embodiment. To anyone skilled in the art, without departing from the scope of the present invention, the technical solution disclosed above can be used to make many possible variations and modifications to the technical solution of the present invention, or to modify equivalent embodiments with equivalent variations. Therefore, any simple modification, equivalent change and modification made to the above embodiments by the technical entity of the present invention all still fall within the protection scope of the technical solution of the present invention, where the technical entity does not depart from the content of the technical solution of the present invention.
It is to be further understood that the present invention is not limited to the particular methodology, compounds, materials, manufacturing techniques, uses, and applications described herein, as such may, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a step" means a reference to one or more steps and may include sub-steps. All conjunctions used should be understood in the broadest sense. Thus, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Structures described herein are to be understood as also referring to functional equivalents of such structures. Language that can be construed as approximate should be so understood unless the context clearly dictates otherwise.
Claims (12)
1. A semiconductor light-emitting element is characterized by comprising the following components in sequence from bottom to top: the semiconductor device comprises a substrate, an n-type semiconductor layer, a quantum well layer and a p-type semiconductor layer, wherein a part of the n-type semiconductor layer and a part of the quantum well layer form an n-type space charge region, a part of the p-type semiconductor layer forms a p-type space charge region, and the width of the n-type space charge region is larger than that of the p-type space charge region.
2. The semiconductor light emitting element according to claim 1, further comprising a non-doped structural layer, wherein the non-doped structural layer is located between the quantum well layer and the p-type semiconductor layer.
3. The semiconductor light-emitting element according to claim 2, wherein the thickness of the undoped structure layer is 0.5nm to 20nm.
4. The semiconductor light-emitting element according to claim 2, wherein the quantum well layer, the undoped structure layer, and the p-type semiconductor layer between the p-type space charge region and the n-type space charge region form a pn space charge region, and the width of the pn space charge region increases by a value of a and a is 10nm or less at aging for 0 hours and 1000 hours.
5. The semiconductor light-emitting element according to claim 4, wherein the pn space charge region has a width d of 0 hour of aging, and d.ltoreq.50 nm.
6. The semiconductor light-emitting element according to claim 4, wherein the pn space charge region has a width e after aging for 1000 hours, and e.ltoreq.60 nm.
7. The semiconductor light-emitting element according to claim 4, wherein the pn space charge region occupies 5% or less of the quantum well layer.
8. The semiconductor light-emitting element according to claim 4, wherein the pn space charge region occupies 5% or less of the p-type semiconductor layer.
9. The semiconductor light-emitting element according to claim 1, wherein the n-type space-charge region occupies 95% or more of a quantum well layer.
10. The semiconductor light-emitting element according to claim 1, wherein the n-type space charge region occupies 5% or more of the n-type semiconductor layer.
11. The semiconductor light-emitting element according to claim 1, wherein the p-type space charge region occupies 5% or more of the p-type semiconductor layer.
12. The semiconductor light emitting element as claimed in claim 1, wherein the n-type semiconductor layer, the quantum well layer and the p-type semiconductor layer are made of one of GaN, alGaN, inGaN, alInGaN, alN, inN and AlInN.
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