CN218387258U - Isolation controllable discharge impact current suppression circuit - Google Patents
Isolation controllable discharge impact current suppression circuit Download PDFInfo
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- CN218387258U CN218387258U CN202222539610.1U CN202222539610U CN218387258U CN 218387258 U CN218387258 U CN 218387258U CN 202222539610 U CN202222539610 U CN 202222539610U CN 218387258 U CN218387258 U CN 218387258U
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Abstract
The utility model discloses an keep apart controllable impact current suppression circuit who releases can control field effect transistor's grid electric capacity pressure release, control field effect transistor's grid electric capacity charge and discharge. The charging of the grid capacitor can be started when the charging of the filter capacitor is close to the completion, so that the starting-up impact current can be effectively inhibited, the field effect transistor can be ensured to be conducted when the filter capacitor is fully charged, the electrical stress when the field effect transistor is conducted is reduced, the grid capacitor can also be released when the input voltage is powered down to a certain value, and the problem that the field effect transistor is still in a conducting state or is conducted in advance when the power is restarted to cause the damage of the field effect transistor due to the secondary impact current is avoided.
Description
Technical Field
The utility model belongs to electron technology and impulse current restrain the field, concretely relates to keep apart impulse current suppression circuit of controllable release.
Background
At the moment when the dc power supply is started, the capacitor between the following lines is equivalent to a short circuit, and when the capacitor is charged, a large impact current is generated on the power supply bus, and the impact current may damage the preceding circuit device or trigger overcurrent protection of the preceding power supply, causing other electronic devices in the same source to fail to operate normally, so that the impact current needs to be suppressed. The GJB181B-2012 aircraft power supply characteristic has a definite requirement on the impact current: and cannot exceed 5 times the rated current.
In a large-current application occasion, the surge current is limited in a mode of connecting MOS (metal oxide semiconductor) tubes in parallel with power resistors. As shown in fig. 1, the delay conduction of the MOS transistor is utilized, the power resistor is used to suppress the surge current, the MOS transistor is conducted when the voltage of the post-stage capacitor (filter capacitor) is charged to be close to the input voltage, the power resistor is bypassed, and the circuit operates with a very small conduction voltage drop and loss.
The impact current suppression method is simple in circuit and wide in application. But have certain limitations in certain applications. For example, in the application of direct current 270V, the MOS tube can be damaged when the startup and shutdown test is rapidly repeated. The reason for this is that when the dc 270V is turned off, the rear-stage load is turned off after the input voltage drops to a certain value, the voltage of the rear-stage capacitor and/or the gate capacitor of the MOS transistor is not discharged completely, and the rear-stage capacitor also charges the gate capacitor, so that there is a residual voltage at both ends of the gate capacitor. When the power is turned on again in a short time, the MOS tube is still kept in a conducting state or is conducted when the rear-stage capacitor is not fully charged, so that instantaneous impact current is overlarge, and the MOS tube is damaged.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing an keep apart the impulse current suppression circuit of controllable release, solve the problem that exists among the prior art.
The utility model discloses a following technical scheme realizes:
an isolated and controllable-leakage impact current suppression circuit comprises a leakage module, a control module, a switch module, a filtering module, a current suppression module, a positive input end, a negative input end, a positive output end and a negative output end;
the filter module is arranged between the positive output end and the negative output end, the positive output end is connected with the positive input end, the positive input end is connected with the positive output of the external direct-current power supply, the negative input end is connected with the negative output of the external direct-current power supply, and the filter module filters and outputs the direct-current power supply;
the switch module and the current suppression module are connected in parallel and then are arranged between the negative input end and the negative output end, and the switch module adopts a field effect transistor as a switch device; when the field effect transistor in the switch module is conducted, the current suppression module is bypassed; when the field effect transistor in the switch module is switched off, the current suppression module is in a working state;
the control module comprises a grid capacitor arranged between a positive input end and a negative input end, and the voltage of the grid capacitor controls the on-off of the field effect transistor; when the grid capacitance voltage is higher than the conduction threshold voltage of the field effect transistor, the switch module is conducted; when the voltage of the grid capacitor is discharged and pulled down, the switch module is switched off;
the bleeder module is connected with the control module in parallel and is used for bleeding the voltage of the gate capacitor in the control module.
In a possible implementation manner, the filter module includes a filter capacitor C3, one end of the filter capacitor C3 is connected to the negative output terminal, and the other end of the filter capacitor C3 is connected to the positive output terminal.
In a possible implementation manner, the current suppression module includes a power resistor R7, one end of the power resistor R7 is connected to the negative input end, and the other end of the power resistor R7 is connected to one end of the filter capacitor C3 and the negative output end, respectively.
In a possible implementation manner, the switch module includes a field effect transistor Q2, a source of the field effect transistor Q2 is connected to one end and a negative input end of the power resistor R7, a drain of the field effect transistor Q2 is connected to the other end of the resistor R7, one end of the filter capacitor C3, and a negative output end, and a gate of the field effect transistor Q2 is connected to the control module.
In a possible implementation manner, the control module includes a gate capacitor C2, one end of the gate capacitor C2 is connected to the source of the field effect transistor Q2, one end of the power resistor R7 and the negative input end respectively, the other end of the gate capacitor C2 is connected to the other end of the filter capacitor C3, the positive input end and the positive output end through a resistor R5 respectively, and the other end of the gate capacitor C2 is further connected to the gate of the field effect transistor Q2.
In a possible implementation mode, the device further comprises a resistor R6, one end of the resistor R6 is connected with the other end of the gate capacitor C2, and the other end of the resistor R6 is connected with the gate of the field effect transistor Q2.
In a possible implementation manner, the clamping module further includes a zener diode D3, an anode of the zener diode D3 is respectively connected to one end of the gate capacitor C2, the source of the field effect transistor Q2, one end of the power resistor R7, and the negative input end, and a cathode of the zener diode D3 is respectively connected to the other end of the gate capacitor C2 and one end of the resistor R6.
In a possible embodiment, the discharge module includes a photocoupler U1, an emitter of an output triode in the photocoupler U1 is respectively connected with one end of the gate capacitor C2, a positive electrode of the zener diode D3, a source of the field effect transistor Q2, one end of the power resistor R7, and a negative input end, and a collector of the output triode in the photocoupler U1 is respectively connected with the other end of the gate capacitor C2, a negative electrode of the zener diode D3, and one end of the resistor R6.
In one possible embodiment, the positive pole of the input diode in the optocoupler U1 is connected to an external positive voltage signal, and the negative pole of the input diode in the optocoupler U1 is connected to an external negative voltage signal.
In a possible implementation mode, the photoelectric coupler U1 further comprises a resistor R3, and the anode of the input end diode in the photoelectric coupler U1 is connected with an external positive voltage signal through the resistor R3.
The utility model provides a pair of keep apart impact current suppression circuit of controllable release can control field effect transistor's grid electric capacity pressure release, and control field effect transistor's grid electric capacity charges and discharges. The charging of the grid capacitor can be started when the charging of the filter capacitor is close to completion, so that the starting-up impact current can be effectively inhibited, the field effect transistor can be ensured to be conducted when the filter capacitor is fully charged, the electric stress when the field effect transistor is conducted is reduced, the grid capacitor can also be released when the input voltage is powered down to a certain value, and the problem that the field effect transistor is still in a conducting state or is conducted in advance when the power is started again, so that the field effect transistor is damaged by secondary impact current is avoided.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:
fig. 1 is a circuit diagram of a conventional inrush current suppression circuit according to an embodiment of the present application.
Fig. 2 is a circuit block diagram of an isolation controlled bleeding inrush current suppression circuit according to an embodiment of the present application.
Fig. 3 is a circuit diagram of an isolation controlled bleed inrush current suppression circuit according to an embodiment of the present application.
Detailed Description
To make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the following examples and drawings, and the exemplary embodiments and descriptions thereof of the present invention are only used for explaining the present invention, and are not intended as limitations of the present invention.
Examples
As shown in fig. 2 and fig. 3, an isolated and controlled-bleeding inrush current suppression circuit includes a bleeding module, a control module, a switching module, a filtering module, a current suppression module, a positive input terminal Vin +, a negative input terminal Vin-, a positive output terminal Vout +, and a negative output terminal Vout-.
The filtering module is arranged between the positive output end Vout + and the negative output end Vout +, the positive output end Vout + is connected with the positive input end Vin +, the positive input end Vin + is connected with the positive output of the external direct current power supply, the negative input end Vin-is connected with the negative output of the external direct current power supply, and the filtering module filters and outputs the direct current power supply. The positive input terminal Vin + and the negative output terminal Vout-are both connected to a rear-stage load.
The switch module and the current suppression module are connected in parallel and then are arranged between the negative input end Vin-and the negative output end Vout-, and the switch module adopts a field effect transistor as a switch device; when the field effect transistor in the switch module is conducted, the current suppression module is bypassed; when the field effect transistor in the switch module is switched off, the current suppression module is in a working state.
The control module comprises a grid capacitor arranged between a positive input end Vin + and a negative input end Vin-, and the voltage of the grid capacitor controls the on-off of the field effect transistor; when the grid capacitance voltage is higher than the conduction threshold voltage of the field effect transistor, the switch module is conducted; when the grid capacitance voltage is discharged and pulled low, the switch module is disconnected.
The bleeder module is connected in parallel with the control module and is used for bleeding off the voltage of the gate capacitance in the control module.
In a possible implementation, the filter module includes a filter capacitor C3, one end of the filter capacitor C3 is connected to the negative output terminal Vout-, and the other end of the filter capacitor C3 is connected to the positive output terminal Vout +.
In one possible implementation, the current suppression module includes a power resistor R7, one end of the power resistor R7 is connected to the negative input terminal Vin-, and the other end of the power resistor R7 is connected to one end of the filter capacitor C3 and the negative output terminal Vout-, respectively.
In a possible implementation mode, the switch module comprises a field effect transistor Q2, a source electrode of the field effect transistor Q2 is respectively connected with one end of the power resistor R7 and the negative input end Vin-, a drain electrode of the field effect transistor Q2 is respectively connected with the other end of the resistor R7, one end of the filter capacitor C3 and the negative output end Vout-, and a gate electrode of the field effect transistor Q2 is connected with the control module.
At the moment of starting up, the filter capacitor C3 is equivalent to a short circuit, and a large impulse current is generated, which is limited because the field effect transistor Q2 is in an off state, and the peak value of the impulse current is about Vin/R7.
The input voltage charges the filter capacitor C3 through the power resistor R7, the voltage across the filter capacitor C3 rises, the charging time constant is C3 × R7, and the voltage across the filter capacitor C3 is charged to be close to the input voltage after about 5 time constants.
In a possible implementation manner, the control module includes a gate capacitor C2, one end of the gate capacitor C2 is connected to the source of the field effect transistor Q2, one end of the power resistor R7 and the negative input terminal Vin-, the other end of the gate capacitor C2 is connected to the other end of the filter capacitor C3, the positive input terminal Vin + and the positive output terminal Vout + through a resistor R5, and the other end of the gate capacitor C2 is further connected to the gate of the field effect transistor Q2.
In a possible implementation manner, the inrush current suppression circuit for isolated controlled discharging further comprises a resistor R6, one end of the resistor R6 is connected to the other end of the gate capacitor C2, and the other end of the resistor R6 is connected to the gate of the field effect transistor Q2.
In a possible implementation manner, the isolation controlled-bleeding inrush current suppression circuit further comprises a clamping module, the clamping module comprises a voltage stabilizing diode D3, the positive electrode of the voltage stabilizing diode D3 is respectively connected with one end of the gate capacitor C2, the source electrode of the field effect transistor Q2, one end of the power resistor R7 and the negative input terminal Vin-, and the negative electrode of the voltage stabilizing diode D3 is respectively connected with the other end of the gate capacitor C2 and one end of the resistor R6.
The voltage at two ends of the grid capacitor C2 can be clamped through the voltage stabilizing diode D3, the voltage bearable by the grid of the field effect transistor Q2 is generally 20V at the highest, and the voltage stabilizing diode D3 clamps the voltage of the field effect transistor Q2 in a full input voltage range or in the presence of overvoltage surge, so that the protection of the field effect transistor Q2 is realized.
In a possible implementation manner, the bleeder module includes a photoelectric coupler U1, an emitter of an output end triode in the photoelectric coupler U1 is respectively connected with one end of the gate capacitor C2, an anode of the zener diode D3, a source of the field effect transistor Q2, one end of the power resistor R7, and the negative input end Vin-, and a collector of the output end triode in the photoelectric coupler U1 is respectively connected with the other end of the gate capacitor C2, a cathode of the zener diode D3, and one end of the resistor R6.
In one possible embodiment, the positive pole of the input diode in the optocoupler U1 is connected to the external positive voltage signal, and the negative pole of the input diode in the optocoupler U1 is connected to the external negative voltage signal.
For the purpose of description, note that the external positive voltage signal is ctr + and the external negative voltage signal is ctr-, during the charging process of the filter capacitor C3, if ctr +/-floats or ctr +/-is low, the photocoupler U1 is not turned on, and the input voltage also charges the gate capacitor C2 of the field effect transistor Q2 through the resistor R5, and the charging time constant is R5 + C2. When the voltage across the gate capacitor C2 exceeds the turn-on threshold voltage of the field effect transistor Q2, the field effect transistor Q2 is turned on, bypassing the power resistor R7.
To ensure that the field effect transistor Q2 is turned on after the filter capacitor C3 is charged to a nearly complete state, the time constant of the resistor R5 and the gate capacitor C2 may be set. It can also be achieved by adjusting the level of ctr +/or.
When ctr +/-is applied with a high level (for example, a +5V voltage is applied to ctr +, ctr-is grounded), the photoelectric coupler U1 is in a conducting state, two ends of the grid capacitor C2 are equivalent to short circuit, and the input voltage cannot charge the grid capacitor C2 through the resistor R5. When the +5V voltage is cut off or reduced to a low level at any time after the filter capacitor C3 is charged, the photoelectric coupler U1 is turned off, the gate capacitor C2 starts to be charged by the resistor R5, and when the voltages at the two ends of the gate capacitor C reach the turn-on threshold voltage of the field effect transistor Q2, the field effect transistor Q2 is turned on, and the resistor R7 is bypassed.
When the input voltage is powered off due to shutdown or other reasons, the filter capacitor C3 is discharged by the rear-stage load (i.e., the load connected to both ends of the filter capacitor C3 is also the load connected to the positive output end and the negative output end), when the voltage at both ends of the filter capacitor C3 drops to a certain value, the rear-stage load stops working, the discharge of the filter capacitor C3 and the gate capacitor C2 of the field effect transistor Q2 is slow, and even when the system is powered on again, the voltage at both ends of the gate capacitor C2 and the filter capacitor C3 still remains. At this time, ctr +/-is applied with a high level (e.g., + 5V), the photocoupler U1 is in a conducting state, and the voltage across the gate capacitor C2 is discharged. After the system is started again, no matter whether the voltage is still present at the two ends of the filter capacitor C3, the field effect transistor Q2 is in a continuous turn-off state, the input voltage is charged for the filter capacitor C3 again through the power resistor R7, and the start-up impact current is limited.
When the power-on device is started at any time, a high level can be applied to ctr +/-first, the voltage at two ends of the grid capacitor C2 is released, and then the input voltage is applied, so that the starting-on impact current can be accurately inhibited, and the field effect transistor Q2 is prevented from being turned on in advance due to the fact that the grid capacitor C2 is not released completely, so that the field effect transistor Q2 is protected from being damaged, and the reliability is improved.
In a possible implementation manner, the inrush current suppression circuit for isolated controlled discharging further comprises a resistor R3, and the anode of the input end diode in the photocoupler U1 is connected with the external positive voltage signal through the resistor R3.
The utility model provides a pair of keep apart controllable impact current suppression circuit who releases can control field effect transistor's grid electric capacity pressure release, and control field effect transistor's grid electric capacity charges and discharges. The charging of the grid capacitor can be started when the charging of the filter capacitor is close to completion, so that the starting-up impact current can be effectively inhibited, the field effect transistor can be ensured to be conducted when the filter capacitor is fully charged, the electric stress when the field effect transistor is conducted is reduced, the grid capacitor can also be released when the input voltage is powered down to a certain value, and the problem that the field effect transistor is still in a conducting state or is conducted in advance when the power is started again, so that the field effect transistor is damaged by secondary impact current is avoided.
The above embodiments further describe the objects, technical solutions and advantages of the present invention in detail, it should be understood that the above embodiments are only specific embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. An isolated and controllable-leakage impact current suppression circuit is characterized by comprising a leakage module, a control module, a switch module, a filtering module, a current suppression module, a positive input end, a negative input end, a positive output end and a negative output end;
the filter module is arranged between the positive output end and the negative output end, the positive output end is connected with the positive input end, the positive input end is connected with the positive output of the external direct-current power supply, the negative input end is connected with the negative output of the external direct-current power supply, and the filter module filters and outputs the direct-current power supply;
the switch module and the current suppression module are connected in parallel and then are arranged between the negative input end and the negative output end, and the switch module adopts a field effect transistor as a switch device; when the field effect transistor in the switch module is conducted, the current suppression module is bypassed; when the field effect transistor in the switch module is switched off, the current suppression module is in a working state;
the control module comprises a grid capacitor arranged between a positive input end and a negative input end, and the voltage of the grid capacitor controls the on-off of the field effect transistor; when the grid capacitance voltage is higher than the conduction threshold voltage of the field effect transistor, the switch module is conducted; when the voltage of the grid capacitor is discharged and pulled down, the switch module is switched off;
the bleeder module is connected with the control module in parallel and is used for bleeding off the voltage of the gate capacitor in the control module.
2. The isolated controlled bleed inrush current suppression circuit of claim 1, wherein said filter module comprises a filter capacitor C3, one end of said filter capacitor C3 being connected to the negative output terminal, the other end of said filter capacitor C3 being connected to the positive output terminal.
3. The isolated controlled bleed inrush current suppression circuit of claim 2, wherein the current suppression module comprises a power resistor R7, one end of the power resistor R7 is connected to the negative input terminal, and the other end of the power resistor R7 is connected to one end of the filter capacitor C3 and the negative output terminal, respectively.
4. The isolated controlled bleed-off inrush current suppression circuit according to claim 3, wherein the switching module comprises a field effect transistor Q2, a source of the field effect transistor Q2 is connected to one end of the power resistor R7 and the negative input end, a drain of the field effect transistor Q2 is connected to the other end of the resistor R7, one end of the filter capacitor C3 and the negative output end, and a gate of the field effect transistor Q2 is connected to the control module.
5. The isolated controlled bleed-off inrush current suppression circuit according to claim 4, wherein the control module comprises a gate capacitor C2, one end of the gate capacitor C2 is connected to the source of the field effect transistor Q2, one end of the power resistor R7 and the negative input end, the other end of the gate capacitor C2 is connected to the other end of the filter capacitor C3, the positive input end and the positive output end through a resistor R5, and the other end of the gate capacitor C2 is further connected to the gate of the field effect transistor Q2.
6. The isolated controlled bleed inrush current suppression circuit of claim 5, further comprising a resistor R6, wherein one end of the resistor R6 is connected to the other end of the gate capacitor C2, and wherein the other end of the resistor R6 is connected to the gate of the field effect transistor Q2.
7. The isolated controlled bleed inrush current suppression circuit of claim 5, further comprising a clamping module, wherein the clamping module comprises a zener diode D3, an anode of the zener diode D3 is connected to one end of the gate capacitor C2, a source of the field effect transistor Q2, one end of the power resistor R7, and a negative input terminal of the zener diode D3, and a cathode of the zener diode D3 is connected to the other end of the gate capacitor C2 and one end of the resistor R6, respectively.
8. The isolated controlled-bleeding inrush current suppression circuit according to claim 7, wherein the bleeding module comprises a photocoupler U1, an emitter of an output-side triode in the photocoupler U1 is connected to one end of the gate capacitor C2, an anode of the zener diode D3, a source of the field effect transistor Q2, one end of the power resistor R7, and a negative input end of the field effect transistor, respectively, and a collector of the output-side triode in the photocoupler U1 is connected to the other end of the gate capacitor C2, a cathode of the zener diode D3, and one end of the resistor R6, respectively.
9. The isolated controlled bleed inrush current suppression circuit of claim 8, wherein the positive terminal of the input terminal diode of the optocoupler U1 is coupled to an external positive voltage signal and the negative terminal of the input terminal diode of the optocoupler U1 is coupled to an external negative voltage signal.
10. The isolated controlled bleed inrush current suppression circuit of claim 9, further comprising a resistor R3, wherein the positive terminal of the input diode of the optocoupler U1 is coupled to the external positive voltage signal via the resistor R3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222539610.1U CN218387258U (en) | 2022-09-26 | 2022-09-26 | Isolation controllable discharge impact current suppression circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222539610.1U CN218387258U (en) | 2022-09-26 | 2022-09-26 | Isolation controllable discharge impact current suppression circuit |
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| CN218387258U true CN218387258U (en) | 2023-01-24 |
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| CN202222539610.1U Active CN218387258U (en) | 2022-09-26 | 2022-09-26 | Isolation controllable discharge impact current suppression circuit |
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