CN218352766U - LED power-down processing circuit and LED lighting device - Google Patents

Abstract

The application relates to an LED power-down processing circuit and an LED lighting device, the LED power-down processing circuit comprises a voltage detection circuit, a sequential logic signal generation circuit, a logic operation circuit and a feedback circuit which are sequentially connected, wherein the voltage detection circuit detects the power supply voltage VCC of a controller, the sequential logic signal generation circuit generates various sequential logic signals according to the power supply voltage VCC, the logic operation circuit performs logic operation on the various sequential logic signals and generates sequential control signals, the sequential control signals control the feedback circuit to generate strong pull-down current after representing that the controller enters an under-voltage locking state, and a voltage-stabilizing capacitor corresponding to the power supply voltage VCC discharges to reduce the input voltage VCC; when the representation power supply voltage VCC drops to a strong pull-down closing threshold voltage which is smaller than the under-voltage locking threshold voltage, controlling the feedback circuit to stop generating strong pull-down current; when the representation power supply voltage VCC rises to a strong pull-down opening threshold voltage which is less than or equal to the under-voltage locking elimination threshold voltage, the feedback circuit is controlled to generate a strong pull-down current.

Description

LED power-down processing circuit and LED lighting device

Technical Field

The application belongs to the technical field of LED power failure processing, and particularly relates to an LED power failure processing circuit and an LED lighting device.

Background

The LED lighting device has the advantages of low energy consumption, long service life, low pollution and the like, and is rapidly popularized in the lighting industry. Some LED lighting devices have a problem of back-flashing of power-off after the lamp is turned off and then turned on again, which is caused by the following reasons:

in the LED lighting device, an ac power source is rectified by a bridge rectifier, and then a dc line voltage VIN is generated on a bus capacitor 4 (see fig. 2). After the power supply is cut off, because peripheral power supply is insufficient to supply power to the LED lighting control circuit, the LED lighting control circuit can enter an under-voltage locking state firstly, under the state, the LED lamp is turned off, after the LED lighting control circuit enters the under-voltage locking state, because the working current of the LED lighting control circuit is reduced, the peripheral power supply enables the LED lighting control circuit to exit the under-voltage locking state, the LED is lightened again after the LED lighting control circuit starts to work, the working current of the LED lighting control circuit is increased, the peripheral power supply can not maintain the LED lighting control circuit to work, the LED lighting control circuit enters the under-voltage locking state again, the process is repeated to cause a plurality of times of power-down back flashings, and the electric quantity of the bus capacitor 4 is insufficient to support the LED lighting control circuit to start.

In practical application, the problem of power-off flash back caused by re-lighting after the lamp of the LED lighting device is turned off can bring poor use experience to users.

SUMMERY OF THE UTILITY MODEL

Therefore, the LED power-down processing circuit and the LED lighting device are provided to solve the problem that the LED lighting device flashes back after power failure.

In order to achieve the purpose, the following technical scheme is adopted in the application:

in a first aspect, the present application provides a power down processing circuit for an LED, including: the voltage detection circuit, the sequential logic signal generation circuit, the logic operation circuit and the feedback circuit are connected in sequence;

the voltage detection circuit is used for detecting the power supply voltage VCC of the controller;

the sequential logic signal generating circuit is used for generating various sequential logic signals according to the power supply voltage VCC;

the logic operation circuit is used for carrying out logic operation on the various time sequence logic signals to generate time sequence control signals, the time sequence control signals are used for driving the feedback circuit to generate a strong pull-down current Isd after the controller is characterized to enter an under-voltage locking state, the strong pull-down current Isd is used for being applied to a power supply voltage VCC end of the controller, the sum of the strong pull-down current Isd and the working current of the controller when the controller enters the under-voltage locking state is larger than the power supply current provided by peripheral power supply, and a voltage stabilizing capacitor corresponding to the power supply voltage VCC end of the controller discharges to reduce the power supply voltage VCC; when the power supply voltage VCC is reduced to a strong pull-down closing threshold voltage, the time sequence control signal drives the feedback circuit to stop generating the strong pull-down current Isd, wherein the strong pull-down closing threshold voltage is smaller than an under-voltage locking threshold voltage; when the power supply voltage VCC is represented to rise to a strong pull-down opening threshold voltage, the time sequence control signal drives the feedback circuit to generate the strong pull-down current Isd, wherein the strong pull-down opening threshold voltage is smaller than or equal to an undervoltage locking elimination threshold voltage.

Further, the sequential logic signal generating circuit includes: the POR detection circuit comprises a first selector, a second selector, a first comparator, a second comparator, a first inverter, a first trigger and a power-on reset POR detection circuit;

the input ends of the first selector, the second selector and the power-on reset POR detection circuit are respectively connected with the voltage detection circuit;

the output end of the first selector is connected with the non-inverting input end of the first comparator;

the output end of the first comparator is connected with the control end of the first selector and the logic operation circuit in common, the output end of the first comparator is also connected with the trigger end of the first trigger through the first phase inverter, and the trigger end of the first trigger

The output end is connected with the logic operation circuit;

the EN end of the first comparator and the CLR end of the first trigger are both connected with a first control output end of the logic operation circuit;

the output end of the second selector is connected with the positive phase input end of the second comparator, and the control end of the second selector is connected with the output end of the second comparator;

the output end of the second comparator is connected with the logic operation circuit; and

and the output end of the power-on reset POR detection circuit is respectively connected with the EN end of the second comparator and the logic operation circuit.

Further, the logical operation circuit includes: the first NAND gate, the second trigger, the second inverter and the driver;

the first NAND gate is respectively connected with the output end of the first comparator and the first trigger

The output end of the first NAND gate is connected with the first input end of the second NAND gate;

a second input end of the second nand gate is commonly connected with an output end of the second comparator and an input end of the second inverter;

the output end of the second inverter is connected with the trigger end of the second trigger;

the CLR end of the second trigger is connected with the output end of the power-on reset POR detection circuit, and the CLR end of the second trigger is connected with the output end of the power-on reset POR detection circuit

The output end of the first NAND gate is connected with the first input end of the first NAND gate;

the Q output end of the second trigger is used as the first control output end;

the output end of the second NAND gate is connected with the input end of the driver, and the output end of the driver is used as a second control output end and connected with the feedback circuit.

Further, the first flip-flop and the second flip-flop are both D flip-flops.

Further, the strong pull-down turn-off threshold voltage is less than the under-voltage lockout threshold voltage and greater than a power-on reset voltage.

Further, the feedback circuit includes:

the control end of the electronic switch is connected with the output end of the logic operation circuit;

and the feedback generation unit is connected with the electronic switch.

Further, the feedback generation unit is a current source circuit.

Further, the feedback generation unit is a resistor.

Further, the electronic switch adopts a field effect transistor.

In a second aspect, the present application provides an LED lighting device comprising the LED power-down processing circuit as described in any one of the above.

This application adopts above technical scheme, possesses following beneficial effect at least:

according to the scheme, the voltage detection circuit detects the power supply voltage VCC of the controller, the sequential logic signal generation circuit generates various sequential logic signals according to the power supply voltage VCC, the logic operation circuit performs logic operation on various sequential logic signals to generate a sequential control signal, after the sequential control signal represents that the controller enters an under-voltage locking state, the driving feedback circuit generates a strong pull-down current Isd, the strong pull-down current Isd is applied to the power supply voltage VCC end of the controller, the sum of the strong pull-down current Isd and the working current when the controller enters the under-voltage locking state is larger than the power supply current provided by peripheral power supply, a voltage-stabilizing capacitor corresponding to the power supply voltage VCC end of the controller discharges to enable the power supply voltage VCC to fall, when the representation power supply voltage VCC falls to a strong pull-down closing threshold voltage smaller than the under-voltage locking threshold voltage, the control feedback circuit stops generating the strong pull-down current Isd, the power supply current provided by the peripheral power supply is larger than the working current of the controller in the state, namely, the peripheral power supply voltage is enabled to the voltage-stabilizing charging capacitor corresponding to the power supply voltage VCC. When the representation power supply voltage VCC rises to the strong pull-down opening threshold voltage which is less than or equal to the under-voltage locking elimination threshold voltage, the control feedback circuit generates a strong pull-down current Isd, at the moment, the power supply current provided by peripheral power supply is less than the sum of the strong pull-down current Isd and the working current of the controller in the state, and the voltage stabilizing capacitor corresponding to the power supply voltage VCC end of the controller discharges to lower the power supply voltage VCC.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 is a flow diagram illustrating a method of LED power down handling in accordance with an exemplary embodiment;

FIG. 2 is a block diagram schematic diagram illustrating an LED power down processing circuit in accordance with an exemplary embodiment;

FIG. 3 is a schematic diagram illustrating a power down process implemented using sequential logic signals in accordance with an illustrative embodiment;

FIG. 4 is a schematic diagram illustrating an LED power down handling circuit implementation in accordance with an exemplary embodiment;

fig. 5 is a schematic diagram illustrating an implementation of a LED power down handling circuit according to another exemplary embodiment.

In the figure:

2-LED power-down processing circuit; 3-a controller; 4-bus capacitance; 5-peripheral power supply module; 6-a voltage stabilizing capacitor;

21-a voltage detection circuit; 22-sequential logic signal generation circuit 22; 23-a logical operation circuit; 24-a feedback circuit;

m1 — a first selector; m2-a second selector; c1-a first comparator; c2 — a second comparator; p1-a first inverter; d1-a first flip-flop; n1-a first NAND gate; n2-a second nand gate; d2-a second flip-flop; p2-second inverter; dr-driver; t1-electronic switch; I.C. A _load -a current source circuit; r is _load -a resistance; 201-power on reset POR detection circuit; 202-feedback generation unit.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be described in detail below. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the examples given herein without making any creative effort, shall fall within the protection scope of the present application.

Referring to fig. 1, fig. 1 is a flowchart illustrating a method for processing power down of an LED, which is applied to an LED lighting device, according to an exemplary embodiment, and includes the following steps:

step S11, controlling a feedback circuit to generate a strong pull-down current Isd based on a power supply voltage VCC of a controller after the controller enters an under-voltage locking state, wherein the strong pull-down current Isd is used for being applied to a power supply voltage VCC end of the controller, the sum of the strong pull-down current Isd and a working current when the controller enters the under-voltage locking state is larger than a power supply current provided by peripheral power supply, and a voltage stabilizing capacitor 6 corresponding to the power supply voltage VCC end of the controller discharges to reduce the power supply voltage VCC;

step S12, when the power supply voltage VCC is reduced to a strong pull-down closing threshold voltage V _SD-OPEN1 And controlling the feedback circuit to stop generating the strong pull-down current Isd, wherein the strong pull-down closes a threshold voltage V _SD-OPEN1 Less than undervoltage lockout threshold voltage V _UVLOL ；

Step S13, when the power supply voltage VCC rises to the strong pull-down opening threshold voltage V _SD-CLOSE And controlling the feedback circuit to generate the strong pull-down current Isd, wherein the strong pull-down opening threshold voltage V _SD-CLOSE Less than or equal to undervoltage lockout cancellation threshold voltage V _UVLOH 。

Specifically, referring to fig. 2 and 3, fig. 2 and 3 illustrate a specific application of the method. In practical application, the LED lighting device is in a lighting state, the bus capacitor 4 stores electric quantity, after the LED lighting device enters a power-down state, the LED lighting device is under the following conditions, the bus capacitor 4 releases the electric quantity, the controller 3 is powered by peripheral power supply, the working current of the controller 3 working normally is large, the peripheral power supply cannot maintain the LED lighting control circuit to work under the state, the voltage stabilizing capacitor corresponding to the VCC end of the power supply voltage of the controller discharges, and the VCC end of the power supply voltage of the controller is pulled down and reduced.

Referring to FIG. 2, when VCC drops below the under-voltage lockout threshold voltage (V in FIG. 3) _UVLOL ) And then, the controller 3 enters an undervoltage locking state, the control feedback circuit 24 generates a strong pull-down current Isd, the strong pull-down current Isd is applied to the power supply voltage VCC end of the controller 3, the sum of the strong pull-down current Isd and the working current when the controller 3 enters the undervoltage locking state is greater than the power supply current provided by peripheral power supply, and the voltage stabilizing capacitor 6 corresponding to the power supply voltage VCC end of the controller 3 discharges, so that the power supply voltage VCC is reduced.

In this application, the strong pull-down turns off the threshold voltage (V in FIG. 3) _SD-OPEN1 ) For indicating release of the applied strong pull-down current Isd when the supply voltage VCC drops to the strong pull-down turn-off threshold voltage V _SD-OPEN1 When the voltage stabilizing capacitor 6 is charged, the voltage stabilizing capacitor is charged, and the voltage of the power supply voltage VCC end of the controller 3 is increased. In practical application, after the LED illumination control circuit enters the undervoltage locking state, the LED illumination control circuit works with currentAnd the supply current provided by the bus capacitor 4 through peripheral power supply after the bridge is less than the working current of the controller 3 under the state, and the voltage stabilizing capacitor 6 corresponding to the power supply voltage VCC end of the controller 3 is charged by the peripheral power supply at the moment, so that the power supply voltage VCC is increased. When the supply voltage VCC rises above the under-voltage lockout cancellation threshold voltage (V in FIG. 3) _UVLOH ) The LED is turned on again after the start of operation, resulting in the occurrence of a flashback.

In the present application, the strong pull-down turn-on threshold voltage (V in FIG. 3) is set _SD-CLOSE ) The strong pull-down turn-on threshold voltage V _SD-CLOSE Used for indicating to reapply the strong pull-down current Isd to ensure that the under-voltage locking state can not be released, and when the power supply voltage VCC rises to the strong pull-down opening threshold voltage V _SD-CLOSE In time, the trigger control feedback circuit 24 generates a strong pull-down current Isd, so that the problem of power failure and back flash caused by trigger release under-voltage locking caused by rising of the power supply voltage VCC is solved. This application is repeated above-mentioned process a plurality of times, can drop the electric quantity in bus capacitor 4 to solved the power off and dodged the problem back, and then helped ensureing user's LED illumination and use experience.

For the above scheme, the following technical effects can also be obtained, please refer to the second power-down shown in fig. 3, that is, during the period that the bus capacitor 4 supplies power to the controller 3 through the peripheral power supply after the bridge, the supply current provided by the peripheral power supply is smaller than the working current of the controller 3 in the under-voltage locking state, and at this time, the voltage stabilizing capacitor 6 corresponding to the supply voltage VCC terminal of the controller 3 discharges, so that the supply voltage VCC of the controller is reduced to be lower than V _POR And meanwhile, the circuit realizes power-down reset and does not influence quick power-on starting again.

In one embodiment, referring to FIG. 3, the strong pull-down turn-off threshold voltage V _SD-OPEN1 Less than the under-voltage lockout threshold voltage V _UVLOL And is greater than the power-on reset voltage V _POR . Under this scheme, during the power failure, realized releasing the electric energy of bus capacitor 4 behind the bridge, guaranteed simultaneously that controller 3 is in non-start operating condition, solved and fallen the power failure and return the sudden strain of a muscle problem. Referring to fig. 3, the first power down and the subsequent warm start are shown, and the controller 3 can start normally by the scheme of the present application. At the same timeAfter power failure reset, the scheme does not influence the starting speed of the controller 3.

In one embodiment, the method further comprises: when the supply voltage VCC rises above the undervoltage lockout elimination threshold voltage V _UVLOH The controller 3 releases the under-voltage lock state. Namely when the supply voltage VCC is greater than the undervoltage lockout elimination threshold voltage V _UVLOH And when the controller 3 is in the normal working state, the undervoltage locking state is switched.

In one embodiment, the constraint control threshold voltage (V) may be increased for the supply voltage VCC of the controller 3 during power-down _{SD_OPEN2} ). Specifically, the threshold voltage V is turned on under strong pull-down _SD-CLOSE Eliminating threshold voltage V with under-voltage lockout _UVLOH With the constraint control threshold voltage V added _{SD_OPEN2} (ii) a During power-down, the supply voltage VCC of the controller 3 increases to a strong pull-down turn-on threshold voltage V _SD-CLOSE At this time, the strong pull-down is turned on, and if the power supply voltage VCC of the controller 3 continues to increase to the constraint control threshold voltage V _{SD_OPEN2} And if so, closing the strong pull-down so as to realize quick start of power-up during power-down. And, in the period that the bus capacitor 4 supplies power to the controller 3 through peripheral power supply after the bridge, the supply current that the peripheral power supply provided is less than the operating current of the controller 3 under the undervoltage locking state, and the voltage stabilizing capacitor 6 that corresponds to the supply voltage VCC end of the controller 3 discharges at this moment, so that the supply voltage VCC of the controller is reduced to be lower than V _POR And meanwhile, the circuit realizes power-down reset and does not influence quick power-on starting again.

In one embodiment, the step of controlling the feedback circuit to generate the strong pull-down current Isd after the controller enters the under-voltage lockout state based on the supply voltage VCC of the controller includes:

aiming at the power supply voltage VCC, obtaining a plurality of time sequence logic signals with preset quantity;

and performing logic operation on the various sequential logic signals, and controlling the feedback circuit to generate the strong pull-down current Isd after determining that a logic operation result represents that the controller 3 enters an undervoltage locking state.

Referring to fig. 3, fig. 3 shows that four sequential logic signals CTR1, CTR2, FLAG and CTR3 are obtained according to the power supply voltage VCC of the controller 3, and then the four sequential logic signals are subjected to logic operation to obtain the logic operation result SD _ CTR shown in fig. 3, where SD _ CTR is also embodied in a sequential logic signal form, and when it is characterized that the controller 3 enters an under-voltage locking state, the control signal is represented by a high level and controls the feedback circuit 24 to generate the strong pull-down current Isd.

The application further provides an LED lighting device to apply the LED power-down processing method.

For the LED lighting device, the LED power failure processing method of any one of the foregoing embodiments is applied to solve the problem of avoiding the problem of power-off flash back caused by re-lighting after the lamp goes out.

Referring to fig. 2, the present application further provides a power down processing circuit for an LED, including: a voltage detection circuit 21, a sequential logic signal generation circuit 22, a logic operation circuit 23 and a feedback circuit 24 which are connected in sequence;

the voltage detection circuit 21 is used for detecting a power supply voltage VCC of the controller;

the sequential logic signal generating circuit 22 is configured to generate a plurality of sequential logic signals according to the supply voltage VCC;

the logic operation circuit 23 is configured to perform logic operation on the multiple kinds of timing logic signals to generate timing control signals, where the timing control signals are configured to drive the feedback circuit 24 to generate a strong pull-down current Isd after characterizing that the controller enters an under-voltage locking state, the strong pull-down current Isd is configured to be applied to a power supply voltage VCC end of the controller, a sum of the strong pull-down current Isd and a working current when the controller enters the under-voltage locking state is greater than a power supply current provided by peripheral power supply, and a voltage stabilizing capacitor 6 corresponding to the power supply voltage VCC end of the controller discharges to reduce the power supply voltage VCC; then, when the characteristic shows that the power supply voltage VCC drops to a strong pull-down closing threshold voltage V _SD-OPEN1 Time, said time sequence controlThe control signal drives the feedback circuit 24 to stop generating the strong pull-down current Isd, which turns off the threshold voltage V _SD-OPEN1 Less than undervoltage lockout threshold voltage V _UVLOL (ii) a When the power supply voltage VCC is represented to rise to a strong pull-down turn-on threshold voltage V _SD-CLOSE Then, the timing control signal drives the feedback circuit 24 to generate the strong pull-down current Isd, and the strong pull-down turns on the threshold voltage V _SD-CLOSE Less than or equal to undervoltage lockout cancellation threshold voltage V _UVLOH 。

Referring to the LED lighting device shown in fig. 2, after the ac power is rectified by the bridge rectifier, the dc line voltage VIN is generated on the bus capacitor 4, and is transmitted to the peripheral power supply module 5, and the peripheral power supply module 5 supplies power to the controller 3. For the functional implementation of both the sequential logic signal generating circuit 22 and the logic operation circuit 23, please refer to the sequential logic signal control shown in fig. 3, fig. 3 shows that four sequential logic signals CTR1, CTR2, FLAG and CTR3 are obtained according to the power supply voltage VCC of the controller 3, then the four sequential logic signals are logically operated to obtain the logical operation result SD _ CTR shown in fig. 3, i.e. a sequential control signal, the SD _ CTR is also embodied in a sequential logic signal form, and the high level thereof drives the feedback circuit 24 to generate the strong pull-down current Isd, for which the function has been described in detail in the related embodiments, and will not be described in detail herein.

The peripheral power supply module 5 shown in fig. 2 can be implemented, but not limited to, by a starting resistor to provide the voltage required by the supply voltage VCC terminal of the controller 3. The voltage detection circuit 21 is used to detect the power supply voltage VCC of the controller 3, and for the voltage detection module 21, a conventional resistance voltage division manner may be adopted to implement, and other conventional voltage detection manners may also be adopted to implement.

In one embodiment, the strong pull-down turn-off threshold voltage V _SD-OPEN1 Less than undervoltage lockout threshold voltage V _UVLOL And is greater than the power-on reset voltage V _POR 。

Referring to fig. 3, fig. 3 shows four timing logics obtained by the controller 3 for the supply voltage VCC, CTR1, CTR2, FLAG and CTR3FIG. 3 shows a timing control signal SD _ CTR obtained under four timing logic signals CTR1, CTR2, FLAG and CTR3, which can represent a strong pull-down turn-off threshold voltage V _SD-OPEN1 Less than undervoltage lockout threshold voltage V _UVLOL And is greater than the power-on reset voltage V _POR . Under this scheme, during the power failure, realized releasing the electric energy of bus capacitor 4 behind the bridge, guaranteed simultaneously that controller 3 is in non-start operating condition, solved and fallen the power failure and return the sudden strain of a muscle problem. Referring to fig. 3, the first power down and the subsequent warm start are shown, and the controller 3 can start normally by the scheme of the present application. Meanwhile, after power failure reset, the starting speed of the controller 3 is not influenced by the scheme.

Further, referring to fig. 4, in one embodiment, the sequential logic signal generating circuit 22 includes: a first selector M1, a second selector M2, a first comparator C1, a second comparator C2, a first inverter P1, a first trigger D1, and a power-on reset POR detection circuit 201;

the input ends of the first selector M1, the second selector M2 and the power-on reset POR detection circuit 201 are respectively connected to the voltage detection circuit 21;

the output end of the first selector M1 is connected with the non-inverting input end of the first comparator C1;

the output end of the first comparator C1 is connected to the control end of the first selector M1 and the logic operation circuit 23, the output end of the first comparator C1 is further connected to the trigger end of the first flip-flop D1 through the first inverter P1, and the output end of the first flip-flop D1 is connected to the trigger end of the first flip-flop D1

The output end is connected with the logic operation circuit 23;

the EN end of the first comparator C1 and the CLR end of the first flip-flop D1 are both connected to the first control output end of the logical operation circuit 23;

the output end of the second selector M2 is connected to the non-inverting input end of the second comparator C2, and the control end of the second selector M2 is connected to the output end of the second comparator C2;

the output end of the second comparator C2 is connected to the logical operation circuit 23; and

the output end of the power-on reset POR detection circuit 201 is connected to the EN end of the second comparator C2 and the logic operation circuit 23, respectively.

Specifically, the above specific embodiment of the sequential logic signal generating circuit 22 is used for generating four sequential logic signals CTR1, CTR2, FLAG and CTR3 shown in fig. 3, wherein the output end of the first comparator C1 is connected to the logic operation circuit 23 to output a first sequential logic signal to the logic operation circuit 23, and the first sequential logic signal corresponds to CTR3 shown in fig. 3; of said first flip-flop D1

The output end of the output end is connected with the logic operation circuit 23 so as to output a second sequential logic signal to the logic operation circuit 23, wherein the second sequential logic signal corresponds to the shown FLAG; the output end of the second comparator C2 is connected to the logic operation circuit 23 to output a third sequential logic signal to the logic operation circuit 23, where the third sequential logic signal corresponds to CTR2 shown in fig. 3; the output terminal of the power-on reset POR detection circuit 202 is connected to the logic operation circuit 23, so as to output a fourth timing logic signal to the logic operation circuit 23, where the fourth timing logic signal corresponds to CTR1 shown in fig. 3.

Further, referring to fig. 4, in one embodiment, the logic operation circuit 23 includes: a first nand gate N1, a second nand gate N2, a second flip-flop D2, a second inverter P2 and a driver Dr;

the first nand gate N1 is respectively connected with the output end of the first comparator C1 and the output end of the first flip-flop D1

The output end of the first NAND gate N1 is connected with the first input end of the second NAND gate N2;

a second input end of the second nand gate N2 is commonly connected with an output end of the second comparator C2 and an input end of the second inverter P2;

the output end of the second inverter P2 is connected to the trigger end of the second flip-flop D2;

the CLR terminal of the second flip-flop D2 is connected to the output terminal of the power-on reset POR detection circuit 201, and the CLR terminal of the second flip-flop D2 is connected to the output terminal of the POR detection circuit 201

The output end of the first NAND gate is connected with the third input end of the second NAND gate N2;

the Q output end of the second trigger D2 is used as the first control output end;

the output end of the second nand gate N2 is connected to the input end of the driver Dr, and the output end of the driver Dr is connected to the feedback circuit 24 as a second control output end.

Specifically, the specific embodiment of the logic operation circuit 23 is configured to perform a logic operation on four sequential logic signals CTR1, CTR2, FLAG, and CTR3 shown in fig. 3 to obtain a logic operation result SD _ CTR shown in fig. 3, where the SD _ CTR is also embodied in a sequential logic signal form, and a high level of the SD _ CTR drives the feedback circuit 24 to generate a strong pull-down current Isd that prevents the bus capacitor 4 from supplying power to the controller 3.

For the first flip-flop D1 and the second flip-flop D2 in the above embodiments, in practical applications, a D flip-flop may be used, but is not limited to.

Referring to fig. 4 and 5, in one embodiment, the feedback circuit 24 includes:

the control end of the electronic switch T1 is connected with the output end of the logic operation circuit 23;

and a feedback generating unit 202 connected to the electronic switch T1.

Specifically, the electronic switch T1 may be implemented by, but not limited to, a field effect transistor, and as shown in fig. 4, the field effect transistor is used as the electronic switch T1. After the electronic switch T1 is turned on, the feedback circuit 24 forms a path, and generates a strong pull-down current Isd by using the feedback generating unit 202, where the strong pull-down current Isd is applied to the supply voltage VCC terminal of the controller 3 to block the bus capacitor 4 from supplying power to the controller 3.

Referring to fig. 4, further, the feedback generation unit 202 may be a current source circuit I _load 。

This scheme is described below. In practical application, the current source circuit I _load When the LED illumination is normally powered, the electric energy can be obtained and stored. After the electronic switch T1 is turned on, the feedback circuit 24 forms a path, the current source circuit I _load The generated feedback current is applied to a supply voltage VCC end of the controller 3, and the sum of the feedback current and the working current when the controller 3 enters an undervoltage locking state is larger than the supply current provided by peripheral power supply, so that the bus capacitor 4 does not supply power to the controller 3.

Referring to fig. 5, further, the feedback generating unit 202 may be a resistor R _load 。

After the electronic switch T1 is turned on, the feedback circuit 24 forms a path, and the resistor R _load And after the strong pull-down current Isd is applied to a power supply voltage VCC end of the controller 3, the sum of the strong pull-down current Isd and the working current when the controller 3 enters an under-voltage locking state is larger than the power supply current provided by peripheral power supply, so that the bus capacitor 4 does not supply power to the controller 3.

The application provides an LED lighting device, includes as above-mentioned any one LED falls electric treatment circuit. For the LED lighting device, the LED power down processing circuit of any one of the foregoing embodiments is applied to solve the problem of avoiding the problem of power-down flash back caused by re-lighting after the lamp goes out, and the circuit has been described in detail in the foregoing embodiments, and will not be described again here.

It is understood that the same or similar parts in the above embodiments may be mutually referred to, and the same or similar contents in other embodiments may be referred to for the contents which are not described in detail in some embodiments.

It should be noted that, in the description of the present application, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In addition, in the description of the present application, the meaning of "plurality" means at least two unless otherwise specified.

It will be understood that when an element is referred to as being "fixed" or "disposed" to another element, it can be directly on the other element or intervening elements may also be present; when an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present, and further, as used herein, connected may include wirelessly connected; the term "and/or" is used to include any and all combinations of one or more of the associated listed items.

Any process or method descriptions in flow charts or otherwise described herein may be understood as: represents modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and the scope of the preferred embodiments of the present application includes additional implementations in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present application.

It should be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.

It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and when the program is executed, the program includes one or a combination of the steps of the method embodiments.

In addition, functional units in the embodiments of the present application may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.

The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc.

In the description herein, reference to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Although embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application, and that variations, modifications, substitutions and alterations may be made to the above embodiments by those of ordinary skill in the art within the scope of the present application.

Claims (10)

1. An LED power-down processing circuit, comprising: the device comprises a voltage detection circuit (21), a sequential logic signal generation circuit (22), a logic operation circuit (23) and a feedback circuit (24) which are connected in sequence;

the voltage detection circuit (21) is used for detecting the power supply voltage VCC of the controller;

the sequential logic signal generating circuit (22) is used for generating various sequential logic signals according to the power supply voltage VCC;

the logic operation circuit (23) is used for performing logic operation on the various sequential logic signals to generate sequential control signals, the sequential control signals are used for driving the feedback circuit (24) to generate a strong pull-down current Isd after representing that the controller enters an under-voltage locking state, wherein the strong pull-down current Isd is used for being applied to a power supply voltage VCC end of the controller, the sum of the strong pull-down current Isd and the working current of the controller when entering the under-voltage locking state is larger than the power supply current provided by peripheral power supply, and a voltage stabilizing capacitor corresponding to the power supply voltage VCC end of the controller discharges to reduce the power supply voltage VCC; when the supply voltage VCC drops to a strong pull-down turn-off threshold voltage (V) as a characteristic _SD-OPEN1 ) The timing control signal drives the feedback circuit (24) to stop generating the strong pull-down current Isd, wherein the strong pull-down turns off a threshold voltage (Vpull-off) _SD-OPEN1 ) Less than the under-voltage lockout threshold voltage (V) _UVLOL ) (ii) a When the supply voltage VCC is raised to a strong pull-down turn-on threshold voltage (V) as a representation _SD-CLOSE ) The timing control signal drives the feedback circuit (24) to generate the strong pull-down current Isd, wherein the strong pull-down turns on a threshold voltage (V) _SD-CLOSE ) Less than or equal to the under-voltage lockout cancellation threshold voltage (V) _UVLOH )。

2. The circuit according to claim 1, wherein the sequential logic signal generating circuit (22) comprises: the POR detection circuit comprises a first selector (M1), a second selector (M2), a first comparator (C1), a second comparator (C2), a first inverter (P1), a first trigger (D1) and a power-on reset POR detection circuit (201);

the input ends of the first selector (M1), the second selector (M2) and the power-on reset POR detection circuit (201) are respectively connected with the voltage detection circuit (21);

the output end of the first selector (M1) is connected with the non-inverting input end of the first comparator (C1);

the first comparator (C)1) Is connected with the control terminal of the first selector (M1) and the logic operation circuit (23), the output terminal of the first comparator (C1) is further connected with the trigger terminal of the first flip-flop (D1) through the first inverter (P1), and the trigger terminal of the first flip-flop (D1)

The output end is connected with the logic operation circuit (23);

the EN end of the first comparator (C1) and the CLR end of the first trigger (D1) are both connected with the first control output end of the logic operation circuit (23);

the output end of the second selector (M2) is connected with the non-inverting input end of the second comparator (C2), and the control end of the second selector (M2) is connected with the output end of the second comparator (C2);

the output end of the second comparator (C2) is connected with the logic operation circuit (23); and

and the output end of the power-on reset POR detection circuit (201) is respectively connected with the EN end of the second comparator (C2) and the logic operation circuit (23).

3. The circuit according to claim 2, wherein the logical operation circuit (23) comprises: a first NAND gate (N1), a second NAND gate (N2), a second flip-flop (D2), a second inverter (P2) and a driver (Dr);

the first NAND gate (N1) is respectively connected with the output end of the first comparator (C1) and the first trigger (D1)

The output end of the first NAND gate (N1) is connected with the first input end of the second NAND gate (N2);

a second input end of the second NAND gate (N2) is connected with an output end of the second comparator (C2) and an input end of the second inverter (P2) in common;

the output end of the second inverter (P2) is connected with the trigger end of the second trigger (D2);

the CLR end of the second trigger (D2) is connected with the output end of the power-on reset POR detection circuit (201), and the CLR end of the second trigger (D2) is connected with the output end of the power-on reset POR detection circuit (201)

The output end of the first NAND gate is connected with the third input end of the second NAND gate (N2);

the Q output end of the second flip-flop (D2) is used as the first control output end;

the output end of the second NAND gate (N2) is connected with the input end of the driver (Dr), and the output end of the driver (Dr) is used as a second control output end and connected with the feedback circuit (24).

4. The circuit according to claim 3, characterized in that the first flip-flop (D1) and the second flip-flop (D2) each employ a D flip-flop.

5. The circuit of claim 1, wherein the strong pull-down turn-off threshold voltage (Vpull-off) _SD-OPEN1 ) Less than the under-voltage lockout threshold voltage (V) _UVLOL ) And is greater than the power-on reset voltage (V) _POR )。

6. The circuit according to any of claims 1-5, wherein the feedback circuit (24) comprises:

the control end of the electronic switch (T1) is connected with the output end of the logic operation circuit (23);

a feedback generation unit (202) connected to the electronic switch (T1).

7. The circuit according to claim 6, wherein the feedback generation unit (202) is a current source circuit (I) _load )。

8. The circuit according to claim 6, characterized in that the feedback generation unit (202) is a resistor (R) _load )。

9. The circuit according to claim 6, characterized in that the electronic switch (T1) is a field effect transistor.

10. An LED lighting device comprising the LED power-down processing circuit as claimed in any one of claims 1 to 9.

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