CN116095899A

CN116095899A - LED power-down processing method, circuit and LED lighting device

Info

Publication number: CN116095899A
Application number: CN202111296289.2A
Authority: CN
Inventors: 牟在鑫; 贺志伟
Original assignee: Meixinsheng Technology Beijing Co ltd
Current assignee: Meixinsheng Technology Beijing Co ltd
Priority date: 2021-11-03
Filing date: 2021-11-03
Publication date: 2023-05-09

Abstract

The application relates to an LED power-down processing method, an LED power-down processing circuit and an LED lighting device. The LED power-down processing method comprises the following steps: based on the power supply voltage VCC of the controller, after the controller enters an under-voltage locking state, the feedback circuit is controlled to generate a strong pull-down current Isd, the strong pull-down current Isd is applied to the power supply voltage VCC end of the controller, the sum of the strong pull-down current Isd and the working current of the controller when the controller enters the under-voltage locking state is larger than the power supply current provided by peripheral power supply, and a voltage stabilizing capacitor corresponding to the power supply voltage VCC is discharged, so that the input voltage VCC is reduced; when the power supply voltage VCC drops to a strong pull-down closing threshold voltage smaller than the undervoltage locking threshold voltage, the control feedback circuit stops generating the strong pull-down current Isd; when the power supply voltage VCC rises to a strong pull-down start threshold voltage less than or equal to the under-voltage lock cancellation threshold voltage, the control feedback circuit generates a strong pull-down current Isd.

Description

LED power-down processing method, circuit and LED lighting device

Technical Field

The application belongs to the technical field of LED power-down processing, and particularly relates to an LED power-down processing method, an LED power-down processing circuit and an LED lighting device.

Background

The LED lighting device has the advantages of low energy consumption, long service life, low pollution and the like, and is rapidly popularized in the lighting industry. Some LED lighting devices, after the power is turned off, may have a power-down back-flash problem that the LED lighting device is turned on again after the LED lighting device is turned off, and the following reasons are formed:

in the LED lighting device, the ac power source is rectified by the bridge rectifier, and then generates the dc line voltage VIN (see fig. 2) through the bus capacitor 4. After the power supply is disconnected, the LED lighting control circuit is powered off by the peripheral power supply, the LED lighting control circuit is turned off in an under-voltage locking state, the LED lighting control circuit is turned off in the under-voltage locking state, the LED lighting control circuit is LED to exit the under-voltage locking state by the peripheral power supply due to the fact that the working current of the LED lighting control circuit is reduced, the LED is restarted by starting working, the working current of the LED lighting control circuit is increased, the peripheral power supply cannot maintain the working of the LED lighting control circuit, the under-voltage locking state is again entered, the process is repeated, and the power-down flash is caused for a plurality of times until the electric quantity of the bus capacitor 4 is insufficient to support the starting of the LED lighting control circuit.

In practical application, the problem of power-down back flashing of the LED lighting device after the lamp is turned off and then turned on again can bring bad use experience to users.

Disclosure of Invention

Therefore, the application provides an LED power-down processing method, an LED power-down processing circuit and an LED lighting device, so as to solve the problem of back flash of the LED lighting device after power down.

In order to achieve the above purpose, the present application adopts the following technical scheme:

in a first aspect, the present application provides a method for processing power failure of an LED, where the method includes:

based on the power supply voltage VCC of a controller, after the controller enters an under-voltage locking state, a feedback circuit is controlled to generate a strong pull-down current Isd, wherein the strong pull-down current Isd is applied to a power supply voltage VCC end of the controller, the sum of the strong pull-down current Isd and working current when the controller enters the under-voltage locking state is larger than power supply current provided by peripheral power supply, and a voltage stabilizing capacitor corresponding to the power supply voltage VCC end of the controller discharges, so that the power supply voltage VCC is reduced;

when the power supply voltage VCC drops to a strong pull-down closing threshold voltage, controlling the feedback circuit to stop generating the strong pull-down current Isd, wherein the strong pull-down closing threshold voltage is smaller than an under-voltage locking threshold voltage;

when the power supply voltage VCC rises to a strong pull-down start threshold voltage, the feedback circuit is controlled to generate the strong pull-down current Isd, wherein the strong pull-down start threshold voltage is smaller than or equal to an under-voltage lock elimination threshold voltage.

Further, the strong pull-down off threshold voltage is less than the under-voltage lockout threshold voltage and greater than a power-on reset voltage.

Further, the method further comprises:

and when the power supply voltage VCC rises to exceed the undervoltage lock elimination threshold voltage, the controller releases the undervoltage lock state.

Further, the step of controlling the feedback circuit to generate the strong pull-down current Isd after the controller enters the under-voltage locking state based on the supply voltage VCC of the controller includes:

obtaining a preset number of various time sequence logic signals aiming at the power supply voltage VCC;

and performing logic operation on the plurality of time sequence logic signals, and controlling the feedback circuit to generate the strong pull-down current Isd after determining that a logic operation result represents that the controller enters an under-voltage locking state.

In a second aspect, the present application provides an LED power down processing circuit, comprising: the device comprises a voltage detection circuit, a sequential logic signal generation circuit, a logic operation circuit and a feedback circuit which are connected in sequence;

the voltage detection circuit is used for detecting the power supply voltage VCC of the controller;

the sequential logic signal generating circuit is used for generating various sequential logic signals according to the power supply voltage VCC;

the logic operation circuit is used for carrying out logic operation on the various time sequence logic signals to generate time sequence control signals, the time sequence control signals are used for driving the feedback circuit to generate strong pull-down current Isd after the controller is represented to enter an under-voltage locking state, the strong pull-down current Isd is used for being applied to a power supply voltage VCC end of the controller, the sum of the strong pull-down current Isd and working current when the controller enters the under-voltage locking state is larger than power supply current provided by peripheral power supply, and a voltage stabilizing capacitor corresponding to the power supply voltage VCC end of the controller is discharged, so that the power supply voltage VCC is reduced; when the power supply voltage VCC is characterized to be reduced to a strong pull-down closing threshold voltage, the time sequence control signal drives the feedback circuit to stop generating the strong pull-down current Isd, wherein the strong pull-down closing threshold voltage is smaller than an under-voltage locking threshold voltage; when the power supply voltage VCC is characterized to rise to a strong pull-down start threshold voltage, the time sequence control signal drives the feedback circuit to generate the strong pull-down current Isd, wherein the strong pull-down start threshold voltage is smaller than or equal to an under-voltage lock elimination threshold voltage.

Further, the sequential logic signal generating circuit includes: a first selector, a second selector, a first comparator, a second comparator, a first inverter, a first trigger and a power-on reset POR detection circuit;

the input ends of the first selector, the second selector and the power-on reset POR detection circuit are respectively connected with the voltage detection circuit;

the output end of the first selector is connected with the non-inverting input end of the first comparator;

the output end of the first comparator is commonly connected with the control end of the first selector and the logic operation circuit, the output end of the first comparator is also connected with the trigger end of the first trigger through the first inverter, and the output end of the first trigger is connected with the trigger end of the first trigger

The output end is connected with the logic operation circuit;

the EN end of the first comparator and the CLR end of the first trigger are connected with the first control output end of the logic operation circuit;

the output end of the second selector is connected with the non-inverting input end of the second comparator, and the control end of the second selector is connected with the output end of the second comparator;

the output end of the second comparator is connected with the logic operation circuit; and

and the output end of the power-on reset POR detection circuit is respectively connected with the EN end of the second comparator and the logic operation circuit.

Further, the logic operation circuit includes: a first NAND gate, a second flip-flop, a second inverter, and a driver;

the first NAND gate is respectively connected with the output end of the first comparator and the first trigger

The output end of the first NAND gate is connected with the first input end of the second NAND gate;

the second input end of the second NAND gate is commonly connected with the output end of the second comparator and the input end of the second inverter;

the output end of the second inverter is connected with the trigger end of the second trigger;

the CLR end of the second trigger is connected with the output end of the power-on reset POR detection circuit, and the CLR end of the second trigger is connected with the output end of the power-on reset POR detection circuit

The output end is connected with the third input end of the second NAND gate;

the Q output end of the second trigger is used as the first control output end;

the output end of the second NAND gate is connected with the input end of the driver, and the output end of the driver is used as a second control output end to be connected with the feedback circuit.

Further, the feedback circuit includes:

the control end of the electronic switch is connected with the output end of the logic operation circuit;

and the feedback generation unit is connected with the electronic switch.

Further, the feedback generation unit is a current source circuit or a resistor.

In a third aspect, the present application provides an LED lighting device, applying the LED power-down processing method as described in any one of the above.

In a fourth aspect, the present application provides an LED lighting device comprising the LED power down processing circuit as defined in any one of the above.

The application adopts the technical scheme, possesses following beneficial effect at least:

according to the scheme, based on the power supply voltage VCC of the controller, after the controller enters an under-voltage locking state, the feedback circuit is controlled to generate a strong pull-down current Isd, after the strong pull-down current Isd is applied to the power supply voltage VCC end of the controller, the sum of working currents when the strong pull-down current Isd and the controller enter the under-voltage locking state is larger than the power supply current provided by peripheral power supply, the voltage stabilizing capacitor corresponding to the power supply voltage VCC end of the controller discharges, so that the power supply voltage VCC drops, when the power supply voltage VCC drops to be smaller than the strong pull-down closing threshold voltage of the under-voltage locking threshold voltage, the feedback circuit is controlled to stop generating the strong pull-down current Isd, and the power supply current provided by the peripheral power supply is larger than the working current of the controller in the state at the moment, that is, the peripheral power supply charges the voltage stabilizing capacitor corresponding to the power supply voltage VCC end of the controller at the moment, and the power supply voltage VCC rises. When the power supply voltage VCC rises to be smaller than or equal to the strong pull-down starting threshold voltage of the undervoltage locking elimination threshold voltage, the feedback circuit is controlled to generate strong pull-down current Isd, at the moment, the power supply current provided by peripheral power supply is smaller than the sum of the strong pull-down current Isd and the working current of the controller in the state, the voltage stabilizing capacitor corresponding to the power supply voltage VCC end of the controller discharges, so that the power supply voltage VCC drops, the process is repeated for a plurality of times, the electric quantity in the bus capacitor behind the bridge can be discharged, and meanwhile, the controller is always in the undervoltage locking state, so that the problem of the power-down back flash which is lightened again after the LED lamp is turned off can be avoided, and the LED lighting use experience of a user can be guaranteed.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a flow chart illustrating a method of LED power down processing according to an exemplary embodiment;

FIG. 2 is a block diagram schematic diagram of an LED power down processing circuit, shown according to an exemplary embodiment;

FIG. 3 is a schematic diagram illustrating a power down process implemented with sequential logic signals, according to an example embodiment;

FIG. 4 is a schematic diagram of an LED power down processing circuit implementation shown in accordance with an exemplary embodiment;

fig. 5 is a schematic diagram of an implementation of an LED power down processing circuit, shown according to another exemplary embodiment.

In the figure:

2-LED power-down processing circuit; 3-a controller; 4-bus capacitance; 5-a peripheral power module; 6-voltage stabilizing capacitor;

21-a voltage detection circuit; 22-a sequential logic signal generating circuit 22; 23-a logic operation circuit; a 24-feedback circuit;

m1-a first selector; m2-a second selector; c1-a first comparator; a C2-second comparator; p1-a first inverter; d1—a first flip-flop; n1-a first NAND gate; n2-a second NAND gate; d2—a second flip-flop; p2-a second inverter; dr-driver; t1-electronic switch; i _load -a current source circuit; r is R _load -a resistance;

201-a power-on reset POR detection circuit; 202-a feedback generation unit.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be described in detail below. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, based on the examples herein, which are within the scope of the protection sought by those of ordinary skill in the art without undue effort, are intended to be encompassed by the present application.

Referring to fig. 1, fig. 1 is a flowchart illustrating a method of processing power down of an LED according to an exemplary embodiment, the method being applied to an LED lighting device, the method including the steps of:

step S11, based on the power supply voltage VCC of a controller, after the controller enters an under-voltage locking state, a feedback circuit is controlled to generate a strong pull-down current Isd, wherein the strong pull-down current Isd is applied to a power supply voltage VCC end of the controller, the sum of the strong pull-down current Isd and working current when the controller enters the under-voltage locking state is larger than power supply current provided by peripheral power supply, and a voltage stabilizing capacitor 6 corresponding to the power supply voltage VCC end of the controller discharges, so that the power supply voltage VCC is reduced;

step S12, when the power supply voltage VCC drops to the strong pull-down closing threshold voltage V _SD-OPEN1 When the feedback circuit is controlled to stop generating the strong pull-down current Isd, wherein the strong pull-down turns off the threshold voltage V _SD-OPEN1 Less than the undervoltage lockout threshold voltage V _UVLOL ；

Step S13, when the power supply voltage VCC rises to the strong pull-down start threshold voltage V _SD-CLOSE When the feedback circuit is controlled to generate the strong pull-down current Isd, wherein the strong pull-down start threshold voltage V _SD-CLOSE Less than or equal to the under-voltage lock-out cancellation threshold voltage V _UVLOH 。

Referring specifically to fig. 2 and 3, fig. 2 and 3 are specific applications for implementing the above method. In practical application, when the LED lighting device is in a lighting state, the bus capacitor 4 stores electric quantity, after the LED lighting device enters a power-down state, the situation that the bus capacitor 4 releases the electric quantity occurs, the controller 3 is powered by peripheral power supply, the working current of the controller 3 in normal work is large, the peripheral power supply cannot maintain the LED lighting control circuit in work in the state, and the voltage-stabilizing capacitor corresponding to the power supply voltage VCC end of the controller is discharged, so that the power supply voltage VCC of the controller 3 is pulled down.

Referring to FIG. 2, the voltage drop below the under-voltage-lock threshold voltage (V in FIG. 3) _UVLOL ) After that, the controller 3 enters an under-voltage locking state, the control feedback circuit 24 generates a strong pull-down current Isd, after the strong pull-down current Isd is applied to the power supply voltage VCC end of the controller 3, the sum of the strong pull-down current Isd and the working current when the controller 3 enters the under-voltage locking state is greater than the power supply current provided by peripheral power supply, and the voltage stabilizing capacitor 6 corresponding to the power supply voltage VCC end of the controller 3 discharges, so that the power supply voltage VCC is reduced.

In the present application, the strong pull-down closes the threshold voltage (V in fig. 3 _SD-OPEN1 ) For indicating a strong pull-down current Isd to be released when the supply voltage VCC falls to a strong pull-down off threshold voltage V _SD-OPEN1 When the controller 3 is in this state, the control feedback circuit 24 is triggered to stop generating the strong pull-down current Isd, and the peripheral power supply supplies a power supply current greater than the working current of the controller 3, and the peripheral power supply charges the voltage stabilizing capacitor 6 corresponding to the power supply voltage VCC terminal of the controller 3, so that the power supply voltage VCC rises. In practical application, after the LED lighting control circuit enters the under-voltage locking state, since the working current of the LED lighting control circuit is reduced, the supply current provided by the bus capacitor 4 after the bridge through the peripheral power supply is greater than the working current of the controller 3 in the state, and at this time, the peripheral power supply charges the voltage stabilizing capacitor 6 corresponding to the supply voltage VCC end of the controller 3, so that the supply voltage VCC rises. When the supply voltage VCC rises above the under-voltage latch-up elimination threshold voltage (V in FIG. 3 _UVLOH ) The operation is started to re-illuminate the LED, resulting in a flashback.

In the present application, the pull-down threshold voltage (V in FIG. 3 _SD-CLOSE ) The strong pull-down threshold voltage V _SD-CLOSE For indicating reapplication of the strong pull-down current Isd to ensure that the under-voltage locking state is not released, and increasing the power supply voltage VCC to the strong pull-down start threshold voltage V _SD-CLOSE In the time-course of which the first and second contact surfaces,the trigger control feedback circuit 24 generates a strong pull-down current Isd to prevent the problem that the power supply voltage VCC rises to cause trigger release of the under-voltage lock and cause power failure and back flash. The power supply device can discharge the electric quantity in the bus capacitor 4 by repeating the above process for a plurality of times, so that the problem of power-down back flash is solved, and the LED lighting experience of a user is further guaranteed.

For the above scheme, referring to fig. 3, the following technical effect can be achieved, when the bus capacitor 4 after the bridge supplies power to the controller 3 through the peripheral power supply, the peripheral power supply provides a power supply current smaller than the working current of the controller 3 in the under-voltage locking state, and the voltage stabilizing capacitor 6 corresponding to the power supply voltage VCC terminal of the controller 3 discharges at this time, so that the power supply voltage VCC of the controller is reduced to be lower than V _POR And when the circuit is in power-down reset, the quick power-up starting again is not influenced.

In one embodiment, referring to FIG. 3, the strong pull-down closes the threshold voltage V _SD-OPEN1 Less than the under-voltage lockout threshold voltage V _UVLOL And is greater than the power-on reset voltage V _POR . Under this scheme, during the power failure, realized the electric energy to behind the bridge busbar electric capacity 4 and released, guaranteed simultaneously that controller 3 is in non-start operating condition, solved the power failure back flashing problem. Referring to fig. 3, the controller 3 can be started normally by the scheme of the present application after the first power-down and the subsequent hot start. Meanwhile, after power-down reset, the scheme does not influence the starting speed of the controller 3.

In one embodiment, the method further comprises: at the power supply voltage VCC rising above the under-voltage lock-out cancellation threshold voltage V _UVLOH The controller 3 releases the under-voltage lock state. I.e. when the supply voltage VCC is greater than the under-voltage lockout elimination threshold voltage V _UVLOH When the controller 3 is in the under-voltage locking state, the controller is switched to the normal working state.

In one embodiment, powered up during power down, the constraint control threshold voltage (V may be increased for the supply voltage VCC of the controller 3 _{SD_OPEN2} ). Specifically, the threshold voltage V is pulled down by a strong pull-down _SD-CLOSE With undervoltage locking cancellationDividing the threshold voltage V _UVLOH Between increasing the constraint control threshold voltage V _{SD_OPEN2} The method comprises the steps of carrying out a first treatment on the surface of the During the power-down period, the power supply voltage VCC of the controller 3 is increased to the strong pull-down start threshold voltage V _SD-CLOSE At this time, the strong pull-down is turned on, if the power supply voltage VCC of the controller 3 continues to increase to the constraint control threshold voltage V _{SD_OPEN2} And closing the strong pull-down, thereby realizing quick start of power-up during power-down. In addition, during the period that the bus capacitor 4 behind the bridge supplies power to the controller 3 through peripheral power supply, the power supply current provided by the peripheral power supply is smaller than the working current of the controller 3 in the under-voltage locking state, and at the moment, the voltage stabilizing capacitor 6 corresponding to the power supply voltage VCC end of the controller 3 discharges, so that the power supply voltage VCC of the controller is reduced to be lower than V _POR And when the circuit is in power-down reset, the quick power-up starting again is not influenced.

In one embodiment, the step of controlling the feedback circuit to generate the strong pull-down current Isd after the controller enters the under-voltage lockout state includes:

and performing logic operation on the plurality of time sequence logic signals, and controlling the feedback circuit to generate the strong pull-down current Isd after determining that the logic operation result represents that the controller 3 enters an under-voltage locking state.

Referring to fig. 3, fig. 3 shows that four sequential logic signals of CTR1, CTR2, FLAG and CTR3 are obtained according to a power supply voltage VCC of the controller 3, and then the four sequential logic signals are subjected to logic operation to obtain a logic operation result sd_ctr shown in fig. 3, where the sd_ctr is also embodied in the form of a sequential logic signal, and when the controller 3 is represented to enter an under-voltage locking state, a control signal is represented by a high level, and the feedback circuit 24 is controlled to generate the strong pull-down current Isd.

In the application, an LED lighting device is further provided, so that the LED power-down processing method is applied to any one of the above.

For the LED lighting device, the above-mentioned method for processing the power failure of the LED is applied to solve the problem of power-down back flash that is avoided to be re-lightened after the lamp is turned off, and the method is described in detail in the above-mentioned embodiments, and will not be described in detail here.

Referring to fig. 2, the present application further provides an LED power-down processing circuit, including: a voltage detection circuit 21, a sequential logic signal generation circuit 22, a logic operation circuit 23, and a feedback circuit 24 connected in this order;

the voltage detection circuit 21 is used for detecting the power supply voltage VCC of the controller;

the sequential logic signal generating circuit 22 is configured to generate a plurality of sequential logic signals according to the supply voltage VCC;

the logic operation circuit 23 is configured to perform logic operation on the plurality of time-sequence logic signals to generate a time-sequence control signal, where the time-sequence control signal is configured to drive the feedback circuit 24 to generate a strong pull-down current Isd after the controller is represented to enter an under-voltage locking state, where the strong pull-down current Isd is used to be applied to a power supply voltage VCC terminal of the controller, and a sum of working currents of the strong pull-down current Isd and the controller when the controller enters the under-voltage locking state is greater than a power supply current provided by peripheral power supply, and a voltage stabilizing capacitor 6 corresponding to the power supply voltage VCC terminal of the controller is discharged, so that the power supply voltage VCC is reduced; thereafter, when the supply voltage VCC is characterized to drop to the strong pull-down off threshold voltage V _SD-OPEN1 When the timing control signal drives the feedback circuit 24 to stop generating the strong pull-down current Isd, the strong pull-down turns off the threshold voltage V _SD-OPEN1 Less than the undervoltage lockout threshold voltage V _UVLOL The method comprises the steps of carrying out a first treatment on the surface of the When the power supply voltage VCC is characterized to rise to the strong pull-down start threshold voltage V _SD-CLOSE When the timing control signal drives the feedback circuit 24 to generate the strong pull-down current Isd, the strong pull-down start threshold voltage V _SD-CLOSE Less than or equal to the under-voltage lock-out cancellation threshold voltage V _UVLOH 。

Referring to the LED lighting device shown in fig. 2, after the ac power source is rectified by the bridge stack, a dc line voltage VIN is generated on the bus capacitor 4 and is sent to the peripheral power supply module 5, and the peripheral power supply module 5 supplies power to the controller 3. For the realization of both functions of the sequential logic signal generating circuit 22 and the logic operation circuit 23, please refer to fig. 3 in conjunction with the sequential logic signal control, fig. 3 shows that four sequential logic signals of CTR1, CTR2, FLAG and CTR3 are obtained according to the supply voltage VCC of the controller 3, and then the four sequential logic signals are subjected to logic operation to obtain the logic operation result sd_ctr shown in fig. 3, i.e. the sequential control signal, which is also embodied in the form of the sequential logic signal, the high level driving feedback circuit 24 generates the strong pull-down current Isd, for which the function is described in detail in the related embodiments, and will not be described in detail herein.

The peripheral supply module 5 shown in fig. 2 may be implemented, but is not limited to, by a start-up resistor to provide the voltage required at the supply voltage VCC terminal of the controller 3. The voltage detection circuit 21 is configured to detect the supply voltage VCC of the controller 3, and for the voltage detection module 21, a conventional resistor voltage division manner may be adopted, or other conventional voltage detection manners may be adopted.

In one embodiment, the strong pulldown closes threshold voltage V _SD-OPEN1 Less than the undervoltage lockout threshold voltage V _UVLOL And is greater than the power-on reset voltage V _POR 。

Referring to fig. 3, fig. 3 shows four sequential logic signals of CTR1, CTR2, FLAG and CTR3 obtained according to a power supply voltage VCC of the controller 3, and fig. 3 shows a sequential control signal sd_ctr obtained under four sequential logic signals of CTR1, CTR2, FLAG and CTR3, which can represent a strong pull-down off threshold voltage V _SD-OPEN1 Less than the undervoltage lockout threshold voltage V _UVLOL And is greater than the power-on reset voltage V _POR . Under this scheme, during the power failure, realized the electric energy to behind the bridge busbar electric capacity 4 and released, guaranteed simultaneously that controller 3 is in non-start operating condition, solved the power failure back flashing problem. Referring to fig. 3, the controller 3 can be started normally by the scheme of the present application after the first power-down and the subsequent hot start. Meanwhile, after power-down reset, the scheme does not influence the starting speed of the controller 3.

Further, referring to fig. 4, in one embodiment, the sequential logic signal generating circuit 22 includes: a first selector M1, a second selector M2, a first comparator C1, a second comparator C2, a first inverter P1, a first flip-flop D1, and a power-on reset POR detection circuit 201;

the input ends of the first selector M1, the second selector M2 and the power-on reset POR detection circuit 201 are respectively connected with the voltage detection circuit 21;

the output end of the first selector M1 is connected with the non-inverting input end of the first comparator C1;

the output end of the first comparator C1 is commonly connected with the control end of the first selector M1 and the logic operation circuit 23, the output end of the first comparator C1 is also connected with the trigger end of the first trigger D1 through the first inverter P1, and the first trigger D1

The output end is connected with the logic operation circuit 23;

the EN end of the first comparator C1 and the CLR end of the first flip-flop D1 are both connected to the first control output end of the logic operation circuit 23;

the output end of the second selector M2 is connected with the non-inverting input end of the second comparator C2, and the control end of the second selector M2 is connected with the output end of the second comparator C2;

the output end of the second comparator C2 is connected with the logic operation circuit 23; and

the output end of the power-on reset POR detection circuit 201 is connected to the EN end of the second comparator C2 and the logic operation circuit 23, respectively.

Specifically, the above embodiment of the sequential logic signal generating circuit 22 is configured to generate four sequential logic signals of CTR1, CTR2, FLAG and CTR3 shown in fig. 3, where the output end of the first comparator C1 is connected to the logic operation circuit 23 to output a first sequential logic signal to the logic operation circuit 23, and the first sequential logic signal corresponds to the CTR3 shown in fig. 3; the Q output end of the first flip-flop D1 is connected to the logic operation circuit 23, so as to output a second sequential logic signal to the logic operation circuit 23, where the second sequential logic signal corresponds to the FLAG; the output end of the second comparator C2 is connected to the logic operation circuit 23, so as to output a third sequential logic signal to the logic operation circuit 23, where the third sequential logic signal corresponds to CTR2 shown in fig. 3; the output end of the power-on reset POR detection circuit 202 is connected to the logic operation circuit 23, so as to output a fourth timing logic signal to the logic operation circuit 23, where the fourth timing logic signal corresponds to CTR1 shown in fig. 3.

Further, referring to fig. 4, in one embodiment, the logic operation circuit 23 includes: a first nand gate N1, a second nand gate N2, a second flip-flop D2, a second inverter P2, and a driver Dr;

the first NAND gate N1 is respectively connected with the output end of the first comparator C1 and the first trigger D1

The output end is connected with the first input end of the second NAND gate N2; />

The second input end of the second NAND gate N2 is commonly connected with the output end of the second comparator C2 and the input end of the second inverter P2;

the output end of the second inverter P2 is connected with the trigger end of the second trigger D2;

the CLR end of the second trigger D2 is connected to the output end of the power-on reset POR detection circuit 201, and the Q output end of the second trigger D2 is connected to the third input end of the second nand gate N2;

the Q output end of the second trigger D2 is used as the first control output end;

the output end of the second nand gate N2 is connected to the input end of the driver Dr, and the output end of the driver Dr is connected to the feedback circuit 24 as a second control output end.

Specifically, the above-mentioned embodiment of the logic operation circuit 23 is configured to perform a logic operation on four sequential logic signals of CTR1, CTR2, FLAG and CTR3 shown in fig. 3, to obtain a logic operation result sd_ctr shown in fig. 3, where the sd_ctr is also embodied in the form of a sequential logic signal, and the high level driving feedback circuit 24 generates a strong pull-down current Isd that blocks the bus capacitor 4 from supplying power to the controller 3.

As for the first flip-flop D1 and the second flip-flop D2 in the above embodiments, in practical applications, D flip-flops may be employed, but are not limited to.

Referring to fig. 4 and 5, in one embodiment, the feedback circuit 24 includes:

the control end of the electronic switch T1 is connected with the output end of the logic operation circuit 23;

the feedback generation unit 202 is connected to the electronic switch T1.

Specifically, the electronic switch T1 may be implemented by, but not limited to, a field effect transistor, as shown in fig. 4, which is used as the electronic switch T1. After the electronic switch T1 is turned on, the feedback circuit 24 forms a path, and the feedback generation unit 202 generates a strong pull-down current Isd for being applied to the power supply voltage VCC terminal of the controller 3 to block the bus capacitor 4 from supplying power to the controller 3.

Referring to fig. 4, further, for the feedback generation unit 202, it may be a current source circuit I _load 。

This scheme is described below. In practical application, the current source circuit I _load The electric energy can be obtained and stored by the LED illumination when the power is normally supplied. After the electronic switch T1 is turned on, the feedback circuit 24 forms a path, and the current source circuit I _load The generated feedback current is applied to the supply voltage VCC terminal of the controller 3, and the sum of the feedback current and the operating current when the controller 3 enters the under-voltage lockout state is greater than the supply current provided by the peripheral supply, so that the bus capacitor 4 does not supply power to the controller 3.

Referring to fig. 5, further, for the feedback generation unit 202, it may be a resistor R _load 。

After the electronic switch T1 is turned on, feedbackThe circuit 24 forms a path, resistor R _load And after the strong pull-down current Isd is applied to the power supply voltage VCC end of the controller 3, the sum of the strong pull-down current Isd and the working current when the controller 3 enters the under-voltage locking state is larger than the power supply current provided by peripheral power supply, so that the bus capacitor 4 does not supply power to the controller 3.

The application provides an LED lighting device, comprising the LED power-down processing circuit according to any one of the above. For the LED lighting device, the LED power-down processing circuit of any one of the above is applied to solve the problem of power-down back flash that is avoided to be re-lightened after the lamp is turned off, and the circuit is described in detail in the above embodiments related to this, and will not be described in detail here.

It is to be understood that the same or similar parts in the above embodiments may be referred to each other, and that in some embodiments, the same or similar parts in other embodiments may be referred to.

It should be noted that in the description of the present application, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Furthermore, in the description of the present application, unless otherwise indicated, the meaning of "plurality", "multiple" means at least two.

It will be understood that when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or intervening elements may also be present; when an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may be present, and further, as used herein, connection may comprise a wireless connection; the use of the term "and/or" includes any and all combinations of one or more of the associated listed items.

Any process or method description in a flowchart or otherwise described herein may be understood as: means, segments, or portions of code representing executable instructions including one or more steps for implementing specific logical functions or processes are included in the preferred embodiments of the present application, in which functions may be executed out of order from that shown or discussed, including in a substantially simultaneous manner or in an inverse order, depending upon the functionality involved, as would be understood by those skilled in the art to which the embodiments of the present application pertains.

It is to be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, may be implemented using any one or combination of the following techniques, as is well known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.

Those of ordinary skill in the art will appreciate that all or a portion of the steps carried out in the method of the above-described embodiments may be implemented by a program to instruct related hardware, where the program may be stored in a computer readable storage medium, and where the program, when executed, includes one or a combination of the steps of the method embodiments.

In addition, each functional unit in each embodiment of the present application may be integrated in one processing module, or each unit may exist alone physically, or two or more units may be integrated in one module. The integrated modules may be implemented in hardware or in software functional modules. The integrated modules may also be stored in a computer readable storage medium if implemented in the form of software functional modules and sold or used as a stand-alone product.

The above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, or the like.

In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Although embodiments of the present application have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the application, and that variations, modifications, alternatives, and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the application.

Claims

1. A method for processing power failure of an LED, the method comprising:

when the supply voltage VCC drops to a strong pull-down off threshold voltage (V _SD-OPEN1 ) When the feedback circuit is controlled to stop generating the strong pull-down current Isd, wherein the strong pull-down turns off the threshold voltage (V _SD-OPEN1 ) Less than the under-voltage lockout threshold voltage (V) _UVLOL )；

When the supply voltage VCC rises to a strong pull-down start threshold voltage (V _SD-CLOSE ) When the feedback circuit is controlled to generate the strong pull-down current Isd, wherein the strong pull-down start threshold voltage (V _SD-CLOSE ) Less than or equal to the under-voltage latch-up elimination threshold voltage (V _UVLOH )。

2. The method according to claim 1The method is characterized in that the strong pull-down is turned off at a threshold voltage (V _SD-OPEN1 ) Less than the under-voltage lockout threshold voltage (V _UVLOL ) And is greater than the power-on reset voltage (V _POR )。

3. The method according to claim 1, wherein the method further comprises:

when the power supply voltage VCC rises above the under-voltage lock-out cancellation threshold voltage (V _UVLOH ) And the controller releases the under-voltage locking state.

4. A method according to any one of claims 1-3, wherein the step of controlling the feedback circuit to generate a strong pull-down current Isd after the controller enters the under-voltage lockout state based on the supply voltage VCC of the controller comprises:

5. An LED power down processing circuit, comprising: a voltage detection circuit (21), a sequential logic signal generation circuit (22), a logic operation circuit (23) and a feedback circuit (24) which are connected in sequence;

the voltage detection circuit (21) is used for detecting the power supply voltage VCC of the controller;

the sequential logic signal generating circuit (22) is used for generating various sequential logic signals according to the power supply voltage VCC;

the logic operation circuit (23) is used for performing logic operation on the various time sequence logic signals to generate time sequence control signals, the time sequence control signals are used for driving the feedback circuit (24) to generate strong pull-down current Isd after the controller is characterized to enter an undervoltage locking state, wherein the strong pull-down current Isd is used for being applied to a power supply voltage VCC end of the controllerThe sum of the strong pull-down current Isd and the working current of the controller in the under-voltage locking state is larger than the supply current provided by peripheral power supply, and the voltage stabilizing capacitor corresponding to the supply voltage VCC end of the controller discharges, so that the supply voltage VCC is reduced; when the supply voltage VCC is characterized as falling to a strong pull-down off threshold voltage (V _SD-OPEN1 ) The timing control signal drives the feedback circuit (24) to stop generating the strong pull-down current Isd, wherein the strong pull-down turns off a threshold voltage (V _SD-OPEN1 ) Less than the under-voltage lockout threshold voltage (V) _UVLOL ) The method comprises the steps of carrying out a first treatment on the surface of the When the supply voltage VCC is characterized as rising to a strong pull-down start threshold voltage (V _SD-CLOSE ) The timing control signal drives the feedback circuit (24) to generate the strong pull-down current Isd, wherein the strong pull-down start threshold voltage (V _SD-CLOSE ) Less than or equal to the under-voltage latch-up elimination threshold voltage (V _UVLOH )。

6. The circuit of claim 5, wherein the sequential logic signal generation circuit (22) comprises: a first selector (M1), a second selector (M2), a first comparator (C1), a second comparator (C2), a first inverter (P1), a first flip-flop (D1), and a power-on reset POR detection circuit (201);

the input ends of the first selector (M1), the second selector (M2) and the power-on reset POR detection circuit (201) are respectively connected with the voltage detection circuit (21);

the output end of the first selector (M1) is connected with the non-inverting input end of the first comparator (C1);

the output end of the first comparator (C1) is commonly connected with the control end of the first selector (M1) and the logic operation circuit (23), the output end of the first comparator (C1) is also connected with the trigger end of the first trigger (D1) through the first inverter (P1), and the first trigger (D1)

The output end is connected with the logic operation circuit (23);

the EN end of the first comparator (C1) and the CLR end of the first trigger (D1) are connected with the first control output end of the logic operation circuit (23);

the output end of the second selector (M2) is connected with the non-inverting input end of the second comparator (C2), and the control end of the second selector (M2) is connected with the output end of the second comparator (C2);

the output end of the second comparator (C2) is connected with the logic operation circuit (23); and

the output end of the power-on reset POR detection circuit (201) is respectively connected with the EN end of the second comparator (C2) and the logic operation circuit (23).

7. The circuit according to claim 6, characterized in that the logic operation circuit (23) comprises: a first NAND gate (N1), a second NAND gate (N2), a second flip-flop (D2), a second inverter (P2), and a driver (Dr);

the first NAND gate (N1) is connected with the output end of the first comparator (C1) and the first trigger (D1) respectively

The output end is connected with the first input end of the second NAND gate (N2), and the output end of the first NAND gate (N1) is connected with the first input end of the second NAND gate;

a second input end of the second NAND gate (N2) is commonly connected with an output end of the second comparator (C2) and an input end of the second inverter (P2);

the output end of the second inverter (P2) is connected with the trigger end of the second trigger (D2);

the CLR end of the second trigger (D2) is connected with the output end of the power-on reset POR detection circuit (201), and the second trigger (D2)

The output end is connected with the third input end of the second NAND gate (N2);

the Q output of the second flip-flop (D2) is used as the first control output;

the output end of the second NAND gate (N2) is connected with the input end of the driver (Dr), and the output end of the driver (Dr) is used as a second control output end to be connected with the feedback circuit (24).

8. The circuit of claim 5, wherein the strong pull-down shutdown threshold voltage (V _SD-OPEN1 ) Less than the under-voltage lockout threshold voltage (V _UVLOL ) And is greater than the power-on reset voltage (V _POR )。

9. The circuit according to any one of claims 5-8, wherein the feedback circuit (24) comprises:

the control end of the electronic switch (T1) is connected with the output end of the logic operation circuit (23);

and a feedback generation unit (202) connected to the electronic switch (T1).

10. The circuit according to claim 9, wherein the feedback generation unit (202) is a current source circuit (I _load ) Or resistance (R) _load )。

11. An LED lighting device characterized by applying the LED power-down processing method according to any one of claims 1 to 4.

12. An LED lighting device comprising the LED power down processing circuit of any one of claims 5-10.