CN220934861U

CN220934861U - Prevent BMS wake-up circuit of reverse connection

Info

Publication number: CN220934861U
Application number: CN202322606033.8U
Authority: CN
Inventors: 何俊青
Original assignee: Poweroad Xiamen Renewable Energy Technology Co ltd
Current assignee: Fujian Liangdao New Energy Development Co.,Ltd.
Priority date: 2023-09-25
Filing date: 2023-09-25
Publication date: 2024-05-10
Anticipated expiration: 2033-09-25

Abstract

The utility model discloses a reverse connection preventing BMS wake-up circuit, which comprises a first input end, a first output end, a second output end, a bridge rectifier circuit and an optical coupler, wherein the first input end is connected with the first output end; the two ends of the first input end are connected with the two ends of the input end of the bridge rectifier circuit and are used for inputting wake-up signals; and two ends of the output end of the bridge rectifier circuit are connected with two ends of the input end of the optocoupler after passing through the current limiting resistor to form a control loop. The bridge rectifier circuit is adopted to prevent reverse design, the optocoupler is adopted to carry out input and output isolation design, and the safety problem caused by the fact that a user carelessly connects the anode and the cathode to the device to damage the device in the using process is avoided.

Description

Prevent BMS wake-up circuit of reverse connection

Technical Field

The utility model relates to the field of battery management systems, in particular to a BMS wake-up circuit capable of preventing reverse connection.

Background

With the development of new energy, the application function of a BMS (battery management system) is becoming more and more complex in order to meet the application demands of users. Facing more and more functions of the BMS, a good experience needs to be given to the user.

At present, in the aspect of BMS startup awakening, the BMS can be awakened by a direct current power supply, and also can be directly awakened.

In the aspect of a wake-up circuit, the current BMS battery management system generally does not have excessive processing, and only the colors of positive and negative interfaces of the wake-up circuit are obviously distinguished. The user can carelessly connect the positive electrode and the negative electrode in the using process, so that the device can be damaged, even the safety problem is caused by short circuit, and the potential safety hazard to the use safety of the user is great.

Disclosure of utility model

In order to solve the problems, the utility model provides the BMS wake-up circuit capable of preventing reverse connection, which can be started normally and has no influence on the BMS even if a user carelessly reverse-connects the positive electrode and the negative electrode of a power supply.

The technical proposal is as follows:

a BMS wake-up circuit capable of preventing reverse connection comprises a first input end, a first output end, a second output end, a bridge rectifier circuit and an optical coupler;

The two ends of the first input end are connected with the two ends of the input end of the bridge rectifier circuit and are used for inputting wake-up signals;

The two ends of the output end of the bridge rectifier circuit are connected with the two ends of the input end of the optocoupler after passing through the current limiting resistor to form a control loop;

The positive electrode of the output end of the optocoupler is connected with the first output end through a resistor and a first diode; and is connected with the second output end through a second diode; the negative electrode of the output end of the optocoupler is grounded; the anode of the first diode is connected with the first output end, and the anode of the second diode is connected with the second output end;

the first output end is connected with the control end of the power supply circuit of the BMS and is used for waking up or turning off the power supply circuit;

The second output terminal is pulled up and connected with the controller of the BMS and used for outputting a wake-up circuit detection signal.

Furthermore, the control loop is also connected with a voltage stabilizing tube in series.

Further, the BMS wake-up circuit further comprises a power-on holding circuit, the power-on holding circuit is an inverter circuit, the input end of the power-on holding circuit is connected with a controller of the BMS, and the output end of the power-on holding circuit is connected with the first output end.

Further, the power-on holding circuit comprises a semiconductor switching tube, a first resistor, a second resistor and a first capacitor, and the input end of the power-on holding circuit is connected with the control end of the semiconductor switching tube through the first resistor, the first capacitor and the control end of the semiconductor switching tube which are connected in parallel; the control end of the semiconductor switching tube is grounded through a second resistor; the output end of the semiconductor switching tube outputs a power supply control signal; the input end of the semiconductor switch tube is grounded.

Further, the power-on holding circuit is driven by the controller, and the controller comprises a logic unit, a first input pin and a first output pin; when the logic unit inputs a falling edge trigger signal to a first input pin, the logic unit outputs a high-level signal to the first output pin and keeps the high-level signal; the first input pin is connected with the second output end; the first output pin is connected with the input end of the power-on holding circuit.

The utility model realizes the following technical effects:

The BMS wake-up circuit increases the anti-reflection design and the isolation design, and avoids the safety problem caused by the fact that a user carelessly connects the anode and the cathode to the device to damage the device in the using process.

Drawings

Fig. 1 is a circuit diagram of a BMS wakeup circuit of the present utility model;

Fig. 2 is a circuit diagram of a power-on hold circuit of the present utility model.

Detailed Description

For further illustration of the various embodiments, the utility model is provided with the accompanying drawings. The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate embodiments and together with the description, serve to explain the principles of the embodiments. With reference to these matters, one of ordinary skill in the art will understand other possible embodiments and advantages of the present utility model.

The utility model will now be further described with reference to the drawings and detailed description.

As shown in fig. 1, the utility model discloses a reverse connection preventing BMS wake-up circuit, which comprises a bridge rectifier circuit and an optical coupler.

The bridge rectifier circuit can be composed of a separated diode, a full bridge or a half bridge, and the reverse connection function is realized. As shown in fig. 1, is composed of two half-bridges D88 and D89.

Positive and negative input terminals chg_weak+/chg_weak of the BMS wake-up circuit are respectively connected with two input terminals of the bridge rectifier circuit. The positive electrode of the output end of the bridge rectifier circuit is connected with the positive electrode of the light-emitting diode of the input end of the optocoupler P5 through a resistor R279; the cathode of the output end is connected with the cathode of the light emitting diode of the input end of the optocoupler P5 to form a control loop.

In the control loop, a voltage stabilizing tube D10 can be connected in series, so that an effective (meeting the voltage requirement) wake-up signal is input to an input port of the BMS wake-up circuit.

The positive electrode of the output end of the optocoupler P5 is connected to the cathode of the first diode D84 through a resistor R272, and the anode of the first diode D84 is connected with a power supply control signal POW_CTRL;

The positive electrode of the output end of the optocoupler P5 is also connected with the cathode of a second diode D85, and the anode of the second diode D85 is connected with a wake-up circuit detection signal PB0_CHG_CHECK.

In a specific application, when a direct current (with any polarity) is input between chg_weak+/chg_weak-, the optocoupler P5 can work normally, and the wake-up circuit detection signal pb0_chg_check and the power control signal pow_ctrl are pulled down.

And when the power supply control signal POW_CTRL is pulled down, the power supply circuit works and is in a starting state, the working power supply required by the work of the controller is output, and the controller is electrified.

The power supply circuit operates to require the power control signal pow_ctrl to remain in a pulled-down state.

The input between CHG_WEAK+/CHG_WEAK is a direct current power supply or a start pulse signal. For this reason, it is necessary to keep the power control signal pow_ctrl in a pulled-down state after the BMS wakes up.

In order to maintain the power control signal pow_ctrl in a pulled-down state, the BMS is provided with a power-on maintaining circuit, and after the BMS wakes up, the power control signal pow_ctrl is in a pulled-down state through the power-on maintaining circuit.

The power-on hold circuit is an inverter circuit. As an example of the circuit shown in fig. 2, the power-on hold circuit is composed of transistors Q4, R18, R17, C34, and the like. When pb1_self_pow_en is high, pow_ctrl is low. C34 and R17 are connected in parallel to play a role of smoothing filter.

The PB1_SELF_POW_EN is connected with an output pin of the controller. Meanwhile, the Pb1_SELF_POW_EN and the Pb0_CHG_CHECK are associated, the Pb0_CHG_CHECK is connected with one input pin of the controller, a logic unit is built in the controller, and the logic relationship between the signal and the power-on maintaining signal Pb1_SELF_POW_EN is established.

One possible logical relationship is: the controller periodically detects the wake-up circuit detection signal pb0_chg_check, and when detecting that pb0_chg_check is a rising edge trigger signal, sets the power-on hold signal pb1_self_pow_en to a high level and holds it, so that pow_ctrl is held at a low level, thereby keeping the BMS in a turned-on state. When the pb0_chg_check falling edge trigger signal is detected, the power-on hold signal pb1_self_pow_en is set to a low level, and a shutdown operation is performed.

While the utility model has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the utility model as defined by the appended claims.

Claims

1. Prevent BMS wake-up circuit of reverse connection, its characterized in that: the device comprises a first input end, a first output end, a second output end, a bridge rectifier circuit, an optocoupler and a controller;

the two ends of the first input end are connected with the two ends of the input end of the bridge rectifier circuit and are used for accessing wake-up signals;

The second output end is pulled up and connected with the controller and used for outputting a wake-up circuit detection signal.

2. The anti-reverse BMS wake-up circuit of claim 1, wherein: the control loop is also connected with a voltage stabilizing tube in series.

3. The anti-reverse BMS wake-up circuit of claim 1, wherein: the BMS wake-up circuit further comprises a power-on holding circuit, the power-on holding circuit is an inverting circuit, an input end is connected with the controller, and an output end is connected with the first output end.

4. The anti-reverse BMS wake-up circuit of claim 3 wherein: the power-on holding circuit comprises a semiconductor switching tube, a first resistor, a second resistor and a first capacitor, and the input end of the power-on holding circuit is connected with the control end of the semiconductor switching tube through the first resistor, the first capacitor and the control end of the semiconductor switching tube which are connected in parallel; the control end of the semiconductor switching tube is grounded through a second resistor; the output end of the semiconductor switching tube outputs a power supply control signal; the input end of the semiconductor switch tube is grounded.

5. The anti-reverse BMS wake-up circuit of claim 3 wherein: the controller comprises a logic unit, a first input pin and a first output pin; the logic unit performs the following logical relationship: outputting a high-level signal to the first output pin and maintaining the high-level signal when the rising edge trigger signal is input to the first input pin, and outputting a low-level signal to the first output pin when the falling edge trigger signal is input to the first input pin; the first input pin is connected with the second output end; the first output pin is connected with the input end of the power-on holding circuit.