CN218276709U

CN218276709U - Back plate and satellite communication equipment

Info

Publication number: CN218276709U
Application number: CN202222798581.0U
Authority: CN
Inventors: 黄小东; 刘毅; 袁文彬
Original assignee: Sichuan Runze Jingwei Information Technology Co ltd
Current assignee: Sichuan Runze Jingwei Information Technology Co ltd
Priority date: 2022-10-24
Filing date: 2022-10-24
Publication date: 2023-01-10
Anticipated expiration: 2032-10-24

Abstract

The utility model discloses a backboard and satellite equipment, the backboard comprises a bottom board and a management board, a plurality of slot position interfaces and a management board interface are distributed on the bottom board, the slot position interfaces are high-speed connectors and are used for assembling different function cards; the management board is provided with a functional circuit and a data interface in a layout mode, and the bottom board and the management board are interconnected through the data interface and the management board interface. The utility model provides a plurality of trench interfaces that are used for different function card assembly of backplate configuration can assemble different function cards according to using the scene, has satisfied and has carried out nimble apolegamy requirement to module quantity and type under different applied scenes, reconfigures different functional circuit, can realize different functions.

Description

Back plate and satellite communication equipment

Technical Field

The utility model belongs to the technical field of the satellite communication product, concretely relates to backplate, this backplate are by mainly used satellite communication equipment.

Background

In the application of satellite communication equipment, the multiband satellite communication receiving equipment is widely applied. In practical application, the equipment needs to match the number and types of modules of the equipment according to different application scenes, and the application is provided on the premise.

SUMMERY OF THE UTILITY MODEL

An object of the present invention is to provide a back plate, which can meet the flexible matching requirements for the number and types of modules under different application scenarios.

Therefore, the back plate provided by the utility model comprises a bottom plate and a management plate, wherein the bottom plate is provided with a plurality of slot position interfaces and management plate interfaces, and the slot position interfaces are high-speed connectors and are used for assembling different function cards;

the management board is provided with a functional circuit and a data interface in a layout mode, and the bottom board and the management board are interconnected through the data interface and the management board interface.

In some embodiments, the bottom plate further has a power interface disposed thereon as a power connector.

In some embodiments, a fan power supply interface for supplying power to the fan and/or a fan and power state detection interface are arranged on the bottom plate.

In some embodiments, the functional circuitry includes FPGA circuitry, PHY circuitry to provide a gigabit ethernet interface, storage circuitry, clock circuitry, debug circuitry, GPS circuitry, and power circuitry.

In some embodiments, a heat sink is further included that is mounted to an upper portion of the management board.

In some embodiments, the heat sink and the chip forming the functional circuit are contacted together through a heat conductive silicone.

In some embodiments, the base plate is fitted with a guide pin thereon.

A second object of the present invention is to provide a satellite communication device, which includes the back plate provided by the present application.

In some embodiments, the system comprises a signal receiving and processing card, a data exchange card and a main control card for receiving and processing radio frequency signals, wherein the signal receiving and processing card, the data exchange card and the main control card are respectively connected to the slot interfaces, and the slot interfaces are interconnected and interconnected with the functional circuit through the data interface and the management board interface.

In some embodiments, the functional circuit includes an FPGA circuit and a clock circuit which are connected with the signal receiving and processing card, the data exchange card and the main control card through the data interface and the management board interface, the FPGA circuit is connected with an upper computer or other devices through a debugging interface, and the clock circuit generates various clock signals to be provided for each circuit as a reference clock.

Adopt the technical scheme of the utility model, the beneficial effect that can reach includes at least:

1) The utility model provides a plurality of trench interfaces that are used for different function card assembly of backplate configuration can assemble different function cards according to using the scene, has satisfied and has carried out nimble apolegamy requirement to module quantity and type under different applied scenes, reconfigures different functional circuit, can realize different functions.

2) The utility model provides a backplate is a general backplate of taking managerial function.

3) The radiating effect is good, has improved the reliability.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:

fig. 1 is a side view of a back plate provided by the present invention;

fig. 2 is a front view of a back plate provided by the present invention;

fig. 3 is a rear view of the back plate provided by the present invention;

FIG. 4 is a front view of the bottom plate depicted in the present invention;

FIG. 5 is a rear view of the base plate described in the present invention;

FIG. 6 is a top view of a management board as described herein;

FIG. 7 is a bottom view of the management board described in the present invention;

fig. 8 is an external view of the heat sink described in the present invention;

fig. 9 is a schematic diagram of a functional circuit described in the present invention.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.

In order to meet the requirement of flexibly matching data and types of functional modules in different application scenes, the application discloses a backplane, the backplane is configured with a bottom board 1 and a management board 2, and the bottom board 1 and the management board 2 respectively comprise a PCBA board and functional modules arranged on the PCBA board. With reference to fig. 1 to 7, a PCBA board of the bottom board 1 is provided with a plurality of slot interfaces and management board interfaces, and the slot interfaces are high-speed connectors for assembling different function cards;

functional circuits and data interfaces are distributed on the PCBA of the management board 2, and the bottom board 1 and the management board 2 are interconnected through the data interfaces and the management board interfaces.

The number of Slot interfaces on the PCBA board of the bottom board 1 is set according to the requirements of scenes to which the Slot interfaces are possibly applied, and the Slot interfaces can be included in Slot 1-10 interfaces 3, wherein the Slot 1-8 can be used for the access of the same function card, and the Slot9 and the Slot10 are respectively used for the access of other function cards; the management board interface 4 is for connecting a management board, and is configured as an FMC connector.

As shown in fig. 4 and 5, the PCBA board on the bottom board 1 in the present disclosure is further configured with:

1) And the power interface 5 is used as a power supply end connector for power supply access, such as connecting a DC12V power supply.

2) The fan power supply interface 6 is used for power supply access and providing a working power supply for the fan, such as a DC12V power supply; configured as a PH-4 connector.

3) The fan and power supply state detection interface 7 is used for providing fan and power supply states, is connected with the functional circuit and realizes the detection of the fan and power supply states; configured as a PH-8 connector.

As shown in fig. 6 and 7, the functional circuit disposed on the PCBA board on the management board 2 of the present disclosure is configured to include:

1) A power supply circuit 8 for supplying a working power supply to the management board;

2) PFGA circuit 9, signal connected to each functional module and daughter card, as shown in fig. 8, to complete system management; the FPGA circuit 9 is used as a management core of the backboard and is interconnected with an upper computer or external equipment through a regulating and measuring circuit 10 to realize data transmission, so that the upper computer or the external equipment acquires the state of each functional module and completes the monitoring of the whole state of the equipment; the upper computer or the external equipment transmits a management instruction to the FPGA circuit through the debugging circuit 10 to complete the configuration management of each functional module; the functions of configuration management, state monitoring and the like of each module of the equipment are realized. The debugging circuit 10 performs interface signal level conversion to provide an external debugging test interface.

3) The PHY circuit 11 provides a gigabit ethernet interface for data transmission, and ensures a transmission rate.

4) The storage circuit 12 stores a relevant file, log information, and the like.

5) The clock circuit 13, including a temperature compensated crystal oscillator, a clock buffer and a phase locked loop PLL, generates a plurality of clock frequency signals, which are provided to the respective circuits as reference clocks.

6) And a GPS circuit 14 for providing GPS functions.

7)

Data interfaces

15, 16, interconnected with corresponding ports of the backplane, are configured as FMC connectors.

The backboard of the present disclosure provides a plurality of slot interfaces, data interfaces, management board interfaces, functional circuits, various functional interfaces, etc., functional modules can be connected to the slot interfaces as required, and then connected by wires to form all functional units or partial units of the functional circuits, and the backboard which meets different application places can be formed by connecting the data interfaces, the management board interfaces, the functional modules, etc. by wires/data lines/cables, etc.

The connection relationship between the slot interface and the broadband signal receiving and processing card, the data exchange card and the main control card, and the functional circuit is illustrated in fig. 9.

The Slot slots 1 to 8 are configured for signal receiving processing card access (the signal receiving processing card can be accessed to one, two or more, when being accessed to a plurality of cards, the signal receiving processing card can realize receiving processing of a plurality of signals), the Slot9 is configured for data exchange card access, and the Slot10 is configured for master card access.

The Slot slots 1-10 are respectively cross-linked with an FPGA circuit, the FPGA circuit is connected to a debugging circuit 10, the cross-linking with an upper computer or external equipment is realized through the testing circuit 10, the testing circuit is used for managing data (data for parameter configuration and management) transmission, the parameter configuration management of the Slot slots 1-10 is realized, or the interaction with service data (data required for processing and analysis) of the upper computer or the external equipment is realized through the debugging circuit 10; the clock circuit is an FPGA circuit and is crosslinked with the Slot positions Slot 1-10, and reference clock signals are respectively provided for the FPGA circuit and the signal receiving and processing card, the data interaction card and the main control card which are accessed into the Slot positions Slot 1-10; the Slot positions Slot 1-8, slot position Slot9 and Slot position Slot10 are mutually cross-linked to realize data transmission; the FPGA circuit is also respectively crosslinked with the Slot positions Slot 1-8, the Slot position Slot9 and the Slot position Slot10 through the PHY circuit, and service data transmission is realized through a gigabit Ethernet interface.

It should be understood by those skilled in the art that when the Slot slots 1 to 8 are configured for signal receiving processing card access, the Slot9 is configured for data exchange card access, and the Slot10 is configured for master card access, the functional circuit on the management board 2 may also only include an FPGA circuit, the Slot slots 1 to 10 are respectively cross-linked with the FPGA circuit, and the FPGA circuit is accessed to the debugging circuit 10, and the testing circuit 10 is used to implement cross-linking with an upper computer or an external device, and is used to transmit management data (data used for parameter configuration and management), implement parameter configuration management on the Slot slots 1 to 10, or implement service data (data required for processing and analysis) interaction with the upper computer or the external device through the debugging circuit 10.

Or, the functional circuit on the management board 2 includes an FPGA circuit and a PHY circuit, the Slot slots 1 to 10 are respectively cross-linked with the FPGA circuit, the FPGA circuit is connected to the debugging circuit 10, and the testing circuit 10 is used to realize cross-linking with the upper computer or the external device, and is used for transmitting management data (data for parameter configuration and management), realizing parameter configuration management of the Slot slots 1 to 10, or realizing service data (data required for processing and analysis) interaction with the upper computer or the external device through the debugging circuit 10; the FPGA circuit is respectively crosslinked with the Slot positions Slot 1-8, the Slot position Slot9 and the Slot position Slot10 through the PHY circuit, and service data transmission is realized through a gigabit Ethernet interface.

Or, the functional circuits on the management board 2 include an FPGA circuit, a PHY circuit, a clock circuit, a memory circuit and a GPS circuit cross-linked with the FPGA circuit, and a power supply circuit for supplying operating power to each functional circuit.

The backboard can also connect the fan power supply interface with the fan without connecting a function card in the slot position interface, and connect the fan and the power state detection interface with the FPGA circuit, thereby realizing the power supply of the fan and the state detection of the fan and the power supply. The functional card can be connected into the slot position interface, the fan is connected into the fan power supply interface, and the fan and power supply state detection interface is connected with the FPGA circuit.

The signal receiving and processing card described in this disclosure is used for collecting and processing signals, and includes an RF interface for radio frequency signal access, an intermediate frequency signal processing circuit, and an ADC circuit, where:

1) The intermediate frequency signal processing circuit comprises a filter, an amplifier, an attenuator and an IQ demodulator, and is used for filtering, amplifying, attenuating, IQ demodulating and the like the input frequency band signal to obtain an I path signal and a Q path signal processed by the ADC circuit.

2) And the ADC circuit comprises two ADC channels, analog-to-digital conversion (A/D conversion) is respectively carried out on the demodulated signals of the I channel and the Q channel to obtain digital signals, and the digital signals are transmitted to the FPGA circuit through a high-speed JESD204B interface or directly transmitted to a data line for processing, namely data acquisition is finished. The sampling rate of the ADC circuit is configured according to the radio frequency signal to be sampled and processed, so as to realize the acquisition of signals of different frequency bands, for example, the sampling rate is configured to 3000MHz, and the functions of intermediate frequency signal acquisition, data processing and the like of an L frequency band (950 MHz-2150 MHz) can be realized. When the signal receiving and processing cards are configured to be multiple, and each sampling rate is different, the acquisition processing of multiple different frequency bands can be realized, and certainly, the signal receiving and processing cards can also be configured to be multiple signal receiving and processing cards with the same sampling rate, so that multiple acquisitions of the same frequency band can be realized.

3) The FPGA circuit is used for carrying out digital baseband filtering on the digital signal from the ADC circuit and optimizing the signal-to-noise ratio of the signal; then DDC processing is carried out to obtain digital zero-frequency signals of a plurality of carriers; and finally, respectively identifying each carrier to obtain information such as frequency spectrum data, service data and the like.

When the signal receiving and processing card is connected with the slot position interface, the output of the signal receiving and processing card is crosslinked with the slot position interface.

The data card described in this disclosure is used for data interaction, and mainly includes:

1) And the switching module integrates gigabit and gigabit Ethernet interfaces and provides a data switching function.

2) The interface circuit provides 2 paths of gigabit Ethernet interfaces and 2 paths of gigabit Ethernet interfaces to the back panel, and provides 2 paths of gigabit SFP + interfaces and 1 path of gigabit RJ45 interfaces to the front panel.

When the data exchange card is connected with the slot interface, the interface circuit is crosslinked with the slot interface.

The master control card described in this disclosure mainly includes:

1) The CPU processor circuit and the core of the CPU monitoring management module are used for completing configuration management and state monitoring of the equipment, providing functions of data statistics, data storage, data forwarding, interface data transmission and the like, and providing multiple data interfaces, so that the management mode is more flexible.

2) The interface circuit comprises a data interface circuit, a gigabit management data interface and a gigabit service data interface, and adopts a VPX standard connector; and the RJ45 interface circuit is used for carrying out data transmission and service interaction with an upper computer or other equipment.

3) And the GPU circuit is interconnected with the CPU through a PCIe bus, performs data transmission and provides a DP display interface to the outside.

When the master control card is connected with the slot position interface, the interface circuit is connected with the slot position interface.

The design also includes a heat sink 17, which heat sink 17 is mounted primarily on the top of the management board PCBA, and is contacted with the primary chip shown in fig. 6 by a thermally conductive silicone pad and then fastened with screws 18. The heat sink 17 is shown in fig. 8 in appearance and includes mounting holes 19 and fins 20. After the heat sink is installed, the management board 2 is snapped onto the base plate 1 and secured to the base plate with screws 18, as shown in FIGS. 1-3.

The back board is provided with various interfaces, slot interfaces and functional circuits, different functional cards can be accessed according to application scenes, and different functions can be realized by connecting the corresponding interfaces and the functional circuits, so that a universal back board with a management function is realized; the radiator is arranged, so that the reliability is improved; the management and monitoring can be realized by matching with different interfaces, and an effective clock signal can be provided.

In addition, a guide pin 21 is also arranged on the bottom plate; the guide pin 21 is used for positioning, when other board cards are inserted into the backboard, the guide pin is firstly contacted and positioned, the sub-card is ensured to be inserted into the corresponding slot position range, and the position deviation of the corresponding slot position sub-card in the insertion engineering is prevented from being too large to damage the connector.

The backplane of the present disclosure also includes a VPX connector 22 for interconnection between the backplane and other VPX daughter cards.

The back plate can be suitable for any equipment, and different circuits can be built according to the equipment requirements to meet different requirements; if the signal receiving and processing card is applied to satellite communication receiving equipment, the satellite signal receiving and processing can be realized by configuring the signal receiving and processing card, and the interaction and processing of data can be realized by configuring the data exchange card and the main control card.

The above embodiments are only used for illustrating the technical solutions of the present invention and not for limiting, and modifications or equivalent replacements made by those of ordinary skill in the art to the technical solutions of the present invention are all covered within the scope of the claims of the present invention as long as they do not depart from the spirit and scope of the technical solutions of the present invention.

Claims

1. A backboard is characterized by comprising a bottom board and a management board, wherein a plurality of slot position interfaces and management board interfaces are distributed on the bottom board, and the slot position interfaces are high-speed connectors and are used for assembling different function cards;

2. The backplane according to claim 1, wherein the backplane further comprises a power interface disposed thereon as a power connector.

3. The back panel as claimed in claim 1, wherein the bottom panel further comprises a fan power supply interface and/or a fan and power status detection interface for providing power to the fan.

4. The backplane of claim 1, wherein the functional circuitry comprises FPGA circuitry, PHY circuitry to provide a gigabit ethernet interface, storage circuitry, clock circuitry, debug circuitry, GPS circuitry, and power circuitry.

5. The backplane of claim 1, further comprising a heat sink mounted to an upper portion of the management board.

6. The backplane according to claim 5, wherein the heat spreader is in contact with the chips constituting the functional circuit by a thermally conductive silicone.

7. The backplate of claim 1, wherein the backplate is fitted with guide pins thereon.

8. A satellite communications device comprising a back plane as claimed in any one of claims 1 to 7.

9. The satellite communication device according to claim 8, comprising a signal receiving processing card, a data exchange card and a main control card for receiving and processing radio frequency signals, wherein the signal receiving processing card, the data exchange card and the main control card are respectively connected to the slot interfaces, and the slot interfaces are interconnected with each other and with the functional circuit through the data interface and the management board interface.

10. The satellite communication device according to claim 9, wherein the functional circuit includes an FPGA circuit and a clock circuit interconnected with the signal receiving and processing card, the data exchange card and the main control card through the data interface and the management board interface, the FPGA circuit is connected with an upper computer or other devices through a debugging interface, and the clock circuit generates various clock signals to be provided to each circuit as a reference clock.