CN218274616U - Multi-main-grid back-contact heterojunction solar cell - Google Patents
Multi-main-grid back-contact heterojunction solar cell Download PDFInfo
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- CN218274616U CN218274616U CN202221398068.6U CN202221398068U CN218274616U CN 218274616 U CN218274616 U CN 218274616U CN 202221398068 U CN202221398068 U CN 202221398068U CN 218274616 U CN218274616 U CN 218274616U
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- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
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- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/042—PV modules or arrays of single PV cells
- H01L31/05—Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells
- H01L31/0504—Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells specially adapted for series or parallel connection of solar cells in a module
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- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
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Abstract
The utility model relates to a many main grids back contact heterojunction solar cell, it includes the semiconductor substrate, set up a plurality of first semiconductor district and the second semiconductor region that set up on the first main face of semiconductor substrate in turn, the isolating groove of setting between each first semiconductor district and second semiconductor region, the level sets up the first insulating layer array more than one row on each first semiconductor district, the level sets up the second insulating layer array more than one row on each second semiconductor region, the same horizontal position of each second insulating layer array carries out the first main grid line that welds more than one row that corresponds the setting and carries out the second main grid line that welds more than one row that corresponds the setting with the same horizontal position of each first insulating layer array; the first insulating layer array and the second insulating layer array are staggered from top to bottom. An object of the utility model is to provide a many main bars back of body contact heterojunction solar cell is showing the electric conductivity requirement that reduces thin grid line, realizes many main bars structure, reduction in production cost.
Description
Technical Field
The utility model relates to a solar cell technical field especially relates to a many main grids back of body contact heterojunction solar cell.
Background
In recent years, the production technology of solar cells is continuously advanced, the production cost is continuously reduced, the conversion efficiency is continuously improved, and the solar cell power generation is widely applied and becomes an important energy source for power supply. The high-efficiency solar cell is the trend of future industries, and can reduce the cost while increasing the generating wattage of a unit area, thereby increasing the added value of module power generation.
A back contact cell, which is one of high efficiency solar cells, maximizes the area of a light receiving surface by shifting all electrodes of the light receiving surface to a back surface, thereby improving the conversion efficiency of the cell, and is typically SUN POWER in the united states.
However, the high efficiency battery technology has a problem of high manufacturing cost at the present stage. For example, the back contact battery adopts the copper electroplating technology, which has the problems of corresponding copper-containing wastewater treatment and environmental protection, and needs a larger production field, which is not beneficial to large-scale mass production and popularization. Therefore, it is necessary to develop a low-cost metal electrode structure for back contact cells to promote mass production of high-efficiency back contact cells.
Disclosure of Invention
An object of the utility model is to provide a many main bars back contact heterojunction solar cell, when showing the electric conductivity requirement that reduces thin grid line, realize many main bars structure, reduction in production cost.
The purpose of the utility model is realized through the following technical scheme:
a multi-main-grid back-contact heterojunction solar cell comprises a semiconductor substrate, a plurality of first semiconductor regions and second semiconductor regions which are arranged on a first main surface of the semiconductor substrate and are alternately arranged from left to right, an isolation groove arranged between each first semiconductor region and each second semiconductor region, more than one row of first insulating layer arrays horizontally arranged on each first semiconductor region, more than one row of second insulating layer arrays horizontally arranged on each second semiconductor region, more than one row of first weldable main grid lines which are electrically connected with each first semiconductor region and are correspondingly arranged at the same horizontal position as each second insulating layer array, and more than one row of second weldable main grid lines which are electrically connected with each second semiconductor region and are correspondingly arranged at the same horizontal position as each first insulating layer array; the first insulating layer array and the second insulating layer array are staggered from top to bottom.
Compare prior art, the utility model has the advantages of:
(1) Adopt first semiconductor region and second semiconductor region to set up the structure in turn, through the insulating layer array that corresponds the semiconductor region and can weld the crisscross setting of main grid line, the insulating layer array is done the separation and is insulated to the different semiconductor regions of same horizontal position, it only forms the electricity with the semiconductor region of same conduction type to guarantee can weld the main grid line and be connected, effectively avoid the short circuit, realize the many main grid structures of back contact heterojunction solar cell, the electric conductivity requirement of solar wafer to thin grid line has been showing to have reduced, cell series welding when very convenient battery test is selected separately and is makeed the subassembly simultaneously.
(2) The metal conducting layer is adopted as the fine grid electrode, a copper electroplating process is not needed, and meanwhile, expensive low-temperature silver paste is not needed for the fine grid electrode, so that the production process flow of the battery piece is greatly simplified, the production cost is reduced, and the method is very suitable for large-scale mass production.
Drawings
Fig. 1 shows a step of manufacturing a solar cell according to a first embodiment of the present invention;
fig. 2 is a cross-sectional view of an n-type silicon wafer with a passivation layer formed on the front surface and a first semiconductor region, an isolation region and a second semiconductor region arranged in a cross-over manner with an anti-reflection layer and a back surface according to an embodiment of the present invention;
fig. 3 is a cross-sectional view of a silicon wafer back surface deposited with a transparent conductive film layer and a metal conductive film layer according to an embodiment of the present invention;
FIG. 4 is a cross-sectional view of a surface printed protective ink on the isolation region on the back side of a silicon wafer according to an embodiment of the present invention;
FIG. 5 is a schematic structural diagram of a silicon wafer backside printing protection ink according to an embodiment of the present invention;
FIG. 6 is a cross-sectional view of an embodiment of the present invention showing isolation grooves;
FIG. 7 is a schematic structural diagram of a silicon wafer according to an embodiment of the present invention after cleaning the protective ink on the back surface;
fig. 8 is a cross-sectional view of an alternative insulating layer formed on the back of a silicon wafer according to an embodiment of the present invention;
fig. 9 is a schematic structural view illustrating an alternative arrangement of insulating layers formed on the back surface of a silicon wafer according to an embodiment of the present invention;
fig. 10 is a cross-sectional view of a solderable main gate line formed on the back side of a silicon wafer according to an embodiment of the present invention;
fig. 11 is a schematic structural view illustrating a solderable main gate line formed on the back surface of a silicon wafer according to an embodiment of the present invention;
fig. 12 is a schematic structural view of a silicon wafer after series welding according to an embodiment of the present invention;
fig. 13 shows a second step of fabricating a solar cell according to an embodiment of the present invention;
fig. 14 is a cross-sectional view of an n-type silicon wafer according to a second embodiment of the present invention, in which a passivation layer is formed on the front surface and a first semiconductor region, an isolation region and a second semiconductor region are formed to intersect with the anti-reflection layer and the back surface;
fig. 15 is a cross-sectional view of a transparent conductive film deposited on the back surface of a second cell according to an embodiment of the present invention;
fig. 16 is a sectional view of a second battery according to an embodiment of the present invention, in which an isolation trench pattern is formed on the back surface;
fig. 17 is a sectional view of a second battery according to an embodiment of the present invention, in which an isolation groove is formed on the back surface of the second battery;
fig. 18 is a schematic structural view of an isolation groove formed on the back surface of a second battery according to an embodiment of the present invention;
fig. 19 is a sectional view of the back surface of a second battery of the present invention with alternately arranged insulating layers;
fig. 20 is a schematic structural view of the second battery of the embodiment of the present invention, in which the insulating layers are alternately arranged on the back surface of the second battery;
fig. 21 is a cross-sectional view of a metal grid line formed on the back of a second battery according to an embodiment of the present invention;
fig. 22 is a schematic structural view of the second battery of the embodiment of the present invention, in which metal grid lines are formed on the back surface of the second battery in an alternating arrangement;
fig. 23 is a schematic structural view of the second battery of the embodiment of the present invention after welding the solder strips in series on the back surface thereof;
fig. 24 is another schematic structural diagram of the second battery of the embodiment of the present invention, in which the metal grid lines are alternately arranged on the back surface.
Detailed Description
A multi-main-grid back-contact heterojunction solar cell comprises a semiconductor substrate, a plurality of first semiconductor regions and second semiconductor regions which are arranged on a first main surface of the semiconductor substrate and are alternately arranged from left to right, an isolation groove arranged between each first semiconductor region and each second semiconductor region, more than one row of first insulating layer arrays horizontally arranged on each first semiconductor region, more than one row of second insulating layer arrays horizontally arranged on each second semiconductor region, more than one row of first weldable main grid lines which are electrically connected with each first semiconductor region and are correspondingly arranged at the same horizontal position as each second insulating layer array, and more than one row of second weldable main grid lines which are electrically connected with each second semiconductor region and are correspondingly arranged at the same horizontal position as each first insulating layer array; the first insulating layer array and the second insulating layer array are staggered from top to bottom.
The first insulating layer array covers the first semiconductor region and the isolation groove on the same horizontal position, so that the second weldable main grid line can only form electrical contact with the second semiconductor region; the second insulating layer array covers the second semiconductor region and the isolation trench at the same horizontal position so that the first solderable busbar can only make electrical contact with the first semiconductor region.
An isolation region is arranged between the first semiconductor region and the second semiconductor region, and the isolation groove is arranged on the isolation region.
First semiconductor district includes first type semiconductor film layer and the first conductive film layer that forms in proper order from the end to the face as the basement with the first principal of semiconductor substrate, the second semiconductor district includes second type semiconductor film layer and the second conductive film layer that forms in proper order from the end to the face as the basement with the first principal of semiconductor substrate, the isolation region includes first type semiconductor film layer, isolation film layer, second type semiconductor film layer and the isolation conductive film layer that forms in proper order from the end to the face as the basement with the first principal of semiconductor substrate, the isolation groove separates the conductive film layer of isolation into two parts about.
The first type semiconductor film layer comprises a first passivation layer and a first semiconductor layer which are sequentially formed from bottom to surface by taking a first main surface of the semiconductor substrate as a substrate; the second type semiconductor film layer comprises a second passivation layer and a second semiconductor layer which are sequentially formed from bottom to surface by taking the first main surface of the semiconductor substrate as a bottom surface; the first conductive film layer, the second conductive film layer and the isolation conductive film layer comprise transparent conductive layers formed by taking the corresponding semiconductor layers as substrates; the isolation film layer comprises an isolation insulating layer formed on the isolation region by taking the first semiconductor layer as a substrate.
Each first semiconductor region between two adjacent first insulation layer arrays is provided with a plurality of first thin grids electrically connected with the first weldable main grid line, and each second semiconductor region between two adjacent second insulation layer arrays is provided with a plurality of second thin grids electrically connected with the second weldable main grid line; the thickness of first thin bars and second thin bars is 5-30um, and length is 10-40mm. In a preferred embodiment, the first conductive film layer, the second conductive film layer and the isolation conductive film layer include a metal conductive layer formed on the basis of a transparent conductive layer, instead of the first fine gate and the second fine gate.
The first passivation layer and the second passivation layer respectively comprise intrinsic amorphous silicon layers and/or intrinsic microcrystalline silicon layers.
The first semiconductor layer and the second semiconductor layer comprise an N-type doped amorphous silicon/microcrystalline silicon layer or a P-type doped amorphous silicon/microcrystalline silicon layer, when the first semiconductor layer is the N-type doped amorphous silicon/microcrystalline silicon layer, the second semiconductor layer is the P-type doped amorphous silicon/microcrystalline silicon layer, and when the first semiconductor layer is the P-type doped amorphous silicon/microcrystalline silicon layer, the second semiconductor layer is the N-type doped amorphous silicon/microcrystalline silicon layer; the isolation film layer comprises at least one of a silicon nitride layer, a silicon oxide layer and a silicon carbide layer.
The transparent conductive layer is at least one of an indium tin oxide layer, an aluminum-doped zinc oxide layer, a gallium-doped zinc oxide layer, a zinc-doped indium oxide layer and a tungsten-doped indium oxide layer, the total thickness is 50-100nm, and the total square resistance is 20-100 omega/9633; the metal conducting layer is at least one of a copper layer, an aluminum layer, a nickel alloy layer and an indium tin oxide layer, the total thickness is 200-600nm, and the total sheet resistance is 0.02-0.5 omega/\9633;.
The width of the isolation groove is 10-150um, and the resistance between the metal conducting layers on the two sides of the isolation groove is greater than 1K omega.
The first weldable main grid line and the first weldable main grid line are a weldable low-temperature silver paste layer, a weldable silver-clad copper paste layer or a weldable nickel paste layer, the thickness of the first weldable main grid line and the first weldable main grid line is 5-30um, and the width of the first weldable main grid line and the first weldable main grid line is 0.04-10mm. In a preferred embodiment, the width of the first solderable main gate line or the second solderable main gate line in the region not in contact with the first semiconductor region or the second semiconductor region is 0.04 to 1mm, and the width of the first solderable main gate line or the second solderable main gate line in the region in contact with the first semiconductor region or the second semiconductor region is 1 to 10mm.
The first insulating layer array and the second insulating layer array are insulating smooth oil layers or insulating ink layers, the thickness is 3-25um, and the width is 0.3-1mm. The first insulating layer array and the second insulating layer array are made of transparent materials.
A method for manufacturing a multi-main-grid back-contact heterojunction solar cell comprises the following steps:
a step a of alternately providing a first semiconductor region and a second semiconductor region from left to right on a first main surface of a semiconductor substrate, and providing an isolation groove between the first semiconductor region and the second semiconductor region;
a step B of forming two or more columns of insulating sections on the first main surface of the semiconductor substrate, the two or more columns of insulating sections being arranged in a staggered manner from top to bottom; each column of insulating sections is only arranged in the first semiconductor region or the second semiconductor region, the first semiconductor region and the second semiconductor region are respectively provided with more than one column of insulating sections, and each first semiconductor region and each second semiconductor region are provided with insulating sections; a column of insulating sections arranged on the same horizontal position of the first semiconductor region is a first insulating layer array, and a column of insulating sections arranged on the same horizontal position of the second semiconductor region is a second insulating layer array;
and step C, correspondingly arranging first weldable main grid lines electrically connected with the first semiconductor regions at the same horizontal position of each second insulating layer array, and correspondingly arranging second weldable main grid lines electrically connected with the second semiconductor regions at the same horizontal position of each first insulating layer array.
The specific method of step a is that the first semiconductor regions and the second semiconductor regions are alternately arranged on the first main surface of the semiconductor substrate from left to right, the isolation region is arranged between the first semiconductor region and the second semiconductor region, and the isolation region is provided with the isolation groove.
First type semiconductor film layer and first conductive film layer are formed in proper order from the end to the face in the first principal plane that first semiconductor district used semiconductor substrate as the basement, the second semiconductor district uses semiconductor substrate's first principal plane to form second type semiconductor film layer and second conductive film layer in proper order from the end to the face as the basement, the isolation region uses semiconductor substrate's first principal plane to form first type semiconductor film layer, isolation rete, second type semiconductor film layer and isolation conductive film layer in proper order from the end to the face as the basement, set up the isolation groove that separates conductive film layer into two parts about with the isolation on the isolation region.
The isolation groove is formed on the surface of the isolation region by a laser etching technology or a chemical corrosion technology; the width of the isolation groove is 10-150um. The laser etching technology has the engraving speed of 3-50 m/s and the pulse energy of 10-1000 microjoules. The chemical etching technology can adopt chemical solution etching to form an isolation groove after printing protective ink, and can also adopt etching ink baking etching to form the isolation groove.
The first type semiconductor film layer is mainly formed by sequentially forming a first passivation layer and a first semiconductor layer from bottom to surface by taking a first main surface of a semiconductor substrate as a substrate; the second type semiconductor film layer is mainly formed by sequentially forming a second passivation layer and a second semiconductor layer from bottom to surface by taking the first main surface of the semiconductor substrate as a bottom surface; the first conductive film layer, the second conductive film layer and the isolation conductive film layer are mainly formed by sequentially forming a transparent conductive layer and a metal conductive layer from bottom to top by taking the corresponding semiconductor layer as a substrate; the isolation film layer is mainly formed by forming an isolation insulating layer on an isolation region by taking the first semiconductor layer as a substrate; the isolation region is provided with an isolation groove which divides the transparent conductive layer and the metal conductive layer into a left part and a right part. In a preferred embodiment, if the first conductive film layer, the second conductive film layer and the isolation conductive film layer do not include a metal conductive layer, the step C further includes forming first fine gates electrically connected to the first main gates on respective first semiconductor regions between two adjacent first insulating layer arrays, and forming second fine gates electrically connected to the second solderable main gate lines on respective second semiconductor regions between two adjacent second insulating layer arrays.
The first passivation layer and the second passivation layer are at least one of intrinsic amorphous silicon and intrinsic microcrystalline silicon, the first semiconductor layer and the second semiconductor layer are an N-type doped amorphous silicon/microcrystalline silicon layer or a P-type doped amorphous silicon/microcrystalline silicon layer, when the first semiconductor layer is the N-type doped amorphous silicon/microcrystalline silicon layer, the second semiconductor layer is the P-type doped amorphous silicon/microcrystalline silicon layer, and when the first semiconductor layer is the P-type doped amorphous silicon/microcrystalline silicon layer, the second semiconductor layer is the N-type doped amorphous silicon/microcrystalline silicon layer. The isolation insulating layer is at least one of silicon nitride, silicon oxide and silicon carbide.
The transparent conductive layer and the metal conductive layer are deposited by Physical Vapor Deposition (PVD) or Reactive Plasma Deposition (RPD) technology. The transparent conductive film layer is at least one of Indium Tin Oxide (ITO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), zinc-doped indium oxide (IZO) and tungsten-doped indium oxide (IWO), the thickness is 50-100nm, and the square resistance is 20-100 omega/\9633. The metal conductive film layer is at least one of Cu, al, ni alloy and ITO with thickness of 200-600nm and sheet resistance of 0.02-0.5 omega/96330.
And the resistance between the metal conducting layers on the two sides of the isolation groove is greater than 1K omega.
The specific method of the step B is to stagger and arrange the first insulating layer array and the second insulating layer array from top to bottom on the first main surface of the semiconductor substrate provided with the first semiconductor region and the second semiconductor region by adopting a roller coating, transfer printing, screen printing or printing technology; the first insulating layer array and the second insulating layer array are respectively provided with more than two. The first and second arrays of insulating layers are made of a transparent material.
The first insulating layer array and the second insulating layer array are formed by insulating ink through roller coating, transfer printing, silk-screen printing or baking at 130-200 ℃ for 5-30M curing, the thickness is 3-25um, the width is 0.3-1mm, and the resistance value is more than 1 megaohm/cm when the thickness of the insulating ink is 10um 2 . In another preferred scheme, the first insulating layer array and the second insulating layer array are made of insulating varnish.
And C, forming a second weldable main grid line or a first weldable main grid line at a horizontal position corresponding to the first insulating layer array or the second insulating layer array by using roll coating, transfer printing, screen printing or printing technology.
The first weldable main grid line and the second weldable main grid line are formed by rolling, transfer printing, silk-screen printing or printing weldable low-temperature silver paste, weldable silver-coated copper paste or weldable nickel paste and then baking at 150-230 ℃ for 5-40M for curing, the width of the first weldable main grid line or the second weldable main grid line in the area which is not in contact with the first semiconductor area or the second semiconductor area is 0.04-1mm, and the width of the first weldable main grid line or the second weldable main grid line in the area which is in contact with the first semiconductor area or the second semiconductor area is 1-10mm.
And a fourth passivation layer and an anti-reflection layer are sequentially formed on the second main surface of the semiconductor substrate from bottom to surface by taking the semiconductor substrate as a substrate. The fourth passivation layer is at least one of intrinsic amorphous silicon, intrinsic microcrystalline silicon, N-type doped amorphous silicon and N-type doped microcrystalline silicon; the anti-reflection layer is at least one of silicon nitride, silicon oxide, silicon carbide and transparent conductive film.
The semiconductor substrate is a cast monocrystalline silicon wafer, a monocrystalline silicon wafer or a polycrystalline silicon wafer.
In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The invention is described in detail below with reference to the drawings and examples:
example 1:
fig. 1 to 12 are schematic diagrams illustrating an embodiment of a multi-master gate back contact heterojunction solar cell according to the present invention.
The following embodiments can be specifically adopted for the fabrication of the embodiment:
s1, providing an n-type silicon wafer 10 with a passivation layer 30 and an anti-reflection layer 31 formed on the front surface and a first semiconductor region 42, an isolation region 44 and a second semiconductor region 43 which are arranged in a crossed mode on the back surface;
s2, depositing a transparent conductive film layer 50 and a metal conductive film layer 51 on the back of the silicon wafer 10 by a Physical Vapor Deposition (PVD) technology;
s3, printing protective ink 52 on the back of the silicon wafer 10 through a printing technology to form an isolation groove pattern;
s4, forming an isolation groove 53 on the surface of the isolation region 44 after the etching and cleaning by using a chemical solution;
s5, simultaneously forming insulating layers 60/61 on the surfaces of the first semiconductor region 42 and the second semiconductor region 43 through a silk-screen technology;
and S6, forming solderable main grid lines 70B/71B alternately arranged at intervals on the surfaces of the first semiconductor region 42 and the second semiconductor region 43 by a silk-screen technology.
As shown in fig. 2, a cross-sectional view of an n-type silicon wafer 10 is provided in S1. The passivation layer 30 formed on the front surface of the silicon wafer 10 is intrinsic oxygen-doped microcrystalline silicon with a thickness of 5-15nm, the anti-reflection layer 31 is silicon nitride with a thickness of 80-150nm, and the passivation layer is formed by Plasma Enhanced Chemical Vapor Deposition (PECVD). The first semiconductor region 42 is provided with a first passivation amorphous silicon layer 20, an N-type doped amorphous silicon and microcrystalline silicon composite layer 21 on the surface of the silicon wafer 10 in sequence. The second semiconductor region 43 is provided with a second passivation amorphous layer 40, a P-type doped amorphous silicon and microcrystalline silicon composite semiconductor layer 41 on the surface of the silicon wafer 10 in sequence. The isolation region 44 is provided with a first passivation amorphous silicon layer 20, an N-type doped amorphous silicon and microcrystalline silicon composite semiconductor layer 21, a silicon nitride isolation layer 22, a second passivation amorphous layer 40 and a P-type doped amorphous silicon and microcrystalline silicon composite semiconductor layer 41 in sequence on the surface of the silicon wafer 10, wherein the first passivation amorphous silicon layer 20, the N-type doped amorphous silicon and microcrystalline silicon composite semiconductor layer 21, the second passivation amorphous layer 40, the P-type doped amorphous silicon and microcrystalline silicon composite semiconductor layer 41 are 5-15nm thick, the silicon nitride isolation layer 22 is 80-150nm thick, and the first passivation amorphous silicon layer 20, the N-type doped amorphous silicon and microcrystalline silicon composite semiconductor layer 21, the silicon nitride isolation layer 22, the second passivation amorphous layer 40, the P-type doped amorphous silicon and microcrystalline silicon composite semiconductor layer 41 are formed by PECVD deposition. The silicon wafer 10 may be a cast single crystal silicon wafer or a single crystal silicon wafer.
As shown in fig. 3, a cross-sectional view of the transparent conductive film layer 50 and the metal conductive film layer 51 deposited on the back surface of the silicon wafer 10 in S2 is shown. The transparent conductive film layer 50 is Indium Tin Oxide (ITO) with the thickness of 80-100nm and the sheet resistance of 30-40 omega/\9633. The metal conductive film layer is a composite layer of copper Cu and Indium Tin Oxide (ITO), wherein the thickness of the copper layer is 300nm, the thickness of the Indium Tin Oxide (ITO) is 20-50nm, and the sheet resistance is 0.05-0.1 omega/\9633.
As shown in fig. 4-5, a pattern of isolation grooves 53 is formed on the back surface of the silicon wafer 10 in S3 by printing the protective ink 52 by using a printing technique, the space between the protective ink 52 is 50-150um, the baking temperature of the protective ink 52 is 150 ℃, and the baking time is 10 minutes.
As shown in FIGS. 6 to 7, the silicon wafer 10 was subjected to the solubility-5% FeCl in S4 3 Etching the metal conductive layer 51 and the transparent conductive film layer 50 outside the area of the protective ink 52 by etching the mixed solution of HCL having a solubility of 5% for 3 minutes, and cleaning the protective ink 52 with a 5% NaOH solution to form an isolation groove 53, wherein the resistance between the metal conductive layers 51 on both sides of the isolation groove 53 is greater than 1 K.OMEGA.
As shown in fig. 8-9, for the back surface of the silicon wafer 10 in S5, a silk screen printing technique is used to simultaneously form insulating layers 60/61 on the surfaces of the first semiconductor region 42 and the second semiconductor region 43, the thickness of the insulating layer 60/61 is 3-25um, the width is 0.5-0.8mm, after printing, the insulating layer 60 on the surface of the first semiconductor region 42 and the insulating layer 61 on the surface of the second semiconductor region 43 are alternately arranged at intervals by baking at 180 ℃ for 5 minutes to dry.
As shown in fig. 10-11, a low-temperature solderable silver-clad copper paste is printed on the back surface of the silicon wafer 10 in S6 by using a screen printing technique to form solderable bus bars 70B/71B, the thickness of the solderable bus bars 70B/71B is 10-15um, the solderable bus bars are formed by baking at 180 ℃ for 30 minutes and curing after printing, the bus bars have 10-20 columns, each column of bus bars is independently connected with the first semiconductor region 42 or the second semiconductor region 43, the width of the bus bar 70B/71B is 0.06mm, and in order to reduce the contact resistance between the bus bar 70B/71B and the metal conductive layer 51, the area where the bus bar 70B/71B directly contacts the metal conductive layer 51 can be widened to 3mm.
In test sorting, IV data can be collected by only leading out the bus bars 70B on the surface of the first semiconductor region 42 and the bus bars 71B on the surface of the second semiconductor region 43, respectively. As shown in fig. 12, when the silicon wafers 10 are serially bonded in the assembly process, the main gate lines 70B on the surface of the first semiconductor region 42 and the main gate lines 71B on the surface of the second semiconductor region 43 on the back surfaces of two adjacent silicon wafers 10 are alternately bonded together by the bonding tape 80, so that the silicon wafers 10 can be serially connected.
The utility model adopts the above technical scheme, can realize the many main bars structures of back contact heterojunction solar cell, it requires to the electric conductivity of thin grid line to show to have reduced solar wafer, adopt physics vapor deposition metal conducting layer as thin grid electrode simultaneously, only can weld the low temperature silver thick liquid that the main grid line adopted present conventional use, make the silver thick liquid unit consumption that the specification is the G1 silicon chip reduce to 50-100mg, be less than the silver thick liquid unit consumption about conventional heterojunction 200mg far away, also be less than the silver thick liquid unit consumption about many main bars silicon base homojunction back contact cell 400mg far away. Meanwhile, the problems of copper-containing wastewater treatment, environmental protection, large production field, high operation cost and the like do not need to be considered when large-scale wet-process copper electroplating equipment is used, so that the production process flow of the cell is greatly simplified, the production cost is reduced, the cell series welding is very convenient for cell testing, sorting and component manufacturing, and the mass production and popularization of the back contact heterojunction solar cell with high conversion efficiency are very facilitated.
Example 2:
fig. 13 to fig. 24 are schematic diagrams illustrating an embodiment of a multi-master-gate back-contact heterojunction solar cell according to the present invention.
The following embodiments can be specifically adopted for the fabrication of the embodiment:
s1, providing an n-type silicon wafer 10 with a passivation layer 30 and an anti-reflection layer 31 formed on the front surface and a first semiconductor region 42, an isolation region 44 and a second semiconductor region 43 which are arranged in a crossed mode on the back surface;
s2, depositing a transparent conductive film layer 50 on the back surface of the silicon wafer 10 by a Physical Vapor Deposition (PVD) technology;
s3, forming an isolation groove pattern 52 on the back of the battery through a silk-screen technology;
s4, forming an isolation groove 53 on the surface of the isolation region 44 through a wet chemical etching ink stripping technology;
s5, forming insulating layers 60 and 61 which are alternately arranged at intervals on the surfaces of the first semiconductor region 42 and the second semiconductor region 43 through a silk-screen technology;
and S6, forming metal grid lines 70/71 which are alternately arranged with the insulating layers 60/61 on the surfaces of the first semiconductor region 42 and the second semiconductor region 43 by a silk-screen technology.
As shown in fig. 14, a cross-sectional view of an n-type silicon wafer 10 is provided in S1. The passivation layer 30 formed on the front surface of the silicon wafer 10 is intrinsic oxygen-doped microcrystalline silicon with a thickness of 5-15nm, the anti-reflection layer 31 is silicon nitride with a thickness of 80-150nm, and the passivation layer is formed by Plasma Enhanced Chemical Vapor Deposition (PECVD). The first semiconductor region 42 is provided with a first passivation amorphous silicon layer 20, an N-type doped amorphous silicon and microcrystalline silicon composite layer 21 on the surface of the silicon wafer 10 in sequence. The second semiconductor region 43 is provided with a second passivation amorphous layer 40, a P-type doped amorphous silicon and microcrystalline silicon composite semiconductor layer 41 on the surface of the silicon wafer 10 in sequence. The isolation region 44 is provided with a first passivation amorphous silicon layer 20, an N-type doped amorphous silicon and microcrystalline silicon composite semiconductor layer 21, a silicon nitride isolation layer 22, a second passivation amorphous layer 40 and a P-type doped amorphous silicon and microcrystalline silicon composite semiconductor layer 41 in sequence on the surface of the silicon wafer 10, wherein the first passivation amorphous silicon layer 20, the N-type doped amorphous silicon and microcrystalline silicon composite semiconductor layer 21, the second passivation amorphous layer 40, the P-type doped amorphous silicon and microcrystalline silicon composite semiconductor layer 41 are 5-15nm thick, the silicon nitride isolation layer 22 is 80-150nm thick, and the first passivation amorphous silicon layer 20, the N-type doped amorphous silicon and microcrystalline silicon composite semiconductor layer 21, the silicon nitride isolation layer 22, the second passivation amorphous layer 40, the P-type doped amorphous silicon and microcrystalline silicon composite semiconductor layer 41 are formed by PECVD deposition. The silicon wafer 10 may be a cast single crystal cell or a single crystal cell.
As shown in fig. 15, a cross-sectional view of a transparent conductive film layer 50 deposited on the back surface of the silicon wafer 10 in S2 is shown. The transparent conductive film layer 50 is Indium Tin Oxide (ITO), the thickness is 80-100nm, and the sheet resistance is 30-40 omega/\9633.
As shown in fig. 16, a cross-sectional view of isolation trench patterns is formed on the back surface of the S3 silicon wafer 10 by printing a protective ink 52 by a screen printing technique. The width of the isolation groove is 30-100um, the baking temperature of the protective printing ink is 150 ℃, and the baking time is 5-10M.
As shown in fig. 17-18, fig. 17 is a cross-sectional view of the back surface of the S4 silicon wafer 10 formed with isolation trenches 53 on the surface of the isolation regions 44 by wet chemical etching ink stripping. Fig. 18 is a schematic structural diagram of the S4 silicon wafer 10 with isolation trenches 53 formed on the surface of the isolation regions 44 by wet chemical etching and de-inking. After the protective ink 52 is baked, the transparent conductive film layer 50 outside the area of the protective ink 52 is etched and cleaned by adopting a hydrochloric acid solution with the solubility of 2-10%, then the protective ink 52 is removed and cleaned by a potassium hydroxide solution with the solubility of 2-10%, and the resistance between the transparent conductive film layers 50 on the two sides of the isolation groove 53 after the ink is removed by etching is larger than 1K omega.
As shown in fig. 19 to 20, cross-sectional views and structural schematic diagrams of the insulating layers 60 and 61 alternately arranged at intervals are formed on the surfaces of the first semiconductor region 42 and the second semiconductor region 43 by the silk-screen printing technique in S5. The insulating layers 60 and 61 are made of insulating ink, the thickness of the insulating ink is 3-25um, the length of the insulating ink is 5-15mm, the width of the insulating ink is 0.5-0.8mm, and the insulating ink is formed by baking at 150 ℃ for 5-10M and curing. The insulating layer 60 covers the first semiconductor region 42 and the isolation trench 53 on the same level; the insulating layer 61 covers the second semiconductor region 43 and the isolation trench 53 on the same horizontal level.
As shown in fig. 21-22, a cross-sectional view and a structural schematic diagram of metal gate lines 70/71 alternately arranged with insulating layers 60/61 are formed on the surfaces of the first semiconductor region 42 and the second semiconductor region 43 by a screen printing technique S6. The metal grid lines comprise thin grid lines 70F/71F and main grid lines 70B/71B, the metal grid lines 70/71 are 10-20 columns in total, the material is one of low-temperature silver paste and weldable silver-coated copper paste, the thin grid lines 70F/71F and the main grid lines 70B/71B are formed in a silk-screen mode at the same time, the thickness is 5-30um, the length is 10-40mm, the thin grid lines are formed by baking 30M at 180 ℃ after silk-screen mode, the metal grid lines 70/71 are alternately arranged on the surfaces of the first semiconductor region 42 and the second semiconductor region 42 at intervals, the metal grid lines 70/71 between the first semiconductor region 42 and the second semiconductor region 42 are mutually insulated, and the insulation resistance is larger than 1K omega. In a preferred embodiment, as shown in fig. 24, a region of the bus bar 70B/71B directly contacting the first semiconductor region 42 or the second semiconductor region 42 may be widened.
This example differs from example 2 in that: s2, only depositing a transparent conductive film layer; and S6, forming a metal grid line which comprises a weldable main grid line and a thin grid line.
By adopting the technical scheme, the double-sided power generation rate of the back contact heterojunction solar cell can reach more than 80%, when the back contact heterojunction solar cell is installed in a field with good back reflection, higher power generation capacity can be obtained, meanwhile, series welding is very convenient when the cell is manufactured into a module, as shown in fig. 23, in order to form a structural schematic diagram after a cell cutting half series welding strip 80 of a metal grid line 70/71, the welding strip 80 performs series welding on a metal main grid line 70B of a first semiconductor region 42 of an adjacent cell and a metal main grid line 71B of a second semiconductor region 43 of the adjacent cell to form a cell string. According to the technical scheme, the use of large-scale wet-process copper electroplating equipment can be avoided, the problems of copper-containing wastewater treatment, environmental protection, large production field, high operation cost and the like do not need to be considered, so that the production process flow of the cell is greatly simplified, the production cost is reduced, and the mass production and popularization of the back contact heterojunction solar cell with high conversion efficiency are facilitated.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not intended to limit the present invention, and any modifications, equivalents, improvements, etc. made within the spirit and principles of the present invention should be included within the scope of the present invention.
Claims (10)
1. A multi-main-gate back-contact heterojunction solar cell is characterized in that: the semiconductor substrate comprises a semiconductor substrate, a plurality of first semiconductor regions and second semiconductor regions which are arranged on a first main surface of the semiconductor substrate and are alternately arranged from left to right, an isolation groove arranged between each first semiconductor region and each second semiconductor region, more than one column of first insulating layer arrays horizontally arranged on each first semiconductor region, more than one column of second insulating layer arrays horizontally arranged on each second semiconductor region, more than one column of first weldable main grid lines which are electrically connected with each first semiconductor region and are in the same horizontal position with each second insulating layer array for welding and corresponding arrangement, and more than one column of second weldable main grid lines which are electrically connected with each second semiconductor region and are in the same horizontal position with each first insulating layer array for corresponding arrangement; the first insulating layer array and the second insulating layer array are staggered from top to bottom.
2. The multi-master-grid back-contact heterojunction solar cell of claim 1, wherein: and a plurality of first thin grids electrically connected with the first weldable main grid line are arranged on each first semiconductor region between two adjacent first insulation layer arrays, and a plurality of second thin grids electrically connected with the second weldable main grid line are arranged on each second semiconductor region between two adjacent second insulation layer arrays.
3. The multi-master-grid back-contact heterojunction solar cell of claim 1 or 2, wherein: an isolation region is arranged between the first semiconductor region and the second semiconductor region, and the isolation groove is arranged on the isolation region.
4. The multi-master-gate back-contact heterojunction solar cell of claim 3, wherein: first semiconductor district includes first type semiconductor film layer and the first electrically conductive rete that forms from the end to the face in proper order with the first principal of semiconductor substrate as the basement, second semiconductor area includes second type semiconductor film layer and the electrically conductive rete of second that forms from the end to the face in proper order with the first principal of semiconductor substrate as the basement, the isolation region includes first type semiconductor film layer, isolation rete, second type semiconductor film layer and the electrically conductive rete of isolation that forms from the end to the face in proper order with the first principal of semiconductor substrate as the basement, the isolation groove will keep apart electrically conductive rete and separate into two parts about.
5. The multi-master-gate back-contact heterojunction solar cell of claim 4, wherein: the first type semiconductor film layer comprises a first passivation layer and a first semiconductor layer which are sequentially formed from bottom to surface by taking a first main surface of a semiconductor substrate as a substrate; the second type semiconductor film layer comprises a second passivation layer and a second semiconductor layer which are sequentially formed from bottom to surface by taking the first main surface of the semiconductor substrate as a bottom surface; the first conductive film layer, the second conductive film layer and the isolation conductive film layer respectively comprise transparent conductive layers formed by taking the corresponding semiconductor layers as substrates; the isolation film layer comprises an isolation insulating layer formed on the isolation region by taking the first semiconductor layer as a substrate.
6. The multi-master-grid back-contact heterojunction solar cell of claim 5, wherein: the first conductive film layer, the second conductive film layer and the isolation conductive film layer comprise metal conductive layers formed by taking the transparent conductive layer as a substrate.
7. The multi-master-grid back-contact heterojunction solar cell of claim 5, wherein: the first passivation layer and the second passivation layer respectively comprise intrinsic amorphous silicon layers and/or intrinsic microcrystalline silicon layers.
8. The multi-master-gate back-contact heterojunction solar cell of claim 5, wherein: the first semiconductor layer and the second semiconductor layer comprise an N-type doped amorphous silicon/microcrystalline silicon layer or a P-type doped amorphous silicon/microcrystalline silicon layer, when the first semiconductor layer is the N-type doped amorphous silicon/microcrystalline silicon layer, the second semiconductor layer is the P-type doped amorphous silicon/microcrystalline silicon layer, and when the first semiconductor layer is the P-type doped amorphous silicon/microcrystalline silicon layer, the second semiconductor layer is the N-type doped amorphous silicon/microcrystalline silicon layer; the isolation film layer comprises at least one of a silicon nitride layer, a silicon oxide layer and a silicon carbide layer.
9. The multi-master-gate back-contact heterojunction solar cell of claim 3, wherein: the first weldable main grid line and the first weldable main grid line are a weldable low-temperature silver paste layer, a weldable silver-clad copper paste layer or a weldable nickel paste layer, the thickness of the first weldable main grid line and the first weldable main grid line is 5-30um, and the width of the first weldable main grid line and the first weldable main grid line is 0.04-10mm.
10. The multi-master-gate back-contact heterojunction solar cell of claim 9, wherein: the first insulating layer array and the second insulating layer array are insulating gloss oil layers or insulating ink layers, the thickness is 3-25um, and the width is 0.3-1mm.
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