CN218272592U - Edge detection circuit without logic device - Google Patents
Edge detection circuit without logic device Download PDFInfo
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- CN218272592U CN218272592U CN202222166447.9U CN202222166447U CN218272592U CN 218272592 U CN218272592 U CN 218272592U CN 202222166447 U CN202222166447 U CN 202222166447U CN 218272592 U CN218272592 U CN 218272592U
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Abstract
The utility model relates to a detect technical field, disclose a no logic device's border detection circuitry. The method comprises the following steps: the edge detection circuit includes: the power input end of the power input module is connected with an external power supply, the power output end of the power input module is connected with the power input end of the control module without the logic device, the signal output end of the signal generation module is connected with the signal input end of the control module without the logic device, and the signal output end of the control module without the logic device is connected with the signal input end of the signal load module. The power supply input module, the signal generation module, the signal load module and the control module without logic devices are adopted, so that the realization is simple and reliable, no logic devices and no integrated chips are needed, the cost is low, the reliability is high, and the like. The control module without the logic device OUTPUTs a short-time pulse at the OUTPUT end when the INPUT end of the edge detection circuit without the logic device has a level change.
Description
Technical Field
The utility model relates to a detect technical field, concretely relates to no logic device's border detection circuit.
Background
Along with the development of electronic science and technology, electronic products are widely used in various fields, a new era of electronic intelligence is started, along with the appearance of electronic products full of precious objects, the change of some electronic signals needs to be sensed sometimes to make some corresponding actions, a plurality of signal detection circuits in the current market adopt an integrated chip to perform logic conversion so as to convert electronic signals changing from sources into required electronic change signals, the logic circuits used by the signal detection circuits are complex, the cost is high, the reliability is weak, the influence of errors of the signals often appears, and the detection information is inaccurate.
Therefore, in view of the above problems, the existing detection circuit is yet to be further improved.
SUMMERY OF THE UTILITY MODEL
The utility model aims at overcoming the complicated structure of current detection circuitry, with high costs, the reliability is poor, inaccurate scheduling problem, adopting power input module, signal generation module, signal load module and no logic device control module, can realize simply reliably, need not any logic device and need not integrated chip to and low-cost, the reliability is high. Particularly, the edge detection circuit without the logic device is composed of a PMOS (Q1), an NMOS (Q2), a plurality of resistors and capacitors by adopting the control module without the logic device, when the INPUT end has a level change, a short-time pulse is OUTPUT at the OUTPUT end so as to be convenient for capturing a signal at a load end, and a storage battery or alternating current is adopted for supplying power, so that a stable required power supply can be provided for the control module without the logic device.
The technical scheme of the utility model is specifically as follows:
an edge detection circuit without a logic device, the edge detection circuit comprising: the power input end of the power input module is connected with an external power supply, the power output end of the power input module is connected with the power input end of the logic-free device control module, the signal output end of the signal generation module is connected with the signal input end of the logic-free device control module, and the signal output end of the logic-free device control module is connected with the signal input end of the signal load module.
Further, no logic device control module includes no logic device control circuit, no logic device control circuit includes resistance R1, resistance R2, resistance R3, resistance R4, resistance R5, electric capacity C1, electric capacity C2, LED1, LED2, PMOS pipe Q1 and NMOS pipe Q2, PMOS pipe Q1's source electrode parallel connection the power output end of power input module, resistance R2 one end and resistance R1 one end, resistance R2 other end parallel connection the grid and the electric capacity C1 one end of PMOS pipe Q1, electric capacity C1 other end parallel connection electric capacity C2 one end, LED2 are anodal and the signal output end of signal generation module, LED2 negative pole is connected resistance R4 one end, resistance R4 other end ground connection, electric capacity C2 other end parallel connection resistance R3 one end, resistance R5 one end and the grid of NMOS pipe Q2, the resistance R5 other end and NMOS pipe Q2's source electrode common ground connection, the drain electrode of resistance R3 other end connection pipe Q1, the drain electrode of NMOS pipe Q2 is connected to the load signal input of the negative pole of signal module and the LED1, the LED1 is connected to the negative pole of NMOS pipe Q1.
Further, the power input module comprises a power input circuit, and the power input circuit is a storage battery power supply circuit and/or an alternating current power supply circuit.
Further, the alternating current power supply circuit comprises a fuse F1, a piezoresistor R11, a thermistor RT1, a capacitor C11, a bridge rectifier DB1, a resistor R12, an inductor L1, a capacitor C12, a capacitor C4, a capacitor C15, a capacitor C22, a capacitor C23, an inductor L2, an inductor L3, a transformer T1, a diode D5, a diode D6, a capacitor C17, a freewheeling diode D1, an inductor L4, a resistor R13 and a capacitor C8, wherein a power live wire L is connected with one end of the fuse F1, the other end of the fuse F1 is connected with one end of the piezoresistor R11, one end of the capacitor C11 and a first input end of the bridge rectifier DB1 in parallel, a power zero line N is connected with one end of the thermistor RT1, the other end of the thermistor RT1 is connected with the other end of the piezoresistor R11, the other end of the capacitor C11 and a second input end of the bridge rectifier DB1 in parallel, a first output end of the bridge rectifier DB1 is connected with one end of the resistor R12, the second output end of the bridge rectifier DB1 is grounded, the other end of the resistor R12 is connected in parallel with one end of the capacitor C12 and one end of the inductor L1, the other end of the inductor L1 is connected in parallel with one end of the capacitor C4, one end of the capacitor C15 and one end of the inductor L2, the other end of the capacitor C12 and the other end of the capacitor C4 are grounded together, the other end of the capacitor C15 is connected with the cathode of the diode D6, the anode of the diode D6 is connected with one end of the capacitor C22, the other end of the inductor L2 is connected in parallel with one end of the inductor L3 and the first input end of the transformer T1, the other end of the capacitor C22 is connected in parallel with the other end of the inductor L3, the second input end of the transformer T1 and the cathode of the diode D5, the anode of the diode D5 is connected with one end of the capacitor C23, the other end of the capacitor C23 is grounded, and the first output end of the transformer T1 is connected with the anode of the freewheeling diode D1, the negative electrode of the fly-wheel diode D1 is connected with one end of the capacitor C17 and one end of the inductor L4 in parallel, the other end of the inductor L4 is connected with one end of the resistor R13, one end of the capacitor C8 and the VCC output end in parallel, and the other end of the resistor R13, the other end of the capacitor C8, the second output end of the transformer T1 and the other end of the capacitor C17 are grounded in common.
Further, the signal generation module selects a temperature controller.
Further, the model of the temperature controller is selected from W1209, W3230 or W1641.
Further, the signal load module selects a refrigeration equipment compressor.
Advantageous effects
The utility model discloses an adopt power input module, signal generation module, signal load module and no logic device control module, can realize simple reliable, need not any logic device and need not integrated chip to and low cost, the reliability is high. Particularly, the edge detection circuit without the logic device is composed of a PMOS (Q1), an NMOS (Q2), a plurality of resistors and capacitors, when the level of an INPUT end changes, a short-time pulse can be OUTPUT at an OUTPUT end so as to facilitate signal capture of a load end, a storage battery or alternating current is adopted for supplying power, a stable required power supply can be provided for the control module without the logic device, and the circuit system can be widely applied to the aspect of signal change collection.
Drawings
Fig. 1 is a schematic diagram of an edge detection circuit without a logic device according to the present invention.
Fig. 2 is a schematic diagram of a power input circuit of an edge detection circuit without a logic device according to the present invention.
Reference numerals: 01. a signal generation module; 02. a power input module; 03. a signal load module; 04. and a control module without logic devices.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
Referring to fig. 1 and fig. 2, the present invention provides an edge detection circuit without logic device, which includes: the power supply control module comprises a power supply input module 02, a signal generation module 01, a signal load module 03 and a control module 04 without logic devices, wherein the power supply input end of the power supply input module 02 is connected with an external power supply, the power supply output end of the power supply input module 02 is connected with the power supply input end of the control module 04 without logic devices, the signal output end of the signal generation module 01 is connected with the signal input end of the control module 04 without logic devices, and the signal output end of the control module 04 without logic devices is connected with the signal input end of the signal load module 03.
The control module 04 without the logic device comprises a control circuit without the logic device, and the control circuit without the logic device comprises a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a capacitor C1, a capacitor C2, an LED1, an LED2, a PMOS tube Q1 and an NMOS tube Q2; the power input module comprises a power input circuit, the power input circuit is an alternating current power supply circuit, and the alternating current power supply circuit comprises a fuse F1, a piezoresistor R11, a thermistor RT1, a capacitor C11, a bridge rectifier DB1, a resistor R12, an inductor L1, a capacitor C12, a capacitor C4, a capacitor C15, a capacitor C22, a capacitor C23, an inductor L2, an inductor L3, a transformer T1, a diode D5, a diode D6, a capacitor C17, a freewheeling diode D1, an inductor L4, a resistor R13 and a capacitor C8; the signal generation module selects a temperature controller, and the model of the temperature controller is selected from W1209, W3230 or W1641; the signal load module selects a refrigeration equipment compressor;
wherein, the live wire L of the power supply is connected with one end of a fuse F1, the other end of the fuse F1 is connected with one end of a piezoresistor R11, one end of a capacitor C11 and a first input end of a bridge rectifier DB1 in parallel, the zero line N of the power supply is connected with one end of a thermistor RT1, the other end of the thermistor RT1 is connected with the other end of the piezoresistor R11, the other end of the capacitor C11 and a second input end of the bridge rectifier DB1 in parallel, the first output end of the bridge rectifier DB1 is connected with one end of a resistor R12, the second output end of the bridge rectifier DB1 is grounded, the other end of the resistor R12 is connected with one end of a capacitor C12 and one end of an inductor L1 in parallel, the other end of the inductor L1 is connected with one end of a capacitor C4, one end of a capacitor C15 and one end of an inductor L2 in parallel, the other end of the capacitor C12 and the other end of the capacitor C4 are grounded, the other end of the capacitor C15 is connected with the cathode of a diode D6, the anode of the diode D6 is connected with one end of a capacitor C22, the other end of the inductor L2 is connected with one end of the first input end of a transformer T1 in parallel, the other end of the capacitor C22 is connected in parallel with the other end of the inductor L3, the second input end of the transformer T1 and the cathode of the diode D5, the anode of the diode D5 is connected with one end of the capacitor C23, the other end of the capacitor C23 is grounded, the first output end of the transformer T1 is connected with the anode of the freewheeling diode D1, the cathode of the freewheeling diode D1 is connected in parallel with one end of the capacitor C17 and one end of the inductor L4, the other end of the inductor L4 is connected in parallel with one end of the resistor R13, one end of the capacitor C8 and the VCC output end, the other end of the resistor R13, the other end of the capacitor C8, the second output end of the transformer T1 and the other end of the capacitor C17 are grounded together, the source of the PMOS tube Q1 is connected in parallel with one end of the capacitor C8, one end of the resistor R2 and one end of the resistor R1 of the power input circuit, the other end of the resistor R2 is connected in parallel with the gate of the PMOS tube Q1 and one end of the capacitor C1, the other end of the capacitor C1 is connected in parallel with one end of the capacitor C2, the anode of the LED2 and the signal output end of the temperature controller of the signal generating module, LED2 negative pole connecting resistance R4 one end, the ground connection of the resistance R4 other end, electric capacity C2 other end parallel connection resistance R3 one end, resistance R5 one end and NMOS pipe Q2's grid, the resistance R5 other end and NMOS pipe Q2's source electrode common ground, PMOS pipe Q1's drain electrode is connected to the resistance R3 other end, NMOS pipe Q2's drain electrode parallel connection signal load module's the refrigeration plant compressor's signal input part and LED 1's negative pole, LED 1's the anodal connecting resistance R1 other end.
The specific implementation working principle is as follows: when the signal output (INPUT) of the temperature controller is at a stable high level, the voltage at the other end (left side) of the capacitor C1 is equal to the voltage VCC at one end (right side) of the capacitor C1, the voltage at the two ends of the capacitor C1 is 0, and the PMOS tube Q1 is cut off; the voltage at one end (left side) of the capacitor C2 is high voltage VCC, the voltage at the right side is pulled down by the resistor R5 and is 0, the NMOS tube Q2 is cut off, the voltage at two ends of the capacitor C2 is VCC, and the voltage is positive left and negative right;
when the signal OUTPUT (INPUT) of the temperature controller jumps from a high level to a low level, because the voltage of a capacitor C1 cannot jump suddenly, the grid of a PMOS (P-channel metal oxide semiconductor) tube Q1 changes to a low level along with the INPUT signal, at the moment, the PMOS tube Q1 is switched on, voltage VCC is added to a resistor R3 and a resistor R5 and then is added to the grid of an NMOS (N-channel metal oxide semiconductor) tube Q2, the NMOS tube Q2 is switched on, a low level is OUTPUT at the OUTPUT end, because the resistor R2 can charge the capacitor C1, when the charging is finished, the grid of the PMOS tube Q1 also changes to a high level, the PMOS tube Q1 is switched off, the NMOS tube Q2 is switched off, and then when the INPUT signal jumps from a high level to a low level, a short-time low level is OUTPUT at the OUTPUT end;
when the INPUT signal is at a stable low level, the voltage on the left side of the capacitor C1 is 0, the voltage on the right side of the capacitor C1 is VCC, and the PMOS transistor Q1 is turned off; the voltage on the left side of the capacitor C2 is 0, the voltage on the right side of the capacitor C2 is 0, the voltage on the two ends of the capacitor C2 is 0, and the NMOS tube Q2 is cut off; when the INPUT signal jumps from low to high, the voltage at the two ends of the capacitor C2 can not suddenly change, so that the voltage on the right side of the capacitor C2 changes to the voltage VCC along with the voltage on the left side, the NMOS tube Q2 is conducted, the OUTPUT of the OUTPUT is low level, the voltage on the right side of the capacitor C2 also gradually changes to 0 as the capacitor C2 is charged gradually through the resistor R5, the NMOS tube Q2 is cut off, and then when the INPUT jumps from low to high, a short low level is OUTPUT at the OUTPUT.
By using the charging and discharging of the capacitor C1 and the capacitor C2, when INPUT has a transition edge, OUTPUT will get a short low-level pulse without using any logic device for switching.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (7)
1. An edge detection circuit without a logic device, the edge detection circuit comprising: the power input end of the power input module is connected with an external power supply, the power output end of the power input module is connected with the power input end of the logic-free device control module, the signal output end of the signal generation module is connected with the signal input end of the logic-free device control module, and the signal output end of the logic-free device control module is connected with the signal input end of the signal load module.
2. The edge detection circuit without the logic device according to claim 1, wherein the control module without the logic device comprises a control circuit without the logic device, the control circuit without the logic device comprises a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a capacitor C1, a capacitor C2, an LED1, an LED2, a PMOS transistor Q1 and an NMOS transistor Q2, a source electrode of the PMOS transistor Q1 is connected in parallel with a power output end of the power input module, one end of the resistor R2 and one end of the resistor R1, the other end of the resistor R2 is connected in parallel with a gate electrode of the PMOS transistor Q1 and one end of the capacitor C1, the other end of the capacitor C1 is connected in parallel with one end of the capacitor C2, an anode of the LED2 and a signal output end of the signal generation module, a cathode electrode of the LED2 is connected with one end of the resistor R4, the other end of the resistor R4 is grounded, the other end of the capacitor C2 is connected in parallel with one end of the resistor R3 and a gate electrode of the NMOS transistor Q2, the other end of the resistor R5 is connected in common with a source electrode of the NMOS transistor Q2, the other end of the resistor R3 is connected with a drain electrode of the NMOS transistor Q1, and the drain electrode of the load module are connected with a drain electrode of the signal input end of the PMOS transistor Q1, and the drain electrode of the signal input end of the signal input module.
3. The edge detection circuit without logic device as claimed in claim 1, wherein the power input module comprises a power input circuit, and the power input circuit is a battery supply circuit and/or an alternating current supply circuit.
4. The logic device-less edge detection circuit according to claim 3, wherein the AC power supply circuit comprises a fuse F1, a voltage dependent resistor R11, a thermistor RT1, a capacitor C11, a bridge rectifier DB1, a resistor R12, an inductor L1, a capacitor C12, a capacitor C4, a capacitor C15, a capacitor C22, a capacitor C23, an inductor L2, an inductor L3, a transformer T1, a diode D5, a diode D6, a capacitor C17, a freewheeling diode D1, an inductor L4, a resistor R13 and a capacitor C8, wherein the power supply live line L is connected to one end of the fuse F1, the other end of the fuse F1 is connected in parallel to one end of the voltage dependent resistor R11, one end of the capacitor C11 and the first input end of the bridge rectifier DB1, the power supply neutral line N is connected to one end of the thermistor RT1, the other end of the thermistor RT1 is connected in parallel to the other end of the voltage dependent resistor R11, the other end of the capacitor C11 and the second input end of the bridge rectifier DB1, the first output end of the bridge rectifier DB1 is connected with one end of a resistor R12, the second output end of the bridge rectifier DB1 is grounded, the other end of the resistor R12 is connected with one end of a capacitor C12 and one end of an inductor L1 in parallel, the other end of the inductor L1 is connected with one end of a capacitor C4, one end of a capacitor C15 and one end of an inductor L2 in parallel, the other end of the capacitor C12 and the other end of the capacitor C4 are grounded together, the other end of the capacitor C15 is connected with the cathode of a diode D6, the anode of the diode D6 is connected with one end of a capacitor C22, the other end of the inductor L2 is connected with one end of an inductor L3 and the first input end of a transformer T1 in parallel, the other end of the capacitor C22 is connected with the other end of the inductor L3, the second input end of the transformer T1 and the cathode of a diode D5 in parallel, the anode of the diode D5 is connected with one end of a capacitor C23, and the other end of a capacitor C23 is grounded, the first output end of the transformer T1 is connected with the anode of the fly-wheel diode D1, the cathode of the fly-wheel diode D1 is connected in parallel with one end of the capacitor C17 and one end of the inductor L4, the other end of the inductor L4 is connected in parallel with one end of the resistor R13, one end of the capacitor C8 and the VCC output end, and the other end of the resistor R13, the other end of the capacitor C8, the second output end of the transformer T1 and the other end of the capacitor C17 are grounded together.
5. The logic device-less edge detection circuit of claim 1, wherein the signal generation module selects the temperature controller.
6. The edge detection circuit without the logic device as claimed in claim 5, wherein the model of the temperature controller is selected from W1209, W3230 or W1641.
7. The logic device-less edge detection circuit of claim 1, wherein the signal load module is selected from a refrigeration equipment compressor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222166447.9U CN218272592U (en) | 2022-08-17 | 2022-08-17 | Edge detection circuit without logic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222166447.9U CN218272592U (en) | 2022-08-17 | 2022-08-17 | Edge detection circuit without logic device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN218272592U true CN218272592U (en) | 2023-01-10 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202222166447.9U Active CN218272592U (en) | 2022-08-17 | 2022-08-17 | Edge detection circuit without logic device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN218272592U (en) |
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2022
- 2022-08-17 CN CN202222166447.9U patent/CN218272592U/en active Active
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