CN218214168U

CN218214168U - Quantum chip and quantum computer

Info

Publication number: CN218214168U
Application number: CN202221932703.4U
Authority: CN
Inventors: 赵勇杰; 曹振; 付耀斌
Original assignee: Origin Quantum Computing Technology Co Ltd
Current assignee: Origin Quantum Computing Technology Co Ltd
Priority date: 2022-07-22
Filing date: 2022-07-22
Publication date: 2023-01-03
Anticipated expiration: 2032-07-22

Abstract

The application discloses quantum chip and quantum computer belongs to quantum computing technology field. The quantum chip includes: sealing the cavity; the first substrate and the second substrate are positioned in the closed cavity, a first qubit is formed on the first substrate, and a second qubit is formed on the second substrate; and a coupling capacitor located within the closed cavity and opposite the first qubit and the second qubit, the coupling capacitor configured to enable coupling between the second qubit and the first qubit. By using the scheme provided by the application, a plurality of substrates formed with the qubits can be integrated, so that the large-scale qubit expansion can be realized.

Description

Quantum chip and quantum computer

Technical Field

The application belongs to the field of quantum information, particularly relates to the technical field of quantum computing, and particularly relates to a quantum chip and a quantum computer.

Background

Quantum computers are physical devices that perform high-speed mathematical and logical operations, store, and process quantum information following quantum mechanics laws. The quantum computer is characterized by high running speed, strong information processing capability, wide application range and the like. Compared with a common computer, the more information processing amount is, the more beneficial the quantum computer to implement operation is, and the more accurate the operation can be ensured.

Quantum chips are the core elements of quantum computers. The quantum chip is realized by various physical systems, such as a superconducting system, a semiconductor quantum dot, an ion trap, a diamond vacancy, a topological quantum, a photon and the like. The superconducting system prepares the quantum bit on the substrate based on the micro-nano processing technology to obtain the superconducting quantum chip, and has superior performances of integration, expandability and the like. In recent years, the superconducting quantum computation is rapidly developed, but a structural form which is beneficial to the integration and expansion of a quantum chip is in need of further optimization.

SUMMERY OF THE UTILITY MODEL

The application aims to provide a quantum chip and a quantum computer, so as to solve the limitation in the aspect of the number expansion of quantum bits on the quantum chip in the prior art.

One aspect of the present application provides a quantum chip, including: sealing the cavity; the first substrate and the second substrate are positioned in the closed cavity, a first qubit is formed on the first substrate, and a second qubit is formed on the second substrate; and a coupling capacitor located within the closed cavity and opposite the first qubit and the second qubit, the coupling capacitor configured to enable coupling between the second qubit and the first qubit.

In some embodiments, the closed cavity includes a substrate and a shielding shell, the shielding shell has an insulating dielectric layer formed on an inner wall thereof, the coupling capacitor is formed on the insulating dielectric layer, and the first substrate and the second substrate are connected to the substrate.

In some embodiments, the shielding case includes a metal layer, and the insulating medium layer includes a metal oxide layer formed on a surface of the metal layer.

In some embodiments, the first qubit has a first capacitive plate, the second qubit has a second capacitive plate, and the first and second capacitive plates are coplanar.

In some embodiments, the coupling capacitor comprises a capacitor plate, and the capacitor plate covers the first capacitor plate and the second capacitor plate.

In some embodiments, the first substrate is formed with a first reading cavity, the second substrate is formed with a second reading cavity, the substrate is formed with a first reading signal line and a second reading signal line, the first qubit, the first reading cavity and the first reading signal line are coupled in sequence, and the second qubit, the second reading cavity and the second reading signal line are coupled in sequence.

In some embodiments, the first read cavity extends from one surface of the first substrate to the other surface of the first substrate; and/or the second reading cavity extends from one surface of the second substrate to the other surface of the second substrate.

In some embodiments, the substrate further has control signal lines formed thereon, and each of the control signal lines is coupled to the first qubit or the second qubit.

As described above, in some embodiments, the control signal line is coupled to the first qubit or the second qubit via a first element.

As described above, in some embodiments, the interconnect element includes a first portion and a second portion joining the first portion and the control signal line, the first portion penetrating through the first substrate or the second substrate.

Another aspect of the application provides a quantum computer comprising a quantum chip as described above.

Compared with the prior art, the coupling capacitor, the first substrate with the first qubit and the second substrate with the second qubit are arranged in the closed cavity, the first qubit and the second qubit which are opposite to the coupling capacitor are mutually coupled by the coupling capacitor, and therefore integration of a plurality of substrates with the qubits is achieved, and further the large-scale qubit expansion is facilitated.

Drawings

Fig. 1 is a schematic structural diagram of a qubit arranged on a quantum chip in the related art;

fig. 2 is a schematic structural diagram of a quantum chip according to an embodiment of the present disclosure.

Description of reference numerals:

1-first substrate, 11-first qubit, 12-first further bit, 13-first read cavity;

2-a second substrate, 21-a second qubit, 22-a second further bit, 23-a second read cavity;

3-substrate, 31-first read signal line, 32-second read signal line, 33-first control signal line,

34-a second control signal line;

4-shielding shell, 41-insulating medium layer, 42-coupling capacitor;

5-interconnect element, 51-first element, 52-second element.

Detailed Description

The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.

To further clarify objects, features and advantages of embodiments of the present application, one or more embodiments are now described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a more thorough understanding of one or more embodiments. It may be evident, however, that one or more embodiments may be practiced in various instances without these specific details, and that the various embodiments may be incorporated by reference into each other without departing from the scope of the present disclosure.

It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the accompanying drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

In addition, it will be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and/or pattern, it can be directly on the other layer or substrate, and/or intervening layers may also be present. In addition, it will be understood that when a layer is referred to as being "under" another layer, it can be directly under the other layer, and/or one or more intervening layers may also be present. In addition, references to "on" and "under" layers may be made based on the drawings.

According to different physical systems adopted for constructing the qubits, the qubits include superconducting quantum circuits, semiconductor quantum dots, ion traps, diamond vacancies, topological quanta, photons and the like in a physical implementation manner. Superconducting quantum computing is the best solid quantum computing implementation method which is developed at present. Because the energy level structure of the superconducting quantum circuit can be regulated and controlled by an external electromagnetic signal, the controllability of the design customization of the circuit is strong. Meanwhile, the superconducting quantum circuit has expandability which is incomparable with most quantum physical systems due to the existing mature integrated circuit process.

Fig. 1 is a schematic structural diagram of a qubit arranged on a quantum chip in the related art.

The key component of the superconducting quantum chip is a Josephson junction, and Transmons is used as a commonly used qubit structure of the superconducting quantum chip, the basic idea is that the Josephson junction and an additionally constructed capacitor plate are connected in parallel to form an energy level system, and as shown in a figure 1, the structure of the qubit usually adopts a single capacitor to the ground and a superconducting quantum interference device with one end grounded and the other end connected with the capacitor, and the capacitor is usually a cross-shaped parallel plate capacitor as shown in the figure 1, and a cross-shaped capacitor plate C _q Surrounded by ground plane (GND), and cross-shaped capacitor plate C _q A gap is arranged between the superconducting quantum interference device and a ground plane (GND), and one end of the superconducting quantum interference device is connected to the cross-shaped capacitor plate C _q And the other end is connected to the ground plane (GND) due to the cross-shaped capacitor plate C _q The first end of the first end is generally used for connecting a superconducting quantum interference device (squid), the second end is used for coupling with the reading cavity, certain space needs to be reserved near the first end and the second end for wiring, for example, space needs to be reserved near the first end for arranging xy signal lines and z signal lines, and a cross-shaped capacitor plate C _q For coupling with adjacent qubits. The basic concept of the structure is that an energy level system is formed by connecting a Josephson junction and an additionally constructed capacitor plate in parallel, and array arrangement is formed on the surface of a substrate to realize the number expansion of the qubits.

Therefore, the application provides a quantum chip and a quantum computer to solve the limitation in the aspect of the number expansion of quantum bits on the quantum chip in the prior art.

Fig. 2 is a schematic structural diagram of a quantum chip according to a first embodiment of the present application.

Referring to fig. 2 in combination with fig. 1, an embodiment of the present application provides a quantum chip, including: sealing the cavity; a first substrate 1 and a second substrate 2 located in the closed cavity, a first qubit 11 being formed on the first substrate 1, and a second qubit 21 being formed on the second substrate 2; and a coupling capacitor 42 located in the closed cavity and forming an opposite pair with both the first qubit 11 and the second qubit 21, where the coupling capacitor 42 is configured to implement coupling between the second qubit 11 and the first qubit 21, that is, implement cross-substrate coupling communication between the qubits, and in specific implementation, the qubits located at an edge of one substrate may be coupled and communicated with the qubits located at an edge of another substrate, and the qubits of the two substrates are integrated, thereby implementing expansion of the number of the qubits. It is understood that multiple qubits on the same substrate may be brought into coupling communication according to certain rules.

In the embodiment provided by the present application, a plurality of qubits are formed on the first substrate 1, wherein each qubit and another qubit may or may not regularly form coupling communication. Illustratively, a first qubit 11 and a first further bit 12 are formed on the first substrate 1, and a coupling is formed between the first qubit 11 and the first further bit 12. Similarly, a first qubit 21 and a second further bit 22 are formed on the second substrate 2, and a coupling is formed between the second qubit 21 and the second further bit 12. In order to realize the number expansion of the qubits on the quantum chip, the coupling strength between the qubits is increased by using the coupling capacitor 42 opposite to the first qubit 11 and the second qubit 21 in the closed cavity, so that the corresponding qubits on the two substrates can be communicated. Therefore, the substrate formed with the quantum bits is integrated, and the large-scale quantum bit expansion is facilitated.

In some embodiments of the present application, the closed cavity includes a base plate 3 and a shielding case 4 which are interconnected, an insulating dielectric layer 41 is formed on an inner wall of the shielding case 4, the coupling capacitor 42 is formed on the insulating dielectric layer 41, and the first substrate 1 and the second substrate 2 are connected to the base plate 3. The shield case 4 may be metal, ceramic, plastic, or the like formed with a coating material or plating layer. In some embodiments of the present application, the shielding case 4 includes a metal layer, and the insulating medium layer 41 includes a metal oxide layer formed on a surface of the metal layer.

The structure of a qubit employs a superconducting quantum interference device, squid, and a capacitive plate, in some embodiments of the application, the first qubit 11 has a first capacitive plate, the second qubit 21 has a second capacitive plate, and the first capacitive plate and the second capacitive plate are coplanar. In some embodiments of the present application, the coupling capacitor 42 includes a capacitor plate covering the first and second capacitor plates to enhance the coupling strength between qubits, and the reliable coupling between the first qubit 11 and the second qubit 21 is established based on the coupling formed by the capacitor plate and the first and second capacitor plates, respectively.

In some embodiments of the present application, to increase the surface space on the substrate where the qubit can be constructed, a signal line or the like may be formed on the surface of the substrate 3, and for example, the following embodiments may be adopted: the first substrate 1 is formed with a first reading cavity 13, the second substrate 2 is formed with a second reading cavity 23, a first reading signal line 31 and a second reading signal line 32 are formed on the base plate 3, the first qubit 11, the first reading cavity 13 and the first reading signal line 31 are coupled in sequence, and the second qubit 21, the second reading cavity 23 and the second reading signal line 32 are coupled in sequence.

In some embodiments of the present application, the first reading chamber 13 extends from one surface of the first substrate 1 to the other surface of the first substrate 1; in still other embodiments of the present application, the second read chamber 23 extends from one surface of the second substrate 2 to the other surface of the second substrate 2. That is, the first reading chamber 13 and the second reading chamber 23 may be selected to be constructed across the surface. Illustratively, the first portion of the first reading chamber 13 is located on the top surface of the first substrate 1, the second portion is located on the bottom surface of the first substrate 1, and the electrical connection between the first portion and the second portion is realized by an electrical structure penetrating through the top surface and the bottom surface, wherein the electrical structure penetrating through the top surface and the bottom surface can be electrically connected by a TSV structure penetrating through the top surface and the bottom surface of the base 3, the TSV structure including a via hole and a superconducting material layer filled in the via hole. This form helps to further reduce the footprint of the physical structure of the read chamber on the surface of the substrate used to form the qubit, increasing the surface space on the substrate in which the qubit can be built.

In some embodiments of the present application, control signal lines are further formed on the substrate 3, and each of the control signal lines is coupled to the first qubit 11 or the second qubit 21. In some embodiments of the present application, the control signal line is coupled to the first qubit 11 or the second qubit 21 via an interconnection element 5. Illustratively, the first control signal line 33 is coupled to the first qubit 11, and the second control signal line 34 is coupled to the second qubit 21, where in particular, the first control signal line 33 may be coupled to the first qubit 11 via a first element 51, and the second control signal line 34 may be coupled to the second qubit 21 via a second element 52. The first control signal line 33 and the second control signal line 34 are used for applying a magnetic flux signal for adjusting the frequency of the qubit and/or a pulse signal for adjusting the quantum state of the qubit.

In some embodiments of the present application, the interconnection element 5 includes a first portion and a second portion joining the first portion and the control signal line, the first portion penetrating through the first substrate 1 or the second substrate 2. The first portion may be a TSV structure formed through top and bottom surfaces of the first or second substrates 1, 2, through which a cross-plane electrical connection is made, wherein an end of the TSV structure coplanar with the first or second qubit 11, 21 may be coupled to the first or second qubit 11, 21.

Here, it should be noted that: the quantum chip provided in the quantum computer has a structure similar to that in the above quantum chip embodiment, and has the same beneficial effects as those in the above superconducting qubit embodiment, and therefore, no further description is given. For technical details not disclosed in the embodiments of the superconducting quantum computer of the present application, those skilled in the art should refer to the description of the superconducting structure above for understanding, and for saving brevity, will not be described again here.

The construction, features and functions of the present application have been described in detail and illustrated in the drawings, the present application is not limited to the embodiments, but rather the invention is intended to cover all modifications, equivalents and equivalents falling within the spirit and scope of the present application.

Claims

1. A quantum chip, comprising:

sealing the cavity;

a first substrate and a second substrate located in the closed cavity, wherein a first qubit is formed on the first substrate, a second qubit is formed on the second substrate, and the first qubit and the second qubit are both energy level systems formed by connecting a Josephson junction and a capacitance plate in parallel; and (c) a second step of,

a coupling capacitor located within the closed cavity and opposite the first qubit and the second qubit, the coupling capacitor to enable coupling between the second qubit and the first qubit.

2. The quantum chip of claim 1, wherein the closed cavity comprises a substrate and a shielding shell which are interconnected, an insulating dielectric layer is formed on an inner wall of the shielding shell, the coupling capacitor is formed on the insulating dielectric layer, and the first substrate and the second substrate are connected with the substrate.

3. The quantum chip of claim 2, wherein the shielding shell comprises a metal layer, and the insulating dielectric layer comprises a metal oxide layer formed on a surface of the metal layer.

4. The quantum chip of claim 1, wherein the first qubit has a first capacitive plate, wherein the second qubit has a second capacitive plate, and wherein the first capacitive plate and the second capacitive plate are coplanar.

5. The quantum chip of claim 4, wherein the coupling capacitor comprises a capacitor plate, and wherein the capacitor plate covers the first capacitor plate and the second capacitor plate.

6. The quantum chip of claim 2, wherein the first substrate is formed with a first reading cavity, the second substrate is formed with a second reading cavity, the substrate is formed with a first reading signal line and a second reading signal line, the first qubit, the first reading cavity and the first reading signal line are coupled in sequence, and the second qubit, the second reading cavity and the second reading signal line are coupled in sequence.

7. The quantum chip of claim 6, wherein the first read cavity extends from one surface of the first substrate to another surface of the first substrate; and/or the second reading cavity extends from one surface of the second substrate to the other surface of the second substrate.

8. The quantum chip of any one of claims 2 to 3 and 6 to 7, wherein control signal lines are further formed on the substrate, and each control signal line is in coupling connection with the first qubit or the second qubit.

9. The quantum chip of claim 8, wherein the control signal line is coupled to the first qubit or the second qubit via an interconnection element.

10. The quantum chip of claim 9, wherein the interconnect element comprises a first portion and a second portion joining the first portion and the control signal line, the first portion extending through the first substrate or the second substrate.

11. A quantum computer comprising a quantum chip according to any one of claims 1 to 10.