CN218162234U - Balance circuit applied to T-type three-level inverter - Google Patents
Balance circuit applied to T-type three-level inverter Download PDFInfo
- Publication number
- CN218162234U CN218162234U CN202222635306.7U CN202222635306U CN218162234U CN 218162234 U CN218162234 U CN 218162234U CN 202222635306 U CN202222635306 U CN 202222635306U CN 218162234 U CN218162234 U CN 218162234U
- Authority
- CN
- China
- Prior art keywords
- capacitor
- voltage
- power switch
- circuit
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Inverter Devices (AREA)
Abstract
The utility model relates to a be applied to three inverter's of T type balancing circuit relates to the power electronics field. The T-type three-level inverter comprises a first capacitor and a second capacitor; the first end of the first capacitor is connected with the positive direct current bus, the first end of the second capacitor is connected with the second end of the first capacitor, and the second end of the second capacitor is connected with the negative direct current bus; the balance circuit comprises a first power switch, a second power switch and a balance inductor; the first end of the first power switch is connected with a positive direct current bus; the first end of the second power switch is connected with the second end of the first power switch, and the second end of the second power switch is connected with the negative direct-current bus; the first end of the balance inductor is connected with the second end of the first power switch, and the second end of the balance inductor is connected with the second end of the first capacitor. The utility model discloses technical scheme can make the voltage holding balance of the second end of first electric capacity, also can guarantee the high efficiency of whole dc-to-ac converter when symmetrical load.
Description
Technical Field
The utility model relates to a power electronics field especially relates to a be applied to three inverter's of T type balancing circuit.
Background
T-type three-level topology is commonly used in inverter circuits because of its high efficiency. Taking the single-phase T-type three-level inverter shown in fig. 1 as an example, the single-phase T-type three-level inverter includes a capacitor C1, a capacitor C2, a power switch Q1, a power switch Q2, a power switch Q3, a power switch Q4, an inductor L1, and an output capacitor C3. The first end of the capacitor C1 and the first end of the power switch Q1 are both connected to a positive direct-current bus, the second end of the capacitor C1 and the first end of the capacitor C2 are connected to a node Vmid (i.e., a direct-current bus midpoint), the second end of the power switch Q1 is connected to the first end of the power switch Q2, the second end of the capacitor C2 and the second end of the power switch Q2 are connected to a negative direct-current bus, the power switch Q3 and the power switch Q4 are connected to the second end of the node Vmid and the second end of the power switch Q1 in series, the first end of the inductor L1 is connected to the second end of the power switch Q1, the second end of the inductor L1 is connected to the first end and the first alternating-current end L of the output capacitor C3, and the second end of the output capacitor C3 is connected to the node Vmid and the second alternating-current end N. A dc bus voltage Vbus is formed between the positive dc bus and the negative dc bus, the dc bus voltage Vbus is provided by a front stage circuit, and an ac voltage Vac is formed between the first ac terminal L and the second ac terminal N.
The working principle of the T-type three-level inverter is as follows: when the ac voltage Vac is in the positive power-frequency half-cycle, and the power switch Q4 is normally on and the power switch Q1 is turned on, the capacitor C1 charges the inductor L1 and the output capacitor C3, and simultaneously supplies current to the load R1, and a current path is shown by a dotted line on the right side of fig. 2, that is, the current path is a current flowing through the capacitor C1, the power switch Q1, the inductor L1, the output capacitor C3, and the load R1. Since the preceding stage circuit keeps the dc bus voltage Vbus constant, the preceding stage circuit charges the capacitors C1 and C2, and the current path is shown by the dashed line on the left side of fig. 2. Since the capacitor C2 only has a charging current, the voltage of the capacitor C2 increases, and the voltage of the capacitor C1 decreases. When the power switch Q1 is turned off and the power switch Q3 is turned on, the current of the inductor L1 freewheels through the output capacitor C3, the load R1, the power switch Q3 and the power switch Q4, and the current path is shown by the dotted line on the right side of fig. 3.
The working principle of the T-type three-level inverter is as follows: when the ac voltage Vac is in the negative half-cycle of the power frequency, the power switch Q3 is normally on, and the power switch Q2 is turned on, the capacitor C2 charges the inductor L1 and the output capacitor C3, and simultaneously supplies current to the load R1, where a current path is shown by a dotted line on the right side of fig. 4, that is, the current path is a current flowing through the capacitor C2, the power switch Q2, the inductor L1, the output capacitor C3, and the load R1. Since the preceding stage will keep the dc bus voltage Vbus constant, the preceding stage will charge the capacitor C1 and the capacitor C2, and the current path is shown by the dashed line on the left side of fig. 4. Since the capacitor C1 only has a charging current, the voltage of the capacitor C1 increases, and the voltage of the capacitor C2 decreases. When the power switch Q2 is turned off and the power switch Q4 is turned on, the current of the inductor L1 freewheels through the output capacitor C3, the load R1, the power switch Q3 and the power switch Q4, and the current path is shown by the dashed line on the right side of fig. 5.
Fig. 6 is a graph of the ac voltage Vac and the current Iac waveform on a purely resistive load R1. The current Iac is symmetrical in a power frequency positive and negative period, the voltage of the capacitor C2 is increased and the voltage of the capacitor C1 is reduced in a power frequency positive half period, the voltage of the capacitor C1 is increased and the voltage of the capacitor C2 is reduced in a power frequency negative half period, so that the voltage of the node Vmid fluctuates at a 1/2Vbus point, and the average value of the voltage is 1/2Vbus.
Fig. 7 is a waveform diagram of the current Iac on the load R1 when it is asymmetrical during the power frequency positive and negative half cycles. The voltage of the node Vmid will deviate from 1/2Vbus seriously, which makes the circuit work abnormally, there is current flowing through the load R1 in the positive half period, the current flowing through the load R1 in the negative half period is 0, there is only charging current but no discharging current on the capacitor C2, the voltage of the capacitor C2 will be charged to be equal to the voltage Vbus of the dc bus, and the voltage of the capacitor C1 will be discharged to 0, i.e. the midpoint of the dc bus is unbalanced.
SUMMERY OF THE UTILITY MODEL
The utility model provides a balanced circuit applied to a T-shaped three-level inverter, which comprises a first capacitor and a second capacitor; the first end of the first capacitor is connected with a positive direct current bus, the first end of the second capacitor is connected with the second end of the first capacitor, and the second end of the second capacitor is connected with a negative direct current bus; the balancing circuit includes:
a first power switch, a first end of the first power switch being connected to the positive DC bus;
a first end of the second power switch is connected with a second end of the first power switch, and a second end of the second power switch is connected with the negative direct current bus; and
and a first end of the balanced inductor is connected with a second end of the first power switch, and a second end of the balanced inductor is connected with a second end of the first capacitor.
Furthermore, the balancing circuit further includes a control circuit, and the control circuit is connected to the control terminal of the first power switch and the control terminal of the second power switch, and is configured to output a first control signal and a second control signal, so as to control the first power switch and the second power switch to be turned on or off, respectively.
Furthermore, the balancing circuit further comprises a first voltage sampling circuit and a second voltage sampling circuit; the first voltage sampling circuit and the second voltage sampling circuit are both connected to the control circuit; the first voltage sampling circuit is coupled to two ends of the first capacitor and used for detecting the voltage of the first capacitor, and the second voltage sampling circuit is coupled to two ends of the second capacitor and used for detecting the voltage of the second capacitor; the control circuit is used for receiving the voltage of the first capacitor and the voltage of the second capacitor and outputting the first control signal and the second control signal.
Furthermore, the control circuit is configured to control the first power switch or the second power switch to be turned on when a voltage difference between the voltage of the first capacitor and the voltage of the second capacitor exceeds a first threshold, so as to balance the voltage at the second end of the first capacitor.
Furthermore, the control circuit is configured to control the second power switch to be turned on when the voltage of the second capacitor exceeds a second threshold.
Furthermore, the control circuit controls the first power switch to be turned on when the voltage of the first capacitor exceeds a third threshold.
Furthermore, the control circuit is configured to control the first power switch or the second power switch to be turned on, so that the balanced inductor operates in an intermittent mode.
Furthermore, when the voltage of the first capacitor is greater than the voltage of the second capacitor, the duty ratio of the first control signal is less than Vc 2/(Vc 1+ Vc 2), where Vc1 is the voltage of the first capacitor and Vc2 is the voltage of the second capacitor.
Furthermore, when the voltage of the second capacitor is greater than the voltage of the first capacitor, the duty ratio of the second control signal is less than Vc 1/(Vc 1+ Vc 2), where Vc1 is the voltage of the first capacitor and Vc2 is the voltage of the second capacitor.
Furthermore, the peak current value of the balanced inductor is (Vc 1/L) × Ton, where L is the inductance value of the balanced inductor, and Ton is the time period when the first control signal is at the high level.
In the embodiment of the present invention, the balancing circuit applied to the T-type three-level inverter includes a first power switch, a second power switch and a balancing inductor. The balancing circuit further comprises a control circuit, and the control circuit controls the conduction of the first power switch or the second power switch according to the voltage of the first capacitor and the voltage of the second capacitor of the T-type three-level inverter, so that the voltage of the second end of the first capacitor (namely the voltage of the connecting node of the first capacitor and the second capacitor) is balanced, and meanwhile, the high efficiency of the whole inverter is ensured when the inverter is symmetrically loaded.
Drawings
Fig. 1 is a schematic structural diagram of a T-type three-level inverter in the prior art.
Fig. 2 is a schematic diagram of a current path of an ac voltage Vac in a power-frequency positive half cycle in the prior art.
Fig. 3 is a schematic diagram of a current freewheeling path in which the ac voltage Vac is in the power-frequency positive half cycle in the prior art.
Fig. 4 is a schematic diagram of a current path of an ac voltage Vac in a power frequency negative half cycle in the prior art.
Fig. 5 is a schematic diagram of a current freewheeling path in which the ac voltage Vac is in a power-frequency negative half cycle in the prior art.
Fig. 6 is a graph of prior art ac voltage Vac and current Iac waveforms on a purely resistive load R1.
Fig. 7 is a waveform diagram of current Iac on load R1 in the prior art when it is asymmetric during both the positive and negative half cycles of power frequency.
Fig. 8 is a schematic structural diagram of a balancing circuit applied to a T-type three-level inverter according to an embodiment of the present invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are only some embodiments, but not all embodiments, of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity, and the same reference numerals denote the same elements throughout. It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relationship terms such as "under 82303030," "under 823030; below," "under 823030; above," "over," etc. may be used herein for convenience of description to describe the relationship of one element or feature to another element or feature illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "at 8230, below" and "at 8230, below" may include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
An embodiment of the present invention provides a balancing circuit applied to a T-type three-level inverter, and particularly, please refer to fig. 8 for a schematic diagram of a balancing circuit applied to a T-type three-level inverter according to an embodiment of the present invention. The utility model discloses a T type three-level inverter of an embodiment includes a electric capacity C1 and second electric capacity C2; the first end of the first capacitor C1 is connected with a positive direct current bus, the first end of the second capacitor C2 is connected with the second end of the first capacitor C1, and the second end of the second capacitor C2 is connected with a negative direct current bus. A direct current bus voltage Vbus is formed between the positive direct current bus and the negative direct current bus, and is provided by a preceding stage circuit. The T-type three-level inverter can be a single-phase three-level inverter circuit or a three-phase three-level inverter circuit. Taking a T-type single-phase three-level inverter as an example, the T-type single-phase three-level inverter includes a power switch Q1, a power switch Q2, a power switch Q3, a power switch Q4, an inductor L1, an output capacitor, a diode D1, and a resistor R1. The first end of first electric capacity C1 is connected with power switch Q1 and positive direct current bus respectively, the first end of second electric capacity C2 is connected with the second end of first electric capacity C1, power switch Q2's first end is connected power switch Q1's second end and is connected, the second end of second electric capacity C2 is connected with power switch Q2's second end and negative direct current bus respectively, power switch Q3 and Q4 series connection are between first electric capacity C1's second end and power switch Q1's second end, wherein power switch Q3 and Q4 are two-way switch. The first end of the inductor L1 is connected with the second end of the power switch Q1, the second end of the inductor L1 is connected with the first end of the output capacitor and the first alternating current end L, the second end of the output capacitor is respectively connected with the second end of the first capacitor C1 and the second alternating current end N, the diode D1 and the resistor R1 which are mutually connected in series are connected between the first alternating current end L and the second alternating current end N, and alternating current voltage Vac is formed between the first alternating current L and the second alternating current end N. The balancing circuit includes a first power switch Q5, a second power switch Q6 and a balancing inductor L2.
The balancing circuit further includes a control circuit (not shown in the figure), which is respectively connected to the control terminal of the first power switch Q5 and the control terminal of the second power switch Q6, and configured to output a first control signal and a second control signal to respectively control on/off of the first power switch Q5 and the second power switch Q6.
The balancing circuit further comprises a first voltage sampling circuit (not shown in the figure) and a second voltage sampling circuit (not shown in the figure); the first voltage sampling circuit and the second voltage sampling circuit are both connected to the control circuit. The first voltage sampling circuit is coupled to two ends of the first capacitor C1, and may be a voltage dividing resistor circuit or a differential sampling circuit, and is configured to detect a voltage of the first capacitor C1, and the second voltage sampling circuit is coupled to two ends of the second capacitor C2, and may be a voltage dividing resistor circuit or a differential sampling circuit, and is configured to detect a voltage of the second capacitor C2; the control circuit is used for receiving the voltage of the first capacitor and the voltage of the second capacitor C2 and outputting the first control signal and the second control signal. The control circuit is configured to control the first power switch Q5 or the second power switch Q6 to be turned on when a voltage difference between the voltage Vc1 of the first capacitor and the voltage Vc2 of the second capacitor exceeds a first threshold, so that the voltages of the second end of the first capacitor C1 are balanced. Specifically, as shown in fig. 7, when the alternating current Iac has current flowing only in the positive half cycle, the voltage of the first capacitor C1 is always decreasing, and the voltage of the second capacitor C2 is always increasing. When the voltage difference between the voltage of the first capacitor C1 and the voltage of the second capacitor C2 exceeds a first threshold, the balancing circuit starts to work, that is, the control circuit controls the first power switch Q5 or the second power switch Q6 to be switched on; when the voltage difference between the voltage of the first capacitor C1 and the voltage of the second capacitor C2 is lower than the first threshold, the balancing circuit stops working, that is, the control circuit controls the first power switch Q5 or the second power switch Q6 to be turned off. Therefore, the voltage of the connection node of the first capacitor C1 and the second capacitor C2 (namely the second end of the first capacitor) can be kept balanced, and the high efficiency of the three-level inverter can be ensured when the three-level inverter is in symmetrical load.
As shown in fig. 8, when the voltage of the second capacitor C2 exceeds the second threshold, the balancing circuit operates. When the alternating current Iac has current only in the positive half cycle in one switching cycle, the control circuit is configured to control the second power switch Q6 to be turned on when the voltage of the second capacitor C2 exceeds a second threshold, and the second capacitor C2 charges the balanced inductor L2, so that the voltage of the second capacitor C2 decreases; when the control circuit controls the second power switch Q6 to be switched off, the balance inductor L2 charges the first capacitor C1 through the body diode of the first power open tube Q5, so that the voltage of the first capacitor C1 rises, and when the voltage of the second capacitor C2 is lower than the second threshold, the balance circuit stops working, so that the voltage of the second end of the first capacitor C1 is balanced.
When the voltage of the first capacitor C1 exceeds a third threshold value, the balancing circuit works. When the voltage of the second capacitor C2 exceeds a second threshold value, the balancing circuit works. When the alternating current Iac has current only in a negative half cycle in one switching period, the control circuit is configured to control the first power switch Q5 to be turned on when the voltage of the first capacitor C1 exceeds a third threshold, and the first capacitor C1 charges the balanced inductor to decrease the voltage of the first capacitor C1; when the control circuit controls the first power switch Q5 to be switched off, the balance inductor charges the second capacitor C2 through the body diode of the second power open tube Q6, so that the voltage of the second capacitor C2 rises, and when the voltage of the first capacitor C1 is lower than the third threshold, the balance circuit stops working, so that the voltage of the second end of the first capacitor C1 is balanced.
In the embodiment, the alternating current Iac is collected by using a hall chip or a current transformer or a current sensor.
In this embodiment, an open-loop control manner is adopted, and the control circuit controls the first power switch Q5 or the second power switch Q6 to be turned on, so that the balanced inductor L2 operates in the discontinuous mode. When the voltage Vc1 of the first capacitor C1 is greater than the voltage Vc2 of the second capacitor C2, i.e. Vc1> Vc2, the first control signal theoretically has the maximum duty ratio
= Vc 2/(Vc 1+ Vc 2). To ensure that the balanced inductor L2 operates in the discontinuous mode completely, the actual duty cycle of the first control signal is taken to be < Vc 2/(Vc 1+ Vc 2). When the voltage Vc2 of the second capacitor C2 is greater than the voltage Vc1 of the second capacitor C1, i.e., vc2> Vc1, the second control signal theoretically has the maximum duty ratio = Vc 1/(Vc 1+ Vc 2). To ensure that the balanced inductor L2 operates in the discontinuous mode completely, the actual duty cycle of the second control signal < Vc 1/(Vc 1+ Vc 2) is taken.
In this embodiment, the control circuit may be a digital controller.
In this embodiment, the peak current value of the balanced inductor L2 is (Vc 1/L) × Ton, where L is the inductance value of the balanced inductor, and Ton is the time period when the first control signal is at the high level. Since the balance inductor L2 operates in the discontinuous mode, and the current peak value of the balance inductor L2 can be obtained by the above calculation, the current value of the balance inductor L2 is not required to be obtained by hardware sampling, and open-loop control can be achieved. The control circuit calculates Ton according to the voltage of the first capacitor C1 and the voltage of the second capacitor C2, and controls the on-time of the first power switch Q5 or the second power switch Q6 through the Ton, thereby realizing the balance control of the node connected with the first capacitor C1 and the second capacitor C2.
The above embodiment can balance the voltage of the second end of the first capacitor C2 and ensure high efficiency of the whole inverter when the inverter is symmetrically loaded.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications or substitutions do not depart from the scope of the invention in its corresponding aspects.
Claims (10)
1. A balance circuit applied to a T-type three-level inverter is characterized by comprising a first capacitor and a second capacitor; the first end of the first capacitor is connected with a positive direct current bus, the first end of the second capacitor is connected with the second end of the first capacitor, and the second end of the second capacitor is connected with a negative direct current bus; the balancing circuit includes:
a first power switch, a first end of the first power switch being connected to the positive DC bus;
a first end of the second power switch is connected with a second end of the first power switch, and a second end of the second power switch is connected with the negative direct current bus; and
and a first end of the balanced inductor is connected with a second end of the first power switch, and a second end of the balanced inductor is connected with a second end of the first capacitor.
2. The balancing circuit applied to the T-type three-level inverter according to claim 1, further comprising a control circuit, wherein the control circuit is respectively connected to the control terminal of the first power switch and the control terminal of the second power switch, and is configured to output a first control signal and a second control signal to respectively control the first power switch and the second power switch to be turned on or off.
3. The balancing circuit applied to the T-type three-level inverter according to claim 2, further comprising a first voltage sampling circuit and a second voltage sampling circuit; the first voltage sampling circuit and the second voltage sampling circuit are both connected to the control circuit; the first voltage sampling circuit is coupled to two ends of the first capacitor and used for detecting the voltage of the first capacitor, and the second voltage sampling circuit is coupled to two ends of the second capacitor and used for detecting the voltage of the second capacitor; the control circuit is used for receiving the voltage of the first capacitor and the voltage of the second capacitor and outputting the first control signal and the second control signal.
4. The balancing circuit applied to the T-type three-level inverter according to claim 3, wherein the control circuit is configured to control the first power switch or the second power switch to be turned on to balance the voltage at the second end of the first capacitor when a voltage difference between the voltage of the first capacitor and the voltage of the second capacitor exceeds a first threshold.
5. The balancing circuit applied to the T-type three-level inverter according to claim 3, wherein the control circuit is configured to control the second power switch to be turned on when the voltage of the second capacitor exceeds a second threshold.
6. The balancing circuit applied to the T-type three-level inverter according to claim 3, wherein the control circuit controls the first power switch to be turned on when the voltage of the first capacitor exceeds a third threshold value.
7. The balancing circuit applied to the T-type three-level inverter according to claim 3, wherein the control circuit is configured to control the first power switch or the second power switch to be turned on, so that the balancing inductor operates in a discontinuous mode.
8. The balance circuit applied to the T-type three-level inverter according to claim 3, wherein when the voltage of the first capacitor is greater than the voltage of the second capacitor, the duty ratio of the first control signal is less than Vc 2/(Vc 1+ Vc 2), where Vc1 is the voltage of the first capacitor and Vc2 is the voltage of the second capacitor.
9. The balance circuit applied to the T-type three-level inverter according to claim 3, wherein when the voltage of the second capacitor is greater than the voltage of the first capacitor, the duty ratio of the second control signal is less than Vc 1/(Vc 1+ Vc 2), where Vc1 is the voltage of the first capacitor and Vc2 is the voltage of the second capacitor.
10. The balance circuit applied to the T-type three-level inverter according to claim 8, wherein a peak current value of the balance inductor is (Vc 1/L) × Ton, where L is an inductance value of the balance inductor and Ton is a time period when the first control signal is at a high level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222635306.7U CN218162234U (en) | 2022-10-08 | 2022-10-08 | Balance circuit applied to T-type three-level inverter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222635306.7U CN218162234U (en) | 2022-10-08 | 2022-10-08 | Balance circuit applied to T-type three-level inverter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN218162234U true CN218162234U (en) | 2022-12-27 |
Family
ID=84566717
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202222635306.7U Active CN218162234U (en) | 2022-10-08 | 2022-10-08 | Balance circuit applied to T-type three-level inverter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN218162234U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116961454A (en) * | 2023-09-18 | 2023-10-27 | 深圳市首航新能源股份有限公司 | Bus midpoint balance circuit, inverter and energy storage system |
-
2022
- 2022-10-08 CN CN202222635306.7U patent/CN218162234U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116961454A (en) * | 2023-09-18 | 2023-10-27 | 深圳市首航新能源股份有限公司 | Bus midpoint balance circuit, inverter and energy storage system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109842287B (en) | PFC circuit compatible with single-phase and three-phase alternating-current input and control method thereof | |
| US11418114B2 (en) | Boost power conversion circuit, method, inverter, apparatus, and system | |
| AU2009230285B2 (en) | Power conversion device | |
| CN102187562B (en) | Power converter | |
| CN105763078A (en) | Switch power source and bus capacitor voltage control method used for switch power source | |
| CN108173299A (en) | Wireless receiving device and use its wireless power transmission device and rectifier | |
| CN218162234U (en) | Balance circuit applied to T-type three-level inverter | |
| WO2020068022A2 (en) | A single phase inverter for photovoltaic panels | |
| CN110768551B (en) | AC-DC and DC-DC conversion multiplexing line and method | |
| US20230253877A1 (en) | Power factor correction and dc-dc multiplexing converter and uninterruptible power supply including the same | |
| Lo et al. | Elimination of the output voltage imbalance in a half-bridge boost rectifier | |
| GB2337643A (en) | Power converter | |
| CN109217704B (en) | Non-isolated five-level inverter for suppressing system leakage current | |
| CN107482892B (en) | Energy buffer circuit and converter | |
| CN113193768B (en) | Four-switch-tube series-type back-to-back three-level rectifier | |
| CN112865563B (en) | Three-port clamping type back-to-back bridgeless three-level rectifier | |
| CN116260351A (en) | AC-DC conversion circuit compatible with single-phase and three-phase alternating current | |
| CN210350838U (en) | Vehicle-mounted charging and discharging system | |
| CN113258797A (en) | Back-to-back type three-level rectifier of heterogeneous switching tube bridge arm | |
| CN216346935U (en) | Frequency conversion controller of intelligent air conditioner | |
| CN112104221B (en) | Power factor correction circuit and control device and control method thereof | |
| CN217508615U (en) | Power supply circuit, air condensing units and air conditioner | |
| CN113271023B (en) | Back-to-back type three-level rectifier of heterogeneous hybrid bridge arm | |
| CN211151845U (en) | Split-phase inverter circuit | |
| US20230253879A1 (en) | Charger, a multiplexing current conversion circuit and an uninterruptible power supply including the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |