CN218123395U - Semiconductor device with a plurality of transistors - Google Patents
Semiconductor device with a plurality of transistors Download PDFInfo
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- CN218123395U CN218123395U CN202222475327.7U CN202222475327U CN218123395U CN 218123395 U CN218123395 U CN 218123395U CN 202222475327 U CN202222475327 U CN 202222475327U CN 218123395 U CN218123395 U CN 218123395U
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 61
- 229910000679 solder Inorganic materials 0.000 claims abstract description 35
- 238000004806 packaging method and process Methods 0.000 claims abstract description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 10
- 239000000463 material Substances 0.000 description 14
- 238000010586 diagram Methods 0.000 description 10
- 229920005989 resin Polymers 0.000 description 9
- 239000011347 resin Substances 0.000 description 9
- 238000005476 soldering Methods 0.000 description 8
- 238000007689 inspection Methods 0.000 description 6
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002759 woven fabric Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- 238000011049 filling Methods 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000000748 compression moulding Methods 0.000 description 2
- 238000001746 injection moulding Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N phenol group Chemical group C1(=CC=CC=C1)O ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 2
- 229920001296 polysiloxane Polymers 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 238000001721 transfer moulding Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000012790 confirmation Methods 0.000 description 1
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229920003986 novolac Polymers 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Images
Abstract
The embodiment of the application discloses a semiconductor device, includes: a package and a plurality of pins. The lead comprises a plurality of pins, the pins surround the packaging body and are connected with the packaging body, the pins are arranged at intervals, each pin is provided with at least one groove, the grooves are formed in one ends, far away from the packaging body, of the pins, the pins are used for being connected with a circuit board through solder, and the grooves are used for accommodating part of the solder. The semiconductor device is heated and reflowed in the process of being welded on the circuit board, and the solder contained in the groove is used for connecting the pin and the circuit board, so that the reliability of the connection between the pin and the circuit board is improved.
Description
Technical Field
The application belongs to the technical field of semiconductors, and particularly relates to a semiconductor device.
Background
More and more electronic functions must now be implemented in a given space. This results in an increasing density of devices on the circuit board. To solve the board level device density problem, the size of the electronic devices used must be reduced. At the same time, smaller packages need to dissipate the same amount of heat in a smaller footprint size, thereby increasing the on-board power density.
The Quad Flat Package (QFN) is a leadless Package, and a large-area exposed bonding pad is disposed at the center of the Quad Flat Package (QFN) and has a heat conduction function, and a conductive bonding pad for realizing electrical connection is disposed at the periphery of the large-area bonding pad. Generally, a heat conducting pad and a conductive pad are mounted on a Circuit Board (PCB), because the contact area between the quad flat package without leads and the Circuit Board is small, the reliability is weak, and the lead side of the quad flat package without leads has poor tin-climbing effect, the solder paste cannot climb up the metal area of the lead side, and the solder joint between the lead and the Circuit Board plays multiple roles of electrical, thermal, mechanical connection and the like. Specifically, in the vehicle-mounted application, the flat package without leads on four sides may cause solder joint peeling due to random vibration of the vehicle, load impact, temperature impact, and the like, and thus the reliability of the connection between the flat package without leads on four sides and the circuit board cannot be ensured.
Disclosure of Invention
The semiconductor device provided by the embodiment of the application can improve the connection strength between the semiconductor device and the circuit board.
An embodiment of an aspect of the present application provides a semiconductor device, including:
a package body;
the lead comprises a plurality of pins, the pins surround the packaging body and are connected with the packaging body, the pins are arranged at intervals, each pin is provided with at least one groove, the grooves are formed in one ends, far away from the packaging body, of the pins, the pins are used for being connected with a circuit board through solder, and the grooves are used for accommodating part of the solder.
According to any of the embodiments of the present application, the lead has at least one groove, the groove is disposed at an end of the lead away from the package body, and the solder is contained in the groove.
According to any one of the foregoing embodiments of the present application, the pin includes an end surface away from the package body, the end surface and the package body are disposed at an interval, and the end surface is recessed toward a direction close to the package body to form a groove.
According to any one of the previous embodiments of the present application, the pin further includes a side surface, the side surface connects the package body and the end surface, and the groove is located at a connection position between the end surface and the package body.
According to any of the previous embodiments of the present application, the recess extends in a thickness direction of the package body.
According to any of the previous embodiments of the present application, the maximum length from the end face to the package body is L1; the maximum length R1 from the groove surface to the plane of the end face of the groove, and the maximum length R2,1/2L1 from the groove surface to the plane of the side face connected to the groove surface of the groove are constructed from R1(s) to 3/4L1,1/2L1(s) to R2(s) to 3/4L 1(s).
According to any of the embodiments described above, lengths L2,1/3L2 of the pieces of yarn-woven fabric r 1-2L2,1/3L 2-yarn-woven fabric r 1/2L2 between both side surfaces perpendicular to the thickness direction of the package body are made of the same material.
According to any of the previous embodiments of the present application, one pin includes two grooves, and the two grooves are respectively disposed on two opposite sides of the end surface.
According to any of the previous embodiments of the present application, the groove surface of the groove is curved.
According to any one of the previous embodiments of the application, the package body comprises a first surface and a heat conducting pad arranged on the first surface, and the first surface and at least one second surface of the pin are in the same plane.
According to any of the previous embodiments of the present application, the pin is copper.
The semiconductor device provided by the embodiment of the application comprises: a package and a plurality of pins. The lead comprises a plurality of pins, the pins surround the packaging body and are connected with the packaging body, the pins are arranged at intervals, each pin is provided with at least one groove, the grooves are formed in one ends, far away from the packaging body, of the pins, the pins are used for being connected with a circuit board through solder, and the grooves are used for accommodating part of the solder. The semiconductor device is heated and reflowed in the process of being welded on the circuit board, and the solder contained in the groove is used for connecting the pin and the circuit board, so that the reliability of the connection between the pin and the circuit board is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application;
fig. 2 is a schematic structural diagram of another semiconductor device provided in an embodiment of the present application;
fig. 3 is a schematic structural diagram of a pin according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of another pin according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of another pin according to an embodiment of the present disclosure.
Description of the reference numerals:
100. a semiconductor device;
1. a package body;
2. a pin; 21. a groove; 22. an end face; 23. a side surface;
x, a first direction; y, a second direction; z, third direction.
Detailed Description
Features and exemplary embodiments of various aspects of the present application will be described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof. In the drawings and the following description, at least some well-known structures and techniques have not been shown in detail in order to avoid unnecessarily obscuring the present application; also, the dimensions of some of the structures may be exaggerated for clarity. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
In the description of the present application, it is to be noted that, unless otherwise specified, "a plurality" means two or more; the terms "upper," "lower," "left," "right," "inner," "outer," and the like, indicate an orientation or positional relationship that is merely for convenience in describing the application and to simplify the description, and do not indicate or imply that the referenced components or elements must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the application. Furthermore, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
The directional terms used in the following description are intended to refer to directions shown in the drawings, and are not intended to limit the specific structure of embodiments of the present application. In the description of the present application, it is also to be noted that, unless otherwise explicitly specified or limited, the terms "mounted" and "connected" are to be interpreted broadly, e.g., as being either fixedly connected, detachably connected, or integrally connected; can be directly connected or indirectly connected. The specific meaning of the above terms in the present application can be understood as appropriate by one of ordinary skill in the art.
Referring to fig. 1 to fig. 3, fig. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present disclosure; fig. 2 is a schematic structural diagram of another semiconductor device provided in an embodiment of the present application;
fig. 3 is a schematic structural diagram of a pin according to an embodiment of the present application. In an embodiment of an aspect of the present application, a semiconductor device 100 is provided, and a singulation process needs to be performed on the semiconductor device 100 in a metal lead frame, where the singulation process is to die cut or cut individual devices from an arrangement of the metal lead frame, and the individual semiconductor devices 100 are obtained after being cut along a dotted line in fig. 1, so that the individual semiconductor devices 100 can be used for being soldered on a circuit board.
The semiconductor device 100 includes a package 1 and a plurality of leads 2. The plurality of pins 2 surround the package body 1 and are connected with the package body 1, the plurality of pins 2 are arranged at intervals, the pins 2 are provided with at least one groove 21, the groove 21 is arranged at one end of each pin 2 far away from the package body 1, the pins 2 are used for being connected with a circuit board through solder, and the grooves 21 are used for accommodating part of the solder.
In the semiconductor device 100 provided by the present application, the recess 21 is disposed at an end of the lead 2 away from the package 1, so as to improve the connection convenience between the solder and the circuit board. Alternatively, the grooves 21 may be punched out by punching or cutting the pins 2 with a punching cutter. The grooves 21 can also be formed by etching with copper chloride, ferric chloride or other chemical etching solutions.
The semiconductor device 100 may be soldered on a circuit board by means of a chip, specifically, the plurality of pins 2 are placed on the circuit board, and optionally, the semiconductor device 100 may further include solder disposed in the groove 21. Because the solder is connected with at least one end of the pin 2 far away from the packaging body 1, after the heating reflux, the solder on the pin 2 can be directly heated and refluxed to be connected with the circuit board, so that the reliability of the connection of the pin 2 and the circuit board is improved, and meanwhile, the processing procedure of taking the solder again can be saved. After the semiconductor device 100 is attached to the circuit board, an inspector may inspect the soldering condition in an inspection direction by Automatic Optical Inspection (AOI). Specifically, the inspection direction may be a direction from the upper surface to the lower surface of the semiconductor device 100, i.e., a thickness direction of the semiconductor device 100, and the inspector may directly perform the inspection at a plan view angle. By performing automatic optical inspection at the angle of the top view, the efficiency of the inspection can be improved.
Optionally, the package 1 may be a cube or a rectangular parallelepiped, and the thickness of the package 1 may be selected according to the size of the circuit board, which is not limited to the above conditions. The extending lengths of the plurality of leads 2 may be the same, so that the soldering areas of the plurality of leads 2 connected to the package body 1 have consistency, so that the difference of the soldering degree is not easily generated when the semiconductor device 100 is soldered on the circuit board, and the semiconductor device 100 can be more stably disposed on the circuit board.
It is understood that the leads 2 may be disposed at only one end of the package body 1, or the leads 2 may be disposed at two ends of the package body 1 or disposed around the package body 1 according to actual requirements. This is not limited in this application.
The solder is mostly tin, and the tin metal has low material cost, strong heat resistance, good conductivity and strong bonding capability.
Referring to fig. 4 and 5 in combination, fig. 4 is a schematic structural diagram of another lead provided in the embodiment of the present application; fig. 5 is a schematic structural diagram of another pin according to an embodiment of the present disclosure. In some alternative embodiments, the lead 2 includes an end surface 22 far away from the package body 1, the end surface 22 is spaced apart from the package body 1, and the end surface 22 is recessed toward the package body 1 to form the groove 21.
In these alternative embodiments, the solder is accommodated in the groove 21, and the end surface 22 is recessed toward the direction close to the package body 1 to form the groove 21, so that the solder can improve the connection strength between the end surface 22 of the lead 2 and the circuit board.
In some alternative embodiments, pin 2 further includes a side 23, where side 23 connects package 1 and end 22, and recess 21 is located at the connection between end 22 and package 1. The solder contained in the groove 21 connects the side surface 23 and the end surface 22, so that the welding area of the solder and the lead can be increased. When the lead 2 is soldered to the circuit board only through the side surface 23 or the end surface 22, accordingly, the solder can be connected to the end surface 22 or the side surface 23, so that the soldering stability can be improved, and the possibility that the semiconductor device 100 is peeled off by vibration can be reduced. In some alternative embodiments, the groove 21 extends in the thickness direction of the package body 1.
In these alternative embodiments, the thickness direction of the package 1 may be the first direction X, the solder is accommodated in the groove 21 through the high-temperature reflow sintering process, the solder may climb up the pin 2 from the pad of the circuit board by using the groove 21 extending along the first direction X, and the solder can be observed from the side 23 of the semiconductor device 100, so as to facilitate confirmation of the soldering condition between the semiconductor device 100 and the circuit board, and further improve the reliability and the solderability of the semiconductor device 100.
In some alternative embodiments, the maximum length of the end face 22 to the package body 1 is L1; the maximum length R1 from the groove surface of the groove 21 to the plane of the end face 22, and the maximum lengths R2,1/2l 1-R3/4L1,1/2l 1-R2-R1 from the groove surface of the groove 21 to the plane of the side face 23 connected to the groove surface of the groove 21.
In these alternative embodiments, the maximum length from the end face 22 to the package body 1 is L1, the length of the lead 2 extending in the direction away from the package body 1 may be the second direction Y, the length of the lead 2 extending in the second direction Y is L1, the maximum length from the groove surface of the groove 21 to the end face 22 in the second direction Y is R1, and the maximum length from the groove surface of the groove 21 to the side face 23 in the third direction Z is R2. R1 may be equal to R2. If R1 is greater than 3/4L1, the conductivity of the lead 2 is affected, and if R1 is less than 1/2L1, the contact area of the solder and the lead 2 is reduced, thereby reducing the connection strength of the semiconductor device 100 and the circuit board.
In some alternative embodiments, lengths L2,1/3L2 of the two side surfaces 23 perpendicular to the thickness direction of the package body 1 are formed as (r 1) s 1/2L2,1/3L2 s 1/2L2 s.
In these alternative embodiments, the lead 2 may be a square body, the lead 2 includes four side surfaces 23 connected to the package 1, two side surfaces 23 are oppositely disposed along the thickness direction of the package 1, that is, two side surfaces 23 are oppositely disposed along the first direction X, and the other two side surfaces 23 are oppositely disposed along the direction perpendicular to the first direction X, and since one end of the lead 2 is connected to the package 1, the other two side surfaces 23 are oppositely disposed along the third direction Z in the figure. The longest distance that one pin 2 extends in the third direction Z is L2.1/3L2 yarn-woven fabric R1/2L2,1/3 L2 yarn-woven fabric R2 yarn-woven fabric 1/2L2 can avoid the phenomenon of connection between two adjacent pins 2, so that the phenomenon of poor short circuit of the semiconductor device 100 can be effectively prevented.
In some alternative embodiments, one pin 2 includes two grooves 21, the two grooves 21 being disposed on opposite sides of the end surface 22. The two grooves 21 respectively arranged on the opposite sides of the pin 2 can be used for combining the solder and the pin 2, so that the connection strength of the pin 2 and the circuit board is improved, and the possibility of peeling the semiconductor device 100 and the circuit board caused by water vapor, vibration and the like is reduced.
In some alternative embodiments, the groove surface of the groove 21 is curved.
In these alternative embodiments, the groove surface of the groove 21 is curved, so that air in the groove 21 can be discharged along the arc shape of the curved surface, and air bubbles remaining when solder is provided in the groove 21 can be reduced, thereby improving the soldering performance of the semiconductor device 100 and improving the reliability of soldering the semiconductor device 100 to a circuit board.
In some alternative embodiments, the package body 1 includes a first surface and a thermal pad disposed on the first surface, and the first surface and at least one second surface of the pin 2 are in the same plane.
In these alternative embodiments, the thermal pad has a direct heat dissipation path for dissipating heat within the semiconductor device 100, typically directly connecting the first surface with the thermal pad to the circuit board. The second surface of the lead 2 can be a side surface 23 of the lead 2, and the first surface and the side surface 23 of the lead 2 are in the same plane, so that no height difference is formed between the package body 1 and the plane where the lead 2 is connected with the circuit board, which can improve the soldering reliability of the semiconductor device 100, save the solder material and reduce the cost of the solder.
In some alternative embodiments, pin 2 is copper. Copper metal has good conductivity.
It is understood that the semiconductor device 100 further includes a leadframe for carrying the semiconductor chip, a semiconductor chip, and a packaging material disposed on the leadframe and covering the semiconductor chip to form a package structure. The packaging structure can isolate external water vapor or oxygen and the like from entering the semiconductor chip, so that the service life and the stability of the semiconductor chip are improved.
In these alternative embodiments, the semiconductor device 100 may be a package structure using a totally enclosed (TO) package. Through the arrangement, the parasitic parameters of the semiconductor device 100 are smaller in the using process, and the manufacturing process of the semiconductor device 100 can be simplified.
The encapsulation material of the semiconductor device 100 may be a uniform single encapsulation material or a mixed encapsulation material, and the encapsulation material may beBut are not limited to: one or more of phenolic-based resin (Novolac-based resin), epoxy-based resin (epoxy-based resin), silicone-based resin (silicone-based resin), or other suitable encapsulating material. Alternatively, the encapsulating material may be a combination of a coating material and a filling material, wherein the coating material may be selected from, but not limited to: one or more of phenolic-based resins, epoxy-based resins, silicon-based resins, or other suitable encapsulating materials; the filling material is preferably low-cost, high-filling and excellent-insulation material, such as powdered silicon dioxide (SiO) 2 ). It is understood that the semiconductor package structure may be formed using a variety of packaging techniques, such as, but not limited to, compression molding (compression molding), injection molding (injection molding), transfer molding (transfer molding), or other suitable packaging techniques.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
In addition, the term "and/or" herein is only one kind of association relationship describing the association object, and means that there may be three kinds of relationships, for example, a and/or B, and may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
It should be understood that in the embodiment of the present application, "B corresponding to a" means that B is associated with a, from which B can be determined. It should also be understood that determining B from a does not mean determining B from a alone, but may be determined from a and/or other information.
While the invention has been described with reference to specific embodiments, the scope of the invention is not limited thereto, and those skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the invention, and these modifications or substitutions are intended to be included in the scope of the invention. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A semiconductor device, comprising:
a package body;
the plurality of pins surround the packaging body and are connected with the packaging body, the plurality of pins are arranged at intervals, each pin is provided with at least one groove, the grooves are formed in one end, far away from the packaging body, of each pin, the pins are used for being connected with a circuit board through solder, and the grooves are used for containing part of the solder.
2. The semiconductor device of claim 1, wherein the leads include end surfaces spaced apart from the package body, the end surfaces being recessed toward the package body to form the recess.
3. The semiconductor device of claim 2, wherein the leads further comprise side surfaces connecting the package body and the end surfaces, and wherein the recess is located at the connection of the end surfaces and the package body.
4. The semiconductor device according to claim 3, wherein the groove extends in a thickness direction of the package body.
5. The semiconductor device according to claim 4, wherein a maximum length of the end face to the package body is L1;
the maximum length R1 of the groove surface of the groove to the plane of the end face, the maximum length R2 of the groove surface of the groove to the plane of the side face connected to the groove surface of the groove, 1/2L1-R1-3/4L1,1/2L1-R2-4L 1.
6. The semiconductor device according to claim 5, wherein lengths L2,1/3 L2-t-R1-t 1/2L2,1/3 L2-t-R2-t 1/2L2 between both the side faces perpendicular to the thickness direction of the package body.
7. The semiconductor device of claim 3, wherein one of said leads includes two of said grooves, said two grooves being disposed on opposite sides of said end surface.
8. The semiconductor device according to claim 1, wherein a groove surface of the groove is a curved surface.
9. The semiconductor device of any one of claims 1-8, wherein the package body comprises a first surface and a thermally conductive pad disposed on the first surface, the first surface and the at least one second surface of the lead being in a same plane.
10. The semiconductor device according to any one of claims 1 to 8, wherein the pin is copper.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222475327.7U CN218123395U (en) | 2022-09-19 | 2022-09-19 | Semiconductor device with a plurality of transistors |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222475327.7U CN218123395U (en) | 2022-09-19 | 2022-09-19 | Semiconductor device with a plurality of transistors |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN218123395U true CN218123395U (en) | 2022-12-23 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202222475327.7U Active CN218123395U (en) | 2022-09-19 | 2022-09-19 | Semiconductor device with a plurality of transistors |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN218123395U (en) |
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- 2022-09-19 CN CN202222475327.7U patent/CN218123395U/en active Active
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| TR01 | Transfer of patent right |
Effective date of registration: 20231116 Address after: No. 6, Lane 1688, Jiugong Road, Jinshan Industrial Zone, Jinshan District, Shanghai, 201500 Patentee after: Ruineng Weien Semiconductor (Shanghai) Co.,Ltd. Address before: 330052 North first floor, building 16, No. 346, xiaolanzhong Avenue, Xiaolan Economic Development Zone, Nanchang County, Nanchang City, Jiangxi Province Patentee before: Ruineng Semiconductor Technology Co.,Ltd. |