CN218068276U

CN218068276U - Radar main lobe interference system

Info

Publication number: CN218068276U
Application number: CN202222028962.0U
Authority: CN
Inventors: 卢凯; 何云川; 何进; 李陶
Original assignee: Chengdu Ruixin Technology Co ltd
Current assignee: Chengdu Ruixin Technology Co ltd
Priority date: 2022-08-02
Filing date: 2022-08-02
Publication date: 2022-12-16
Anticipated expiration: 2032-08-02

Abstract

The utility model relates to a radar interference technical field, in particular to a radar main lobe interference system, which comprises a host and an accessory, wherein the host comprises a broadband radio frequency module, a digital processing module, a power supply module and a data transmission module, and the accessory comprises an antenna, a radio frequency cable and an external battery; the broadband radio frequency module, the digital processing module and the data transmission module are all electrically connected with the power module and are powered by a power supply; the broadband radio frequency module and the data transmission module are both connected to the antenna through radio frequency cables. The utility model discloses based on independent communication link and power supply system, need not outside platform power supply and data transmission, can arrange in various platforms fast conveniently, realize interfering system's quick adaptation and operation, it is poor to effectively solve among the prior art interfering system flexibility, operation and awkward problem.

Description

Radar main lobe interference system

Technical Field

The utility model relates to a radar jamming technique field particularly, relates to a radar mainlobe interference system.

Background

Radar is a detection system that uses radio waves to determine the range, angle or velocity of an object. It can be used to detect aircraft, ships, spacecraft, guided missiles, automobiles, weather formations, terrain. The radar system includes a transmitter, a transceiver antenna, a receiver, and a processor to determine object properties.

The radar countermeasure is the important content of the information war, and has great significance for capturing the information war by effectively interfering the radar. According to the characteristics of the radar in the working process, interference signals are generated and enter a radar receiver, and detection target information and measurement target information of the radar receiver are damaged.

The existing radar main lobe interference system is required to depend on a platform, is not easy to be deployed on different platforms during deployment, limits the operation and use of the radar main lobe interference system, and is poor in flexibility.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a radar mainlobe interference system, it includes host computer and annex, the host computer includes broadband radio frequency module, digital processing module, power module and data transmission module, the annex includes antenna, radio frequency cable and external battery, based on independent communication link and power supply system, need not outside platform power supply and data transmission, can arrange in various platforms fast conveniently, realizes interference system's quick adaptation and operation, can effectively solve among the prior art interference system flexibility poor, operation and awkward problem.

The embodiment of the utility model discloses a realize through following technical scheme: a radar main lobe interference system comprises a host and accessories, wherein the host comprises a broadband radio frequency module, a digital processing module, a power supply module and a data transmission module, and the accessories comprise an antenna, a radio frequency cable and an external battery;

the broadband radio frequency module, the digital processing module and the data transmission module are all electrically connected with the power supply module and are powered by a power supply;

the broadband radio frequency module and the data transmission module are both connected to the antenna through radio frequency cables.

According to a preferred embodiment, the broadband radio frequency module, the digital processing module and the data transmission module are all connected with the power supply module through a VPX motherboard.

According to a preferred embodiment, the digital processing module is composed of a baseband processing module and an interface control module.

According to a preferred embodiment, the baseband processing module and the broadband radio frequency module are connected by a radio frequency cable.

According to a preferred embodiment, the interface control module comprises a central processing unit, a first FPGA and a network interface;

the first FPGA is connected with the central processing unit, the central processing unit and the first FPGA are both connected with a memory, and the network interface is connected to the first FPGA through a VPX motherboard.

According to a preferred embodiment, the wideband radio frequency module comprises a wideband up-converter, a wideband down-converter and a power amplifier.

According to a preferred embodiment, the baseband processing module comprises a high-speed ADC chip, a second FPGA and a high-speed DAC chip, and both the high-speed ADC chip and the high-speed DAC chip are connected to the second FPGA.

According to a preferred embodiment, the baseband processing module further includes a clock CLK, and the high-speed ADC chip, the high-speed DAC chip, and the second FPGA are all connected to the clock CLK.

According to a preferred embodiment, the baseband processing module further includes a memory DDR, and the memory DDR is connected to the second FPGA.

According to a preferred embodiment, the wideband down converter is connected to a signal input end of the high-speed ADC chip, and the wideband up converter and the power amplifier are both connected to a signal output end of the high-speed DAC chip.

The utility model discloses technical scheme has following advantage and beneficial effect at least: the utility model provides a radar main lobe interference system based on independent communication link and power supply system, need not outside platform power supply and data transmission, can arrange in various platforms fast conveniently, realizes interference system's quick adaptation and operation, can effectively solve among the prior art interference system flexibility poor, operation and awkward problem.

Drawings

Fig. 1 is a schematic diagram of a main lobe jamming system provided in embodiment 1 of the present invention;

fig. 2 is a system host architecture diagram provided in embodiment 1 of the present invention;

fig. 3 is a system signal processing flow chart provided by embodiment 1 of the present invention;

fig. 4 is a schematic diagram of a baseband processing module provided in embodiment 1 of the present invention;

fig. 5 is a schematic composition diagram of an interface control module provided in embodiment 1 of the present invention;

fig. 6 is a schematic structural diagram of a system provided in embodiment 1 of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention, as generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations.

Example 1

Referring to fig. 1, fig. 1 is a schematic diagram of a main lobe jamming system according to an embodiment of the present invention.

The embodiment of the utility model provides a radar mainlobe interference system can produce simulation echo and interfering signal simultaneously or timesharing, realizes radar mainlobe interference function to and radar echo simulation function.

Specifically, the embodiment of the present invention provides a radar main lobe interference system, which comprises a host and an accessory, wherein the host comprises a broadband radio frequency module, a digital processing module, a power module and a data transmission module, and the accessory comprises an antenna, a radio frequency cable and an external battery; the broadband radio frequency module, the digital processing module and the data transmission module are all electrically connected with the power supply module and are powered by a power supply; the broadband radio frequency module and the data transmission module are both connected to the antenna through radio frequency cables. In an implementation manner of this embodiment, the functional modules of the radar main lobe jamming system are designed to be integrated according to the standard of a 3u_vpx module. The standardized design of the module and the chassis mechanism part enables the host to realize high integration level, low power consumption, high reliability and convenience in maintenance.

Referring to fig. 2, specifically, the broadband radio frequency module, the digital processing module, and the data transmission module are all connected to the power supply module through a VPX motherboard, and data interaction, signal transmission, and power distribution are performed through the VPX motherboard.

The digital processing module is composed of a baseband processing module and an interface control module, wherein, referring to fig. 5, the interface control module includes a central processing unit, a first FPGA and a network interface; the first FPGA is connected with the central processing unit, the central processing unit and the first FPGA are both connected with a memory, and the network interface is connected to the first FPGA through a VPX motherboard.

Based on the structure, the main machine of the main board interference system is light and compact, the size of the main machine is only 200mm 130mm 143mm (no handle, joint and other parts are included), and the weight can be controlled within 6 kg. Furthermore, the host of the system adopts the design of an open type back board and a functional module, and hardware and software upgrading can be carried out on part of the modules according to actual application requirements at a later stage so as to improve and expand the system functions, for example, echo simulation or interference can be carried out on radar targets at a longer distance by improving the receiving sensitivity and the transmitting power of a broadband radio frequency module; or combining practical environment application experience, loading a radar database on the system, updating an echo simulation or interference algorithm, and adopting the most effective interference strategy to improve the overall efficiency of the system.

It should be noted that, in this embodiment, the interface control module not only comprehensively manages and controls the working timing sequence, working parameters, and the like of the system, but also stores and reads radar data information intercepted and received by the system, and a database for a specific radar signal environment can be formed by performing statistics and comprehensive analysis on the activity rule of a target.

Referring to fig. 3 and 4, the baseband processing module includes a high-speed ADC chip, a second FPGA, and a high-speed DAC chip, and the high-speed ADC chip and the high-speed DAC chip are both connected to the second FPGA. It should be noted that, in an implementation manner of this embodiment, the baseband processing module employs a digital radio frequency storage DRFM technology, and can process an intermediate frequency signal with an instantaneous bandwidth of 1GHz in real time, and the processing method does not depend on a signal intra-pulse modulation manner, so that the system can adapt to pulse radars such as conventional pulse, pulse doppler, chirp, phase coding, frequency agility, repetition jitter, and staggered repetition frequency, which are mainstream at present. And because the system adopts independent receiving and transmitting channels and antenna design, the system can simultaneously receive and transmit radio frequency signals, so the system is also suitable for continuous wave system radars.

The baseband processing module further comprises a clock CLK, and the high-speed ADC chip, the high-speed DAC chip and the second FPGA are all connected with the clock CLK; the baseband processing module further comprises a memory DDR, the memory DDR is connected with the second FPGA, and it should be noted that the first FPGA and the second FPGA are both large-scale FPGAs.

Further, the baseband processing module is connected with the broadband radio frequency module through a radio frequency cable. In an implementation manner of this embodiment, after the baseband processing module finishes collecting, storing, and processing a 1300MHz to 2300MHz intermediate frequency signal, the baseband processing module sends data to the high-speed DAC chip to generate a 1300MHz to 2300MHz intermediate frequency signal to the broadband radio frequency module.

In the baseband processing module provided by the embodiment, a high-capacity high-speed memory is used for completing DRFM, then various high-efficiency echo simulation and interference algorithm operations are performed on stored data, finally, echoes and interference are synthesized in a digital domain, and the data are sent to a high-speed DAC chip.

The broadband radio frequency module adopts a broadband design, can completely cover radio frequency transceiving processing of C and X waveband signals, and comprises a broadband up-converter, a broadband down-converter and a power amplifier. The broadband down converter is connected with the signal input end of the high-speed ADC chip, and the broadband up converter and the power amplifier are both connected with the signal output end of the high-speed DAC chip.

Based on the independent communication link and the power supply system provided by the above, external platform power supply and data transmission are not needed, and the system can be quickly and conveniently deployed on various platforms, such as small and medium-sized unmanned aerial vehicles, helicopters, fixed wing airplanes, vehicles, ships and warships and other moving platforms, or fixedly placed in high buildings, towers, mountain tops and other places for use, so that quick adaptation and operation of an interference system are realized.

It should be noted that, the radar interference system calculates the characteristic parameters of the airspace radar signals in real time by rapidly detecting the radar scanning signals of the airspace, and further processes the data by the system to obtain the radar beam main board discrimination threshold, so that the main lobe and the auxiliary lobe of the radar can be correctly and autonomously identified. With respect to the radar echo simulation function, when target echoes or interferences are generated, main board interferences and echo patterns close to real targets can be generated at a short distance relative to the radar by setting the system to only respond to radar main lobe irradiation and not to radar side lobe irradiation.

Specifically, referring to fig. 6, the broadband upconverter includes an amplitude limiter, a low noise amplifier, a first digital controlled attenuator, and a first intermediate frequency matched filter, which are connected in sequence; and the signal input end of the amplitude limiter is connected with a 2-12GHz receiving antenna, and the signal output end of the first intermediate frequency matching filter is connected with the high-speed ADC chip. The broadband down converter and the power amplifier comprise a 30dbm power amplifier, a second numerical control attenuator and a second intermediate frequency matched filter which are sequentially connected, the signal output end of the power amplifier is connected with a 2-12GHz transmitting antenna, and the signal input end of the power amplifier is connected with the high-speed DAC. The broadband radio frequency module further comprises a frequency synthesizer and a power divider, the frequency synthesizer is connected with the power divider, and a signal output end of the power divider is connected between the first numerical control attenuator and the first intermediate frequency matched filter and between the second intermediate frequency matched filter and the high-speed DAC chip.

The interface control module further comprises a power supply control module and a clock CLK, and the power supply control module is connected with the first FPGA. The baseband processing module further comprises a memory, and the memory is connected with the second FPGA.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A radar main lobe interference system is characterized by comprising a host and an accessory, wherein the host comprises a broadband radio frequency module, a digital processing module, a power supply module and a data transmission module, and the accessory comprises an antenna, a radio frequency cable and an external battery;

2. The radar mainlobe jamming system of claim 1, wherein the wideband radio frequency module, the digital processing module, and the data transmission module are connected to the power supply module through a VPX motherboard.

3. The radar mainlobe jamming system of claim 1, wherein the digital processing module is comprised of a baseband processing module and an interface control module.

4. The radar mainlobe jamming system of claim 3, wherein the baseband processing module and the wideband radio frequency module are connected by a radio frequency cable.

5. The radar mainlobe jamming system of claim 3, wherein the interface control module includes a central processing unit, a first FPGA, and a network interface;

6. The radar mainlobe jamming system of claim 3, wherein the wideband radio frequency module includes a wideband up-converter, a wideband down-converter, and a power amplifier.

7. The radar mainlobe jamming system of claim 6, wherein the baseband processing module includes a high-speed ADC chip, a second FPGA, and a high-speed DAC chip, the high-speed ADC chip and the high-speed DAC chip both connected to the second FPGA.

8. The radar mainlobe jamming system of claim 7, wherein the baseband processing module further includes a clock CLK, the high-speed ADC chip, the high-speed DAC chip, and the second FPGA all coupled to the clock CLK.

9. The radar mainlobe jamming system of claim 7, wherein the baseband processing module further comprises a memory DDR, the memory DDR being connected to a second FPGA.

10. The radar mainlobe jamming system of any one of claims 7 to 9, wherein the wideband down-converter is connected to a signal input of a high-speed ADC chip, and the wideband up-converter and the power amplifier are both connected to a signal output of a high-speed DAC chip.