CN218068218U - Chip interface connection test circuit - Google Patents
Chip interface connection test circuit Download PDFInfo
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- CN218068218U CN218068218U CN202222117100.5U CN202222117100U CN218068218U CN 218068218 U CN218068218 U CN 218068218U CN 202222117100 U CN202222117100 U CN 202222117100U CN 218068218 U CN218068218 U CN 218068218U
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Abstract
The application provides a chip interface connection test circuit, which comprises a control module, a switch module and a gating module, wherein the switch module is connected between a voltage output interface of the control module and a power interface of a chip, a grounding interface of the chip and a plurality of interfaces to be tested and is used for switching on or off the connection between the voltage output interface of the control module and the power interface of the chip, the grounding interface of the chip and the plurality of interfaces to be tested under the control of the control module so as to control the voltage provided for the power interface of the chip, the grounding interface of the chip and the plurality of interfaces to be tested; the gating module is connected between the voltage acquisition end of the control module and the plurality of interfaces to be tested and is used for communicating the connection between at least one interface to be tested in the plurality of interfaces to be tested and the voltage acquisition end of the control module under the control of the control module; the control module is used for detecting the interface connection conditions of the plurality of interfaces to be detected according to the voltage collected by the voltage collecting end. The technical scheme can save the number of interfaces of the control module.
Description
Technical Field
The application relates to the field of circuits, in particular to a chip interface connection testing circuit.
Background
In order to ensure that the chip device can be normally used, before the chip device is put into use, an Open-Short Test (Open-Short Test), which may also be referred to as a connectivity Test or a connection Test, is generally performed on the chip to confirm that all signal pins of the chip are electrically connected to corresponding channels of the Test system and no signal pin is shorted to other signal pins, a power supply or ground.
When a connection test is performed on a chip device, it is common to test the diode effect of a General-purpose input/output (GPIO) interface of the chip device on a power supply and a ground. Generally, 2 GPIO interfaces of a Micro Control Unit (MCU) are respectively connected to a power interface of a chip device and a GPIO interface of the chip to detect a diode effect of the GPIO interface of the chip on a power supply, and 2 GPIO interfaces of the MCU are respectively connected to a ground interface of the chip device and the GPIO interface of the chip to detect a diode effect of the GPIO interface of the chip on ground. When the GPIO ports of the chip are more, the MCU is required to have more GPIO ports than the chip to complete the connection test of the chip.
SUMMERY OF THE UTILITY MODEL
The application provides chip interface connection test circuit to accomplish the many technical problem of MCU's the GPIO interface that the connection test of chip needs when the GPIO mouth of solving the chip is more.
The application provides a chip interface connection test circuit, its characterized in that, chip interface connection test circuit includes control module, switch module and gating module, wherein:
the switch module is respectively connected with the control module, a preset power supply, a power supply interface of the chip and a grounding interface of the chip, and the voltage acquisition ends of the switch module and the control module are connected with a plurality of interfaces to be tested of the chip through the gating module;
the switch module is used for switching on or off the connection between the preset power supply and the power supply interface of the chip, the grounding interface of the chip and the plurality of interfaces to be tested under the control of the control module so as to control the chip interface to connect the voltage provided by the test circuit to the power supply interface of the chip, the grounding interface of the chip and the plurality of interfaces to be tested;
the gating module is used for communicating the connection between at least one interface to be tested in the plurality of interfaces to be tested and the voltage acquisition end of the control module under the control of the control module;
the control module is used for detecting the interface connection condition of the plurality of interfaces to be detected according to the voltage collected by the voltage collecting end.
In one possible design, the preset power supply includes a power supply terminal and a ground terminal; the switch module comprises a first on-off unit, a second on-off unit and a third on-off unit; wherein: the first end of the first on-off unit is connected with a power supply end of the preset power supply, the second end of the first on-off unit is connected with a grounding end of the preset power supply, the third end of the first on-off unit is connected with a power supply interface of the chip, the fourth end of the first on-off unit is connected with the control module, and the first on-off unit is used for controlling the voltage provided by the chip interface connection test circuit to the power supply interface of the chip under the control of the control module; the first end of the second on-off unit is connected with a power supply end of the preset power supply, the second end of the second on-off unit is connected with a grounding end of the preset power supply, the third end of the second on-off unit and a voltage acquisition end of the control module are connected with the plurality of interfaces to be tested through the gating module, the fourth end of the second on-off unit is connected with the control module, and the first on-off unit is used for controlling the voltage provided by the chip interface connection test circuit to the at least one interface to be tested under the control of the control module; the first end of the third breaking unit is connected with the power supply end of the preset power supply, the second end of the third breaking unit is connected with the grounding end of the preset power supply, the third end of the third breaking unit is connected with the grounding interface of the chip, the fourth end of the third breaking unit is connected with the control module, and the third breaking unit is used for controlling the voltage provided by the chip interface connection test circuit to the grounding interface of the chip under the control of the control module.
In one possible design, the chip interface connection test circuit further comprises a voltage dividing module; the third end of the second on-off unit is connected with the gating module and the voltage acquisition end of the control module through the voltage division module; the voltage division module is used for forming a voltage division circuit with the gating module.
In one possible design, the first switching unit includes a first resistor, a second resistor, a first transistor, and a second transistor; one end of the first resistor is connected with a first control end of the control module and a controlled end of the first transistor, the other end of the first resistor is connected with a power end of the preset power supply and a power connection end of the first transistor, and a controlled response end of the first transistor is connected with a power interface of the chip; one end of the second resistor is connected with the second control end of the control module and the controlled end of the second transistor, the other end of the second resistor is connected with the grounding end of the preset power supply and the power connection end of the second transistor, and the controlled response end of the second transistor is connected with the power interface of the chip.
In one possible design, the first transistor and the second transistor are both MOS transistors.
In one possible design, the second switching unit includes a third resistor, a fourth resistor, a third transistor, and a fourth transistor; one end of the third resistor is connected with a third control end of the control module and a controlled end of the third transistor, the other end of the third resistor is connected with a power supply end of the preset power supply and a power supply connecting end of the third transistor, and a controlled response end of the third transistor is connected with the gating module and a voltage acquisition end of the control module; one end of the fourth resistor is connected with a fourth control end of the control module and a controlled end of the fourth transistor, the other end of the fourth resistor is connected with a grounding end of the preset power supply and a power connection end of the fourth transistor, and a controlled response end of the fourth transistor is connected with the gating module and a voltage acquisition end of the control module.
In one possible design, the third turn-off unit includes a fifth resistor, a sixth resistor, a fifth transistor, and a sixth transistor; one end of the fifth resistor is connected with a fifth control end of the control module and a controlled end of the fifth transistor, the other end of the fifth resistor is connected with a power supply end of the preset power supply and a power connection end of the fifth transistor, and a controlled response end of the fifth transistor is connected with a ground interface of the chip; one end of the sixth resistor is connected to the sixth control end of the control module and the controlled end of the sixth transistor, the other end of the sixth resistor is connected to the ground end of the preset power supply and the power connection end of the sixth transistor, and the controlled response end of the sixth transistor is connected to the ground interface of the chip.
In one possible design, the gating module includes at least one multi-way analog switch, wherein: the common interface of each multi-path analog switch is connected with the voltage acquisition end of the control module and the gating module, the address interface and the control interface of each multi-path analog switch are connected with the gating interface of the control module, and one input/output interface of one multi-path analog switch is connected with one interface to be tested of the chip.
In one possible design, the multi-way analog switch is a digital gate CD4067.
In one possible design, the chip interface connection test circuit further includes a connector; the connector is used for connecting the gating module and the plurality of interfaces to be tested of the chip.
The application can realize the following technical effects: the application provides a chip interface connection test circuit, including control module, switch module and gating module, wherein: the switch module is respectively connected with the control module, a preset power supply, a power supply interface of the chip and a grounding interface of the chip, and the voltage acquisition ends of the switch module and the control module are connected with a plurality of interfaces to be tested of the chip through the gating module; the switch module is used for switching on or off the connection between the preset power supply and the power interface of the chip, the ground interface of the chip and the plurality of interfaces to be tested under the control of the control module so as to control the chip interface to connect the voltage provided by the test circuit to the power interface of the chip, the ground interface of the chip and the plurality of interfaces to be tested; the gating module is used for communicating the connection between at least one interface to be tested in the plurality of interfaces to be tested and the voltage acquisition end of the control module under the control of the control module; the control module is used for detecting the interface connection condition of the plurality of interfaces to be detected according to the voltage collected by the voltage collecting end. The gating module and the switch module are added between the control module and the chip interface, the control module can select the chip interface through the gating module and control the voltage of the chip interface through the switch module to finish the connection test of one chip interface, and further can finish the connection test of all chip interfaces through selecting the chip interfaces for multiple times; because the control module and the switch module are connected with the gating module and not directly connected with the interface of the chip, the connection test of the chip can be completed by fewer interfaces, and the number of the interfaces of the control module is saved.
Drawings
FIGS. 1 and 2 are schematic diagrams of one circuit connection scheme for chip connection testing;
fig. 3 is a block diagram of a chip interface connection testing circuit according to an embodiment of the present disclosure;
fig. 4 is a schematic connection diagram of a gating module according to an embodiment of the present disclosure;
fig. 5 is a block diagram of a switch module according to an embodiment of the present disclosure;
fig. 6 is a schematic circuit diagram of a switch module according to an embodiment of the present disclosure;
fig. 7 and 8 are schematic diagrams of a detection circuit provided in an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.
Referring first to fig. 1 and 2, fig. 1 and 2 are schematic diagrams of a circuit connection scheme for testing chip connections.
As shown in figure 1, when testing the diode effect of the GPIO interface of the chip to the power supply, the power PIN PIN1 and the GPIO interface PIN PIN3 of the chip are respectively connected with 2 GPIO interfaces of the MCU after being connected with resistors in series, then the MCU outputs 3.3V voltage through the GPIO interface J1 of the GPIO interface PIN PIN3 of the chip, and 0V voltage is output through a GPIO interface J2 connected with a power PIN PIN1 of the chip, then the voltages of the power PIN PIN1 and a GPIO interface PIN PIN3 of the chip are collected, and the voltage drop of a diode connected with a power supply in the chip is obtained through subtraction calculation.
As shown in fig. 2, when the diode effect of the GPIO interface of the test chip to the ground is tested, the ground PIN2 and the GPIO interface PIN3 of the chip are respectively connected to 2 GPIO interfaces of the MCU after being connected to resistors in series, then the MCU outputs 0V voltage through the GPIO interface J1 connected to the GPIO interface PIN3 of the chip, and outputs 3.3V voltage through the GPIO interface J3 connected to the ground PIN2 of the chip, and then collects the voltages at the ground PIN2 and the GPIO interface PIN3 of the chip, and the voltage drop of the diode connected to the ground is obtained by subtraction calculation.
As can be seen from fig. 1 and fig. 2, to complete the diode effect to the power and to the ground of one interface of the chip, at least 2 GPIO interfaces of the MCU are required. When the number of interfaces of the chip needing to be detected is large, the MCU is required to have more GPIO interfaces.
In view of this, the present application provides a chip interface connection test circuit, which can complete connection test of a chip with fewer MCU interfaces when there are more interfaces for detecting the chip. The technical scheme of the application can be suitable for connection testing of the chip device, and is particularly suitable for the chip device with a large number of GPIO interfaces. The chip is a general term for semiconductor device products, and may be referred to as an Integrated Circuit (IC), a microcircuit (microcircuit), and the like.
Referring to fig. 3, fig. 3 is a block diagram of a structure of a chip interface connection testing circuit provided in an embodiment of the present application, and as shown in fig. 3, a chip interface connection testing circuit 1 includes a control module 10, a switch module 20, and a gating module 30, where:
the switch module 20 is respectively connected with the control end of the control module 10, a preset power supply, a power supply interface of the chip and a ground interface of the chip, and the voltage acquisition ends of the switch module 20 and the control module 10 are connected with a plurality of interfaces to be tested of the chip through the gating module 30;
The gating module 30 is configured to communicate, under the control of the control module 10, connection between at least one to-be-tested interface of the plurality of to-be-tested interfaces and the voltage acquisition end of the control module 10. The gating module 30 is a circuit unit capable of implementing channel selection and on-off control according to a control instruction. The voltage acquisition end of the control module 10 refers to an acquisition interface for completing voltage acquisition in the control module. Specifically, the voltage collecting end of the control module may be an analog-digital collecting port. The gating module 30 is connected between at least one of the multiple interfaces to be tested of the chip and the voltage acquisition end of the control module 10 under the control of the control module 10, and can acquire voltages of different interfaces to be tested, so that the connection test of the interfaces to be tested is realized based on the voltage provided by the chip interface connection test circuit 1 to the power interface of the chip, the ground interface of the chip and the interfaces to be tested.
The control module 10 is configured to detect interface connection conditions of the plurality of interfaces to be tested according to the voltage collected by the voltage collection terminal. The control module 10 is a circuit unit for implementing various acquisition and control. Specifically, the control module 10 may be an MCU. The control module 10 may perform one-by-one detection on each interface to be detected by gating one interface to be detected each time, so as to detect the interface connection condition of the plurality of interfaces to be detected. The connection condition of the interface to be tested refers to the detection of the diode effect on the power supply and the diode effect on the ground of the interface to be tested.
In the technical scheme of fig. 3, a gating module and a switch module are added between the control module and the chip interface, and the control module selects the chip interface through the gating module and controls the voltage of the chip interface through the switch module to complete the connection test of one chip interface, so that the connection test of all chip interfaces can be completed through selecting the chip interfaces for multiple times; because the control module and the switch module are connected with the gating module and are not directly connected with the interfaces of the chip, the connection test of the chip can be completed by fewer interfaces, and the number of the interfaces of the control module is saved.
Some specific implementations of the above chip interface connection test circuit are described below.
In some possible designs, the gating module 10 includes at least one multi-channel analog switch, wherein a common interface of each multi-channel analog switch is connected to the voltage acquisition end of the control module and the gating module, an address interface and a control interface of each multi-channel analog switch are connected to the gating interface of the control module, and an input/output interface of one multi-channel analog switch is connected to an interface to be tested of the chip.
The gating interface of the control module is a GPIO interface for outputting a gating signal to the gating module. The control module can output gating signals to the address interface and the control interface of the multi-path analog switch through the gating interface to control the conduction of one channel in the multi-path analog switch, namely the common interface of the multi-path analog switch is connected with one input/output interface, so that the connection between the voltage acquisition end of the control module and one interface to be tested of the chip can be communicated.
In one possible design, the multi-way analog switch may be a digital gate CD4067. For example, referring to fig. 4, in the case that the multi-way analog switch is a CD4067 of a digital gate, a common interface (COM port) of the CD4067 of the digital gate is connected to the voltage acquisition terminal SAR _ AD of the control module, and an address interface (CTRA/CTRB/CTRC/CTRD) and a control Interface (INH) of the digital gate are connected to a gate interface of the control module, wherein one control interface of one CD4067 of the digital gate is connected to one gate interface of the control module. The input and output interfaces of each digital gate CD4067 are respectively connected with the interfaces to be tested of the chip, wherein the input and output interfaces are in one-to-one correspondence with the interfaces to be tested of the chip, that is, one input and output interface of one digital gate is connected with one interface to be tested of the chip.
The control module outputs different signals to the address interface and the control interface of the digital gate CD4067, so that channels between the common interface and different gate interfaces can be controlled and conducted, and the connection between the voltage acquisition end SAR _ AD of the control module and the interfaces to be tested of different chips is communicated.
Specifically, the truth table of the digital gate CD4067 is shown in table 1.
Optionally, the multi-way analog switch may also be a CD4051, a CD4052, or the like, which is not limited in this application.
Optionally, the chip interface connection test circuit may further include a connector; the connector is used for connecting the gating module and the plurality of interfaces to be tested of the chip.
The connector is used for establishing connection between each module (mainly a gating module) in the chip interface test circuit and the chip so as to realize connection test of the chip.
Specifically, the preset power supply includes a power supply terminal and a ground terminal, the voltage of the power supply terminal of the preset power supply may be 3.3V, and the voltage of the ground terminal of the preset power supply may be 0V.
In one possible design, as shown in fig. 5, the switch module 20 includes a first switching unit 201, a second switching unit 202, and a third switching unit 203; wherein:
a first end of the first on-off unit 201 is connected with a power supply end of the preset power supply, a second end of the first on-off unit 201 is connected with a grounding end of the preset power supply, a third end of the first on-off unit 201 is connected with a power supply interface of the chip, a fourth end of the first on-off unit 201 is connected with the control module, and the first on-off unit is used for controlling the voltage provided by the chip interface connection test circuit to the power supply interface of the chip under the control of the control module;
a first end of the second on-off unit 202 is connected to a power end of the preset power supply, a second end of the second on-off unit 202 is connected to a ground end of the preset power supply, a third end of the second on-off unit 202 and a voltage acquisition end of the control module 10 are connected to the plurality of interfaces to be tested through the gating module 30, a fourth end of the second on-off unit 202 is connected to the control module, and the first on-off unit 202 is configured to control the chip interface to connect to a voltage provided by the test circuit to the at least one interface to be tested under the control of the control module;
the first end of the third breaking unit 203 is connected with the power end of the preset power supply, the second end of the third breaking unit 203 is connected with the grounding end of the preset power supply, the third end of the third breaking unit is connected with the grounding interface of the chip, the fourth end of the third breaking unit 203 is connected with the control end of the control module 10, and the third breaking unit 203 is used for controlling the voltage provided by the chip interface connection test circuit to the grounding interface of the chip under the control of the control module.
Specifically, the first on-off unit 201 can provide a voltage of a ground terminal of a preset power supply to the power interface of the chip under the control of the control module 10, that is, 0V; the voltage of the power end of the preset power supply, that is, 3.3V, may also be provided to the power interface of the chip under the control of the control module 10. The second switching-off unit 202 may provide the voltage of the power end of the preset power to the interface to be tested of the chip under the control of the control module 10, that is, 0V, or may provide the voltage of the power end of the preset power to the interface to be tested of the chip under the control of the control module 10, that is, 3.3V. The third cut-off unit 203 can provide the voltage of the ground terminal of the preset power supply to the ground interface of the chip under the control of the control module 10, which is 0V; the voltage of the power end of the preset power supply can also be provided to the ground interface of the chip under the control of the control module 10, that is, 3.3V. When the first on-off unit 201 provides the voltage of the grounding terminal of the preset power supply to the power interface of the chip under the control of the control module 10, and the second on-off unit 202 provides the voltage of the power terminal of the preset power supply to the interface to be tested of the chip under the control of the control module 10, the diode effect of the interface to be tested on the power supply can be tested; when the third disconnection unit 203 provides the voltage of the power terminal of the preset power to the ground interface of the chip under the control of the control module 10, and the second disconnection unit 202 provides the voltage of the ground terminal of the preset power to the interface to be tested of the chip under the control of the control module, the diode effect to the ground of the interface to be tested can be tested.
The circuit compositions of the first on-off unit 201, the second on-off unit 202 and the third on-off unit 203 may be the same or different.
In one possible design, the first switching unit 201 includes a first resistor, a second resistor, a first transistor, and a second transistor; one end of the first resistor is connected with a first control end of the control module and a controlled end of the first transistor, the other end of the first resistor is connected with a power end of the preset power supply and a power connection end of the first transistor, and a controlled response end of the first transistor is connected with a power interface of the chip; one end of the second resistor is connected with the second control end of the control module and the controlled end of the second transistor, the other end of the second resistor is connected with the grounding end of the preset power supply and the power connection end of the second transistor, and the controlled response end of the second transistor is connected with the power interface of the chip.
In one possible design, the second switching unit 202 includes a third resistor, a fourth resistor, a third transistor, and a fourth transistor; one end of the third resistor is connected to a third control end of the control module and a controlled end of the third transistor, the other end of the third resistor is connected to a power source end of the preset power source and a power source connection end of the third transistor, and a controlled response end of the third transistor is connected to the gating module and a voltage acquisition end of the control module; one end of the fourth resistor is connected with a fourth control end of the control module and a controlled end of the fourth transistor, the other end of the fourth resistor is connected with a grounding end of the preset power supply and a power connection end of the fourth transistor, and a controlled response end of the fourth transistor is connected with the gating module and a voltage acquisition end of the control module.
In one possible design, the third cut-off unit 203 includes a fifth resistor, a sixth resistor, a fifth transistor, and a sixth transistor; one end of the fifth resistor is connected to a fifth control end of the control module and a controlled end of the fifth transistor, the other end of the fifth resistor is connected to a power end of the preset power supply and a power connection end of the fifth transistor, and a controlled response end of the fifth transistor is connected to the ground interface of the chip; one end of the sixth resistor is connected to the sixth control end of the control module and the controlled end of the sixth transistor, the other end of the sixth resistor is connected to the ground end of the preset power supply and the power connection end of the sixth transistor, and the controlled response end of the sixth transistor is connected to the ground interface of the chip.
The transistors (the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, or the sixth transistor) may be transistors, MOS transistors, or other electronic tubes capable of performing on-off control. When the transistor is a triode, the base electrode of the triode is the controlled end of the transistor, the collector electrode of the triode is the power supply connecting end of the transistor, and the emitter electrode of the triode is the controlled response end of the transistor; when the transistor is an MOS transistor, the grid electrode of the MOS transistor is the controlled end of the transistor, the source electrode of the MOS transistor is the power supply connecting end of the transistor, and the drain electrode of the MOS transistor is the controlled response end of the transistor.
For example, referring to fig. 6, the first transistor may be a PMOS transistor Q4, the second transistor may be an NMOS transistor Q3, a gate of the PMOS transistor Q4 is connected to the first control terminal PA4 of the control module and one end of the first resistor R6, a source of the PMOS transistor Q4 is connected to the other end of the first resistor R6 and a power end of the predetermined power supply, a drain of the PMOS transistor Q4 is connected to the drain of the NMOS transistor Q3 and the power interface of the chip, a gate of the NMOS transistor Q3 is connected to the second control terminal PA3 of the control module and one end of the second resistor R7, and a source of the NMOS transistor Q3 is connected to the other end of the second resistor R7 and a ground terminal of the predetermined power supply. When Q4 is switched on and Q3 is switched off, the TOP _ VDDIO voltage provided by the chip interface test circuit to the power interface of the chip is equal to the voltage of the power supply end of the preset power supply, namely 3.3V; when Q4 is turned off and Q3 is turned on, the voltage TOP _ VDDIO provided by the chip interface test circuit to the power interface of the chip is equal to the voltage of the ground terminal of the preset power supply, which is 0V.
Specifically, as shown in fig. 6, the third transistor may be a PMOS transistor Q6, the fourth transistor may be an NMOS transistor Q5, a gate of the PMOS transistor Q6 is connected to the third control end PA5 of the control module and one end of the third resistor R15, a source of the PMOS transistor Q6 is connected to the other end of the third resistor R15 and a power end of the preset power supply, a drain of the PMOS transistor Q6 is connected to the drain of the NMOS transistor Q5, the gating module 30, and the voltage collecting end of the control module 10, a gate of the NMOS transistor Q5 is connected to the fourth control end PA6 of the control module 10 and one end of the fourth resistor R16, and a source of the NMOS transistor Q5 is connected to the other end of the fourth resistor R16 and a ground end of the preset power supply. When Q6 is turned on and Q5 is turned off, the voltage AD _ OS _ POWER provided by the chip interface test circuit to the interface to be tested of the chip is equal to the voltage of the POWER end of the preset POWER supply, namely 3.3V; when Q6 is cut off and Q5 is conducted, the voltage AD _ OS _ POWER provided by the chip interface test circuit to the interface to be tested of the chip is equal to the voltage of the grounding end of the preset POWER supply, namely 0V.
Specifically, as shown in fig. 6, the fifth transistor may be a PMOS transistor Q29, the sixth transistor may be an NMOS transistor Q30, a gate of the PMOS transistor Q29 is connected to the fifth control terminal PA1 of the control module and one end of the fifth resistor R13, a source of the PMOS transistor Q29 is connected to the other end of the fifth resistor R13 and a power end of the predetermined power supply, a drain of the PMOS transistor Q29 is connected to the drain of the NMOS transistor Q30 and a ground interface of the chip, a gate of the NMOS transistor Q30 is connected to the sixth control terminal PA2 of the control module and one end of the sixth resistor R3, and a source of the NMOS transistor Q30 is connected to the other end of the sixth resistor R3 and a ground end of the predetermined power supply. When the Q29 is turned on and the Q30 is turned off, the TOP _ GND voltage provided by the chip interface test circuit to the ground interface of the chip is equal to the voltage of the power supply end of the preset power supply, namely 3.3V; when the Q29 is turned off and the Q30 is turned on, the voltage TOP _ GND provided by the chip interface test circuit to the ground interface of the chip is equal to the ground voltage of the preset power supply, i.e. 0V.
Optionally, as shown in fig. 5, the chip interface connection test circuit further includes a voltage dividing module 40; the third end of the second switching-off unit 203 is connected with the gating module 30 and the voltage acquisition end of the control module 10 through the voltage dividing module 40; the voltage dividing module 40 is used to form a voltage dividing circuit with the gating module 30.
The resistance value corresponding to the voltage dividing module 40 should be much larger than the resistance value corresponding to the gating module 10, which can be understood that, in a voltage dividing circuit formed by the voltage dividing module 40 and the gating module 20, the voltage obtained by voltage dividing by the gating module 30 is much smaller than the voltage obtained by voltage dividing by the voltage dividing module 40, that is, the voltage obtained by voltage dividing by the gating module 30 is negligible.
Specifically, as shown in fig. 6, the voltage dividing module 40 may be a voltage dividing resistor Ry in fig. 6.
The principle of the chip testing by the chip interface connection test circuit is described below by taking the gating module as the aforementioned digital gate CD4067 and the switch module as an example as shown in fig. 6.
Assume that the interface to be tested (hereinafter referred to as target interface to be tested) connected to the OS _ TP15 interface of the first digital gate CD4067 in fig. 6 is tested.
When the target interface to be tested is tested for the zener diode, the control module inputs a high level signal to each address interface of the first digital gate CD4067 according to the truth table of table 1, and controls the channel 15 of the first digital gate CD4067 to be conducted. The first control end PA4 and the second control end PA3 of the control module output high levels, Q4 is cut off, Q3 is conducted, and TOP _ VDDIO of the voltage provided by the chip interface test circuit to the power interface of the chip is the voltage of the grounding end of a preset power supply, namely 0V; a third control end PA5 and a fourth control end PA6 of the control module output low levels, Q6 is switched on and Q5 is switched off, and the voltage AD _ OS _ POWER provided by the chip interface test circuit to the interface to be tested of the chip is equal to the voltage of a POWER end of a preset POWER supply, namely 3.3V; the fifth control end PA1 of the control module outputs high level, the sixth control end PA2 of the control module outputs low level, and Q29 and Q30 are cut off. Thus, the circuit shown in fig. 7 is formed, and since the voltage drop of the on-resistance Rx of the CD4067 is much smaller than that of the voltage-dividing resistance Ry, the voltage acquired by the voltage acquisition end SAR _ AD of the control module is subtracted by TOP _ VDDIO, which is the tube voltage drop of the target to-be-detected interface to the antenna diode D1.
When the target interface to be tested is tested for the zener diode, the control module inputs a high level signal to each address interface of the first digital gate CD4067 according to the truth table of table 1, and controls the channel 15 of the first digital gate CD4067 to be conducted. A first control end PA4 of the control module outputs a high level, a second control end PA3 of the control module outputs a low level, and Q4 and Q3 are both cut off; a third control end PA5 and a fourth control end PA6 of the control module output high levels, Q5 is conducted, Q6 is cut off, and the voltage AD _ OS _ POWER provided by the chip interface test circuit to the interface to be tested of the chip is equal to the voltage of the grounding end of a preset POWER supply, namely 0V; the fifth control end PA1 and the sixth control end PA2 of the control module output low level, Q29 is turned on and Q30 is turned off, and the TOP _ GND voltage provided by the chip interface test circuit to the ground interface of the chip is equal to the voltage of the power supply end of the preset power supply, namely 3.3V. Thus, the current loop shown in fig. 8 is formed, and since the voltage drop of the on-resistance Rx of the CD4067 is much smaller than that of the voltage-dividing resistance Ry, the TOP _ GND minus the voltage collected by the voltage collecting end SAR _ AD of the control module is the tube voltage drop of the target interface to be measured to the ground diode D2.
It should be understood that the connection test of other interfaces under test of the chip is the same as the connection test of the target interface under test described above. Different level signals are input to the address interface of the digital gate CD4067 through the control module, and then different interfaces to be tested can be selected to carry out connectivity testing.
Because a digital gate CD4067 can be connected with 15 interfaces to be tested, for a chip with 100 interfaces to be tested, only 7 digital gate CD4067 are needed to be connected with 100 interfaces to be tested respectively, for 7 digital gate CD4067, the control module only needs to be connected with the control interface of the digital gate CD4067 through 7 input/output interfaces respectively, and is connected with the address interface of each digital gate CD4067 through 4 input/output interfaces, the interface to be tested can be selected, and then 6 MOS pipes in 6 can be controlled through 6 control interfaces, therefore, the control module can realize the connection test of each interface to be tested of the chip only through 17 GPIO interfaces, and the number of the interfaces of the control module is saved.
The above disclosure is only for the purpose of illustrating the preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention, therefore, all equivalent variations of the present invention are intended to be covered by the present invention.
Claims (10)
1. The utility model provides a chip interface connection test circuit, its characterized in that, chip interface connection test circuit includes control module, switch module and gating module, wherein:
the switch module is respectively connected with the control module, a preset power supply, a power supply interface of the chip and a grounding interface of the chip, and the voltage acquisition ends of the switch module and the control module are connected with a plurality of interfaces to be tested of the chip through the gating module;
the switch module is used for switching on or off the connection between the preset power supply and the power interface of the chip, the ground interface of the chip and the plurality of interfaces to be tested under the control of the control module so as to control the chip interface to connect the voltage provided by the test circuit to the power interface of the chip, the ground interface of the chip and the plurality of interfaces to be tested;
the gating module is used for communicating the connection between at least one interface to be tested in the plurality of interfaces to be tested and the voltage acquisition end of the control module under the control of the control module;
the control module is used for detecting the interface connection condition of the plurality of interfaces to be detected according to the voltage collected by the voltage collecting end.
2. The chip interface connection test circuit of claim 1, wherein the predetermined power supply comprises a power supply terminal and a ground terminal; the switch module comprises a first on-off unit, a second on-off unit and a third on-off unit; wherein:
the first end of the first on-off unit is connected with a power supply end of the preset power supply, the second end of the first on-off unit is connected with a grounding end of the preset power supply, the third end of the first on-off unit is connected with a power supply interface of the chip, the fourth end of the first on-off unit is connected with the control module, and the first on-off unit is used for controlling the voltage provided by the chip interface connection test circuit to the power supply interface of the chip under the control of the control module;
the first end of the second on-off unit is connected with a power supply end of the preset power supply, the second end of the second on-off unit is connected with a grounding end of the preset power supply, the third end of the second on-off unit and a voltage acquisition end of the control module are connected with the plurality of interfaces to be tested through the gating module, the fourth end of the second on-off unit is connected with the control module, and the first on-off unit is used for controlling the voltage provided by the chip interface connection test circuit to the at least one interface to be tested under the control of the control module;
the first end of the third breaking unit is connected with the power end of the preset power supply, the second end of the third breaking unit is connected with the grounding end of the preset power supply, the third end of the third breaking unit is connected with the grounding interface of the chip, the fourth end of the third breaking unit is connected with the control module, and the third breaking unit is used for controlling the voltage provided by the chip interface connection test circuit to the grounding interface of the chip under the control of the control module.
3. The chip interface connection test circuit of claim 2, further comprising a voltage divider module;
the third end of the second switching-on unit is connected with the gating module and the voltage acquisition end of the control module through the voltage division module; the voltage division module is used for forming a voltage division circuit with the gating module.
4. The chip interface connection test circuit of claim 2, wherein the first switching unit comprises a first resistor, a second resistor, a first transistor, and a second transistor;
one end of the first resistor is connected with a first control end of the control module and a controlled end of the first transistor, the other end of the first resistor is connected with a power end of the preset power supply and a power connection end of the first transistor, and a controlled response end of the first transistor is connected with a power interface of the chip;
one end of the second resistor is connected with the second control end of the control module and the controlled end of the second transistor, the other end of the second resistor is connected with the grounding end of the preset power supply and the power connection end of the second transistor, and the controlled response end of the second transistor is connected with the power interface of the chip.
5. The chip interface connection test circuit of claim 4, wherein the first transistor and the second transistor are both MOS transistors.
6. The chip interface connection test circuit of claim 2, wherein the second turn-on unit comprises a third resistor, a fourth resistor, a third transistor, and a fourth transistor;
one end of the third resistor is connected with a third control end of the control module and a controlled end of the third transistor, the other end of the third resistor is connected with a power supply end of the preset power supply and a power supply connecting end of the third transistor, and a controlled response end of the third transistor is connected with the gating module and a voltage acquisition end of the control module;
one end of the fourth resistor is connected with a fourth control end of the control module and a controlled end of the fourth transistor, the other end of the fourth resistor is connected with a grounding end of the preset power supply and a power connection end of the fourth transistor, and a controlled response end of the fourth transistor is connected with the gating module and a voltage acquisition end of the control module.
7. The chip interface connection test circuit of claim 2, wherein the third disconnection unit comprises a fifth resistor, a sixth resistor, a fifth transistor, and a sixth transistor;
one end of the fifth resistor is connected with a fifth control end of the control module and a controlled end of the fifth transistor, the other end of the fifth resistor is connected with a power supply end of the preset power supply and a power connection end of the fifth transistor, and a controlled response end of the fifth transistor is connected with a ground interface of the chip;
one end of the sixth resistor is connected with a sixth control end of the control module and a controlled end of the sixth transistor, the other end of the sixth resistor is connected with a grounding end of the preset power supply and a power connection end of the sixth transistor, and a controlled response end of the sixth transistor is connected with a grounding interface of the chip.
8. The chip interface connection test circuit of any one of claims 1-7, wherein the gating module comprises at least one multi-way analog switch, wherein:
the common interface of each multi-path analog switch is connected with the voltage acquisition end of the control module and the gating module, the address interface and the control interface of each multi-path analog switch are connected with the gating interface of the control module, and one input and output interface of one multi-path analog switch is connected with one interface to be tested of the chip.
9. The chip interface test circuit of claim 8, wherein the multi-way analog switch is a digital gate CD4067.
10. The chip interface connection test circuit of any one of claims 1-7, wherein the chip interface connection test circuit further comprises a connector; the connector is used for connecting the gating module and the plurality of interfaces to be tested of the chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222117100.5U CN218068218U (en) | 2022-08-12 | 2022-08-12 | Chip interface connection test circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222117100.5U CN218068218U (en) | 2022-08-12 | 2022-08-12 | Chip interface connection test circuit |
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| CN218068218U true CN218068218U (en) | 2022-12-16 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202222117100.5U Active CN218068218U (en) | 2022-08-12 | 2022-08-12 | Chip interface connection test circuit |
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| CN (1) | CN218068218U (en) |
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