CN117112330A

CN117112330A - Memory bank detection circuit, system and method

Info

Publication number: CN117112330A
Application number: CN202311100938.6A
Authority: CN
Inventors: 张琛星; 刘晓东; 祝国昌
Original assignee: Optofidelity High Tech Zhuhai Ltd
Current assignee: Optofidelity High Tech Zhuhai Ltd
Priority date: 2023-08-29
Filing date: 2023-08-29
Publication date: 2023-11-24

Abstract

The utility model relates to a memory strip detection circuit, system and method, detection circuit includes article to be tested, signal transfer board and test bottom plate, its characterized in that, test bottom plate includes function switching circuit, accept circuit, micro control circuit and communication circuit, article to be tested connects signal transfer board, signal transfer board connects function switching circuit, function switching circuit connects accepts the circuit, accept circuit connects micro control circuit, micro control circuit connects communication circuit, communication circuit connection terminal, function switching circuit is used for switching mode, mode includes the short circuit test and the electric leakage test of memory strip, accept the circuit and be used for converting the signal, micro control circuit is used for handling the signal and triggers function switching circuit and switch mode. The application can simplify the test process of the memory strip, improve the test speed and is applied to the field of memory strip test.

Description

Memory bank detection circuit, system and method

Technical Field

The present application relates to the field of memory stripe testing, and in particular, to a memory stripe detection circuit, system and method.

Background

The traditional memory strip test uses a computer motherboard as a test fixture, and the newly produced memory strip may have the risks of short circuit between a power pin and a functional pin and between the power pin and the ground, so that the computer motherboard is easy to damage, and when the computer motherboard and other test equipment are used for testing the memory strip, the test process is complex, and the test speed is slower.

Disclosure of Invention

Accordingly, an object of the embodiments of the present application is to provide a memory stripe detection circuit, system and method, which can simplify a memory stripe testing process and increase a testing speed.

In order to solve one of the above problems, in a first aspect, the present application provides a memory bank detection circuit, including a signal adapter board and a test board, where the test board includes a function switching circuit, a receiving circuit, a micro control circuit, and a communication circuit;

the to-be-tested product is connected with the signal switching board, the signal switching board is connected with the function switching circuit, the function switching circuit is connected with the bearing circuit, the bearing circuit is connected with the micro-control circuit, the micro-control circuit is connected with the communication circuit, and the communication circuit is connected with the terminal;

the function switching circuit is used for switching working modes, wherein the working modes comprise short circuit test and electric leakage test of the memory bank;

the receiving circuit is used for converting signals, and the micro control circuit is used for processing the signals and triggering the function switching circuit to switch the working mode.

Optionally, the function switching circuit comprises a relay circuit and a test switching circuit, and the relay circuit comprises a plurality of relays;

the relay circuit is connected with the signal adapter plate and the test switching circuit, and the test switching circuit is connected with the receiving circuit;

the relay circuit is used for switching the test pins of the to-be-tested product.

Optionally, the detection circuit further comprises a power supply circuit, wherein the power supply circuit comprises a constant current source circuit and a constant voltage source circuit;

the constant current source circuit comprises a constant current source generating circuit and a voltage limiting circuit, the constant current source generating circuit is connected with the voltage limiting circuit, and the voltage limiting circuit is connected with the function switching circuit;

the constant voltage source circuit is connected with the function switching circuit.

Optionally, the power supply circuit is connected with the micro-control circuit,

the micro control circuit is used for setting the output voltage of the power supply circuit;

the micro control circuit is also used for adjusting the output current of the power supply circuit.

Optionally, the test switching circuit includes a first switch, a second switch, and a fourth switch;

one side of the first switch, one side of the second switch and one side of the fourth switch are connected with the relay circuit;

the other side of the first switch is connected with the other side of the second switch and one side of the fourth switch;

the first switch and the second switch are combined to be used for switching a leakage test mode, the leakage test mode comprises a high-side leakage test and a low-side leakage test, and the fourth switch is used for switching the working mode.

Optionally, the test switching circuit further comprises a third switch;

one side of a third switch is connected with one side of the first switch and one side of the second switch, and the other side of the third switch is connected with one side of the voltage limiting circuit and one side of the constant voltage source circuit;

the third switch is used for switching power supply types, and the power supply types comprise constant current sources and constant voltage sources.

Optionally, the signal adapter plate comprises a read-write switching circuit and a relay driving circuit;

the read-write switching circuit is connected with the to-be-detected article, the read-write switching circuit is connected with the relay driving circuit, and the relay driving circuit is connected with the micro-control circuit;

the read-write switching circuit is used for switching read-write modes, wherein the read-write modes comprise a memory bank burning mode and a memory bank encryption and decryption mode;

the relay driving circuit is used for driving the read-write switching circuit.

Optionally, the signal patch panel further includes a bus interface circuit;

the bus interface circuit is connected with the read-write switching circuit, and the bus interface circuit is connected with the micro-control circuit;

the bus interface circuit is used for establishing communication between the read-write switching circuit and the micro control circuit.

In order to solve one of the above problems, a second aspect of the present application provides a memory bank detection system, including a terminal and a detection circuit as set forth in any one of the memory bank detection circuits; wherein,

the terminal is used for generating a control signal, receiving a detection signal, analyzing the detection signal to obtain a detection result, and displaying the detection result; the detection result comprises a detection signal, a test result of the to-be-detected article and a fault point of the to-be-detected article.

In order to solve one of the above problems, in a third aspect, the present application provides a memory bank detection method, applied to a memory bank detection system, the method comprising:

the micro control circuit confirms a working mode according to the received control signal and drives the function switching circuit according to the working mode;

the function switching circuit sequentially detects each pin signal of the to-be-detected product through the signal adapter plate, outputs the pin signals to the receiving circuit, converts the pin signals by the receiving circuit and sends the converted pin signals to the terminal through the communication circuit;

and the terminal determines a pin detection result according to the converted pin signal of the to-be-detected article and positions a fault pin.

Optionally, the method further comprises:

the microcontroller circuit confirms a read-write mode according to the received control signal, and confirms the connection mode of the signal adapter plate and the to-be-detected article according to the read-write mode; the connection mode comprises a burning connection mode and an encryption and decryption connection mode;

and the terminal changes the program stored in the to-be-tested product according to the connection mode through the communication module.

The application has the following beneficial effects: the application discloses a memory bank detection circuit, which comprises a signal switching board and a test base board, wherein the test base board comprises a function switching circuit, a receiving circuit, a micro control circuit and a communication circuit, a to-be-detected product is connected with the signal switching board, the signal switching board is connected with the function switching circuit, the function switching circuit is connected with the receiving circuit, the receiving circuit is connected with the micro control circuit, the micro control circuit is connected with the communication circuit, the communication circuit is connected with a terminal, the function switching circuit is used for switching a working mode, the working mode comprises a short circuit test and a leakage test of a memory bank, the receiving circuit is used for converting signals, the micro control circuit is used for processing the signals and triggering the function switching circuit to switch the working mode, and the micro control circuit is used for controlling the function switching circuit to complete the rapid switching of the working mode, so that the switching process is simplified, and the detection speed of the memory bank is improved.

Drawings

FIG. 1 is a schematic diagram of a memory bank detection circuit according to the present application;

FIG. 2 is a schematic diagram showing the connection of a function switching circuit in a memory bank detection circuit according to the present application;

FIG. 3 is a schematic diagram showing the connection of a power supply circuit in a memory bank detection circuit according to the present application;

FIG. 4 is a schematic diagram showing the connection between a power supply circuit and a micro control circuit in a memory bank detection circuit according to the present application;

FIG. 5 is a schematic diagram of circuit connection for OS test of a memory bank detection circuit according to the present application;

FIG. 6 is a schematic diagram of circuit connection of a high-side leakage test of a memory bank detection circuit according to the present application;

FIG. 7 is a schematic diagram of a circuit connection of a low-side leakage test of a memory bank detection circuit according to the present application;

FIG. 8 is a schematic diagram of the circuit connection of the memory bank detection circuit burning and encryption and decryption provided by the application;

FIG. 9 is a schematic diagram showing the connection between a read-write switching circuit and a relay driving circuit in a memory bank detection circuit according to the present application;

fig. 10 is a schematic diagram of a power supply circuit board of a memory bank detection circuit provided by the present application.

Detailed Description

The application will now be described in further detail with reference to the drawings and to specific examples. The step numbers in the following embodiments are set for convenience of illustration only, and the order between the steps is not limited in any way, and the execution order of the steps in the embodiments may be adaptively adjusted according to the understanding of those skilled in the art.

For a better understanding of embodiments of the present application, the following terms will now be explained.

OPEN/SHORT (OS) test: the method is mainly used for testing the connection condition of the electronic devices, testing the open circuit and the short circuit of the electronic devices, and testing whether the place where one electronic device should be connected is connected, wherein the place where the electronic device should be connected is not connected or is open circuit, and the place where the electronic device should not be connected is connected or is short circuit.

Digital-to-analog converter (Digital to analog converter, DAC): is a device that converts digital signals into analog signals (in the form of current, voltage or charge). In many digital systems (e.g., computers), signals are stored and transmitted digitally, and digital-to-analog converters can convert such signals to analog signals so that they can be recognized by the outside world (human or other non-digital system).

Analog-to-Digital Converter (ADC): refers to devices that convert a continuously variable analog signal to a discrete digital signal. Analog signals, such as temperature, pressure, sound or images, etc., need to be converted into digital form for easy storage, processing and transmission. The analog-to-digital converter can perform this function and its shadow can be found in a variety of different products.

Constant current source: the alternating current constant current source, the direct current constant current source, the current generator and the large current generator are also called a current source and a steady current source, and are wide-frequency-spectrum high-precision alternating current steady current power supplies, high in response speed, high in constant current precision, capable of stably working for a long time, suitable for loads with various properties (resistive, inductive, capacitive) and the like. The method is mainly used for detecting production occasions such as thermal relays, molded case circuit breakers, small short-circuiting devices and the like, wherein rated current, action current, short-circuit protection current and the like are required to be set.

Microcontroller (MCU): an integrated circuit chip is a small and perfect microcomputer system formed by integrating the functions of CPU, RAM, ROM, I/O ports, interrupt system, timer and counter with data processing capability on a silicon chip by using very large scale integrated circuit technique.

In order to solve the above problems, in some embodiments, as shown in fig. 1, fig. 1 is a schematic diagram of a memory bank detection circuit, and the present application provides a memory bank detection circuit, including a signal adapter board and a test board, where the test board includes a function switching circuit, a receiving circuit, a micro control circuit and a communication circuit;

Specifically, the to-be-tested product is connected into the test circuit through the signal adapter plate, wherein each pin of the to-be-tested product is connected into the signal adapter plate respectively and then is connected into the test bottom plate, the connection modes of the function switching circuits are different, the electric leakage test and the OS test can be respectively realized, the pin signals of the to-be-tested product enter the receiving circuit through the function switching circuits with different connection modes, the receiving circuit simply processes the pin signals, the pin signals are sent to the terminal through the communication module after being processed by the micro control circuit, and the terminal judges whether the signal pin is faulty or normal according to the limit.

The micro control signal can also control the function switching circuit to switch to different working modes according to the test content selected by the terminal, and the function switching circuit automatically switches the connection mode according to the driving signal, so that the test circuit can complete high-side electric leakage test, low-side electric leakage test, open circuit test and short circuit test.

The micro control circuit can comprise, but is not limited to, a single chip microcomputer circuit, a serial port debugging circuit, a reset circuit, a prompting circuit and a burning circuit, wherein the single chip microcomputer circuit can complete signal analysis, control a driving function switching circuit and realize communication, and the communication comprises communication with a communication circuit and communication of a signal adapter plate; the serial port debugging circuit is used for debugging the circuit board; the reset circuit is used for resetting the singlechip circuit and returning to factory setting; the prompting circuit is used for prompting the power-on of the circuit; the burning circuit is used for switching the burning mode of the singlechip.

In order to solve the above-mentioned problems, in some embodiments, as shown in fig. 2, fig. 2 is a schematic diagram showing connection of a function switching circuit in a memory bank detection circuit; the function switching circuit comprises a relay circuit and a test switching circuit, and the relay circuit comprises a plurality of relays;

The relay circuit is matched with the function switching circuit, pins of the to-be-tested product are led into the detection circuit one by one under the corresponding test content, and detection of all pins of the to-be-tested product is achieved.

In order to solve the above-mentioned problems, in some embodiments, as shown in fig. 3, fig. 3 is a schematic connection diagram of a power supply circuit in a memory stripe detection circuit, where the detection circuit further includes a power supply circuit, and the power supply circuit includes a constant current source circuit and a constant voltage source circuit;

The constant current source circuit can also comprise a driving circuit of the function switching circuit, and the driving circuit is used for driving the function switching circuit according to the output current of the constant current source circuit, particularly, the micro control circuit sends a control signal according to the test content, the constant current source circuit passes through the driving circuit according to the control signal, and the driving function switching circuit is started in a mode corresponding to the test content, wherein the test content comprises a short circuit test and an open circuit test.

Specifically, the OS test includes an open circuit test and a short circuit test, and when the OS test is performed, the microcontroller circuit selectively turns on the constant current source circuit and the function switching circuit to supply power to the OS test.

When the high-side leakage test and the low-side leakage test are performed, the micro control circuit selectively connects the constant voltage source circuit and the function switching circuit to supply power for the high-side leakage test and the low-side leakage test.

In order to solve the above-mentioned problems, in some embodiments, as shown in fig. 4, fig. 4 is a schematic diagram showing connection between a power circuit and a micro control circuit in a memory bank detection circuit, the power circuit is connected to the micro control circuit,

Specifically, the microcontroller circuit adjusts the power supply gear of the constant current source generating circuit, sets different current magnitudes, sets a protection voltage for the OS test through the voltage limiting circuit, wherein the protection voltage may be, but is not limited to, 2.5V and 3V, and in addition, the constant current source circuit may further include a reference voltage circuit, and provides different reference voltages for the voltage limiting circuit, so that the voltage limiting circuit sets the protection voltage as a reference voltage, and the reference voltages may include 2.5V and 3V.

The micro control circuit regulates the output voltage of the constant voltage source circuit, and sets protection voltage and protection current for high-side leakage test and low-side leakage test.

In order to solve the above problem, in some embodiments, as shown in fig. 5, fig. 5 is a schematic circuit connection diagram of an OS test of a memory bank detection circuit, in which KA is a first switch, KB is a second switch, KC is a third switch, KD is a fourth switch, TP1-TP288 is a pin to be tested, KA1-KA288 is a connection line between each relay in a relay circuit and the first switch, and KB1-KB288 is a connection line between each relay in the relay circuit and the second switch.

The test switching circuit comprises a first switch, a second switch and a fourth switch;

The working mode is the same as the working mode, and the switching of the working mode is realized by changing the internal switching contact of the fourth switch and the switching of the relay circuit and the pin to be tested, the first switch and the second switch.

And when the contact position of the fourth switch is in the leakage test mode, the contact connection points of the first switch and the second switch are changed to finish switching of the high-side leakage test and the low-side leakage test.

To solve the above problem, in some embodiments, the test switching circuit further includes a third switch as shown in fig. 5;

Specifically, in the case of OS testing, as shown in fig. 5, the detection circuits KA1, KB2 to KB288 are closed, KB1, KA2 to KA288 are opened, and KA, KB, KC, KD are connected to the contacts shown in fig. 5, wherein the light-colored connection line portion indicates that KB2 to KB288 are closed to short the test pins except the TP1 pin on the test sample, and short the power supply (GND) of the constant current source circuit through the KB short-circuit contacts.

As shown by dark connection lines in fig. 5, a power signal reaches a pin TP1 under test of the sample to be tested from the positive electrode of the constant current source circuit through KC, KA and KA1, and as shown by light connection lines in fig. 5, the power signal returns to the negative electrode of the constant current source circuit through TP2-TP288 through KB and KC, and the micro control circuit collects voltages V at two ends of TP1 and TP2-TP140 through the receiving circuit, so as to calculate the current TP1 point OS resistance value r=v/I (I is a known current and comes from the constant current source circuit).

After the detection of the TP1 pins is finished, the relay circuit is switched to other pins, the steps are repeated, all 288 TP point tests are finally tested, test results are uploaded to the terminal while the test is carried out, the terminal judges whether the resistance value R is in a normal range, the resistance value R passes through the detection when the resistance value R is in the normal range, the current detected pins are positioned to fault pins when the resistance value R does not pass through the detection when the resistance value R is not in the normal range.

In addition, the program can be burnt in the MCU in the micro control circuit, so that the micro control circuit can process the pin signal, judge whether the resistance value R is in a normal range, pass detection if the resistance value R is not in the normal range, fail detection if the resistance value R is not in the normal range, locate the fault pin on the currently detected pin, collect the voltage V at the two ends of TP1 and TP2-TP140, pass detection, fail detection and send the pin number of the to-be-detected product to the terminal by the receiving circuit, and the terminal can only be used for displaying the resistance value R, collect the voltage V at the two ends of TP1 and TP2-TP140, pass detection, fail detection and the pin number of the to-be-detected product.

In the high-side leakage test, as shown in fig. 6, fig. 6 is a circuit connection schematic diagram of the high-side leakage test of the memory bank detection circuit, the detection circuits KA1, KB 2-KB 288 are closed, KB1, KA 2-KA 288 are opened, KA, KB, KC, KD are connected to the contacts shown in fig. 6, wherein the light-colored connection line portion indicates that KB 2-KB 288 are closed to short the test pins of the test article except the TP1 pin, and short the test pins to the negative electrode (GND) of the constant voltage source circuit through the KB short-circuit contacts.

As shown by dark connection lines in fig. 6, a power signal passes through KC and KA from the positive electrode of the constant voltage source circuit and reaches a pin TP1 under test of the sample to be tested through a sampling resistor Rs, as shown by light connection lines in fig. 6, the power signal passes through TP2-TP288 and passes through KB and KC to return to the negative electrode of the constant voltage source circuit, and the micro control circuit collects the voltages V at both ends of the sampling resistor through the receiving circuit and calculates the leakage current i=v/Rs (Rs is a sampling resistor with a known size) of the current TP1 pin.

After the detection of the TP1 pins is finished, the relay circuit is switched to other pins, the testing steps are repeated, all 288 TP point tests are finally tested, test results are uploaded to the terminal while testing, the terminal judges whether the leakage current I is in a normal range, if the leakage current I is in the normal range, the leakage current I is detected, if the leakage current I is not in the normal range, the leakage current I is not detected, and the fault pin is positioned as the currently detected pin.

In addition, the program can be burnt in the MCU in the micro control circuit, so that the micro control circuit can process the pin signals, judge whether the leakage current I is in a normal range, pass detection if the leakage current I is not in the normal range, fail detection if the leakage current I is not in the normal range, locate the currently detected pin with the fault pin, collect the voltage V at the two ends of TP1 and TP2-TP140, pass detection, fail detection and send the pin numbers of the to-be-detected products to the terminal, and the terminal can only be used for displaying the leakage current I, collect the voltage V at the two ends of TP1 and TP2-TP140, pass detection, fail detection and the pin numbers of the to-be-detected products.

In the low-side leakage test, as shown in fig. 7, fig. 7 is a circuit connection schematic diagram of a low-side leakage test of a memory bank detection circuit, detection circuits KB1, KA 2-KA 288 are closed, KA1, KB 2-KB 288 are opened, KA, KB, KC, KD is connected with contacts shown in fig. 7, and the dark connection line portions KA 2-KA 288 of fig. 7 are closed to short the test points except for TP1 of the test sample and then short the test points to the positive electrode of the constant voltage source circuit through the KA short-circuit contacts.

As shown by the dark connection line in fig. 7, the power signal reaches TP2-TP288 from the positive pole of the constant voltage source circuit through KA, and reaches the sampling resistor Rs through TP1 and KA as shown by the dark connection line in fig. 6, the micro control circuit collects the voltages V at two ends of the sampling resistor through the receiving circuit, and calculates the leakage current i=v/Rs (Rs is the sampling resistor with a known size) of the current TP1 pin.

From the above analysis, it is known that the constant current source circuit is used for OS test, the constant voltage source circuit is used for leakage test, the third switch is used for switching the power supply type, the power supply type includes constant current source and constant voltage source, and the first switch and the second switch are combined to realize switching of low side leakage test and high side leakage test.

In order to solve the above-mentioned problems, in some embodiments, as shown in fig. 8, fig. 8 is a circuit connection schematic diagram of the memory bank detection circuit for writing and encrypting and decrypting, and the signal switching board includes a read-write switching circuit and a relay driving circuit;

the relay driving circuit is used for driving the read-write switching circuit.

As shown in FIG. 8, the read-write switching circuit comprises switches K1-K8, the switch K1 is connected with the SDA pin and the SCL pin of the to-be-detected article, the switch K2 is connected with the VDD_SPD pin and the VSS pin of the to-be-detected article, the switch K3 is connected with the EVENT pin and the SA0 pin of the to-be-detected article, the switch K5 is connected, one contact of the switch K5 is connected with the switch K6 through a resistor, the other contact is grounded through the resistor, two contacts of the switch K6 are respectively connected with 10V and 3.3V, two contacts of the switch K4 are respectively connected with the SA1 pin and the SA2 pin of the to-be-detected article, two contacts of the switch K7 are respectively connected with 3.3V and grounded, and two contacts of the switch K8 are respectively connected with 3.3V and grounded.

As shown in fig. 9, fig. 9 is a schematic diagram of connection between a read-write switching circuit and a relay driving circuit in a memory bank detection circuit, wherein 8 pins K1-K8 of the relay driving circuit are respectively connected with pins corresponding to the switches K1-K8, and are respectively used for driving the switches K1-K8, for example, the pin K1 of the switch K1 is connected with the corresponding pin K1 in the relay driving circuit. The other 10 pins PA1-PA7 and PB10 and PB11 of the relay driving circuit are respectively connected with the MCU host of the micro control circuit, so that the micro control circuit can control the on of the switches K1-K8.

To address the above problems, in some embodiments, as shown in fig. 8 and 9, the signal patch panel further includes a bus interface circuit;

Specifically, in combination with the read-write switching circuit and the relay driving circuit, when in a memory bank burning mode, K1, K2, K3 and K4 are closed, K5, K6, K7 and K8 are opened, pins SDA and SCL of the to-be-tested product are connected to a terminal through a bus interface circuit, a communication link between the terminal and the to-be-tested product is connected, VDD_SPD of the to-be-tested product is connected with 3.3V, VSS is connected with GND, power supply of the to-be-tested product is connected, and pins SA0, SA1 and SA2 of the to-be-tested product are connected with GND to set a communication address of the to-be-tested product. The to-be-tested product enters a burning mode and is burnt into the to-be-tested product through an I2C interface burning program.

When the memory bank is in an encryption and decryption mode, the switches K1, K2, K3, K4, K5 and K6 are closed, the switches K7 and K8 are opened, the pins SDA and SCL of the to-be-tested product are connected to the terminal through the bus interface circuit, so that the communication link between the terminal and the to-be-tested product is connected, the pin VDD_SPD of the to-be-tested product is connected with 3.3V, the pin VSS is connected with GND, the power supply of the to-be-tested product is connected, the pin SA0 is connected with 10V, the detection circuit is set to be in an encryption/decryption mode, and the pins SA1 and SA2 of the to-be-tested product are connected with GND to set the communication address of the to-be-tested product. The test article enters an encryption/decryption mode. The program stored on the test article is encrypted/decrypted through the I2C interface.

In order to solve the above problems, in some embodiments, as shown in fig. 10, fig. 10 is a schematic diagram of a power supply circuit board of a memory stripe detection circuit, where the detection circuit further includes a power supply circuit board, and the power supply circuit board is connected to a signal adapter board and a test base board, and includes a power input circuit, a filter circuit, a power indicator circuit, and a voltage conversion circuit, where a power supply is connected to a power supply voltage through the power input circuit, and the power supply voltage may be, but is not limited to +12v, -12v, and +5v. The power supply voltage is filtered by a filter circuit and then is subjected to level conversion by a voltage conversion circuit, and the power supply voltage for supplying power to each circuit is converted, wherein the power supply voltage comprises, but is not limited to, A+10V, A-10V, A+3.3V and D+3.3V, wherein A+10V, A-10V and A+3.3V are used for an analog circuit part, and D+3.3V is used for a digital circuit.

Through the embodiment, one detection circuit can complete DDR4 memory burning/encrypting/decrypting, DDR4 memory bank OS testing, high side leakage testing and low side leakage testing.

In order to solve the above problems, in some embodiments, the present application provides a detection circuit including a terminal and any one of the above embodiments of a memory bank detection circuit; wherein,

The specific process and technical terms are the same as those of the detection circuit, and are not repeated here.

In order to solve the above-mentioned problems, in some embodiments, the present application provides a memory bank detection method, which is applied to a detection system of a memory bank detection system, and is characterized in that the method includes:

To solve the above-mentioned problem, in some embodiments, the method further comprises:

While the preferred embodiment of the present application has been described in detail, the application is not limited to the embodiment, and various equivalent modifications and substitutions can be made by those skilled in the art without departing from the spirit of the application, and these equivalent modifications and substitutions are intended to be included in the scope of the present application as defined in the appended claims.

Claims

1. The memory bank detection circuit comprises a signal adapter plate and a test bottom plate, and is characterized in that the test bottom plate comprises a function switching circuit, a receiving circuit, a micro control circuit and a communication circuit;

2. The detection circuit according to claim 1, wherein the function switching circuit comprises a relay circuit and a test switching circuit, the relay circuit comprising a plurality of relays;

3. The detection circuit according to claim 2, wherein the detection circuit further comprises a power supply circuit including a constant current source circuit and a constant voltage source circuit;

4. The detection circuit of claim 3, wherein the power circuit is connected to the micro-control circuit,

5. The detection circuit of claim 3, wherein the test switching circuit comprises a first switch, a second switch, and a fourth switch;

6. The detection circuit of claim 5, wherein the test switching circuit further comprises a third switch;

7. The detection circuit according to claim 1, wherein the signal patch panel includes a read-write switching circuit, a relay driving circuit;

the relay driving circuit is used for driving the read-write switching circuit.

8. The detection circuit of claim 7, wherein the signal patch panel further comprises a bus interface circuit;

9. A memory bank detection system comprising a terminal and the detection circuit of any one of claims 1-8; wherein,

10. A memory bank detection method applied to the detection system of claim 9, wherein the method comprises: