CN218041488U - Signal processing circuit, synchronous phase locking system and video processing equipment - Google Patents
Signal processing circuit, synchronous phase locking system and video processing equipment Download PDFInfo
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- CN218041488U CN218041488U CN202222132312.0U CN202222132312U CN218041488U CN 218041488 U CN218041488 U CN 218041488U CN 202222132312 U CN202222132312 U CN 202222132312U CN 218041488 U CN218041488 U CN 218041488U
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Abstract
The application discloses a signal processing circuit, a synchronous phase locking system and a video processing device. Wherein, this circuit includes: a signal input circuit for inputting a first video signal; the external bias circuit is connected with the input circuit and is used for adjusting the bias voltage of the first video signal to be matched with the central point voltage of the effective input voltage range of the signal amplification circuit to obtain a second video signal; the signal amplification circuit is connected with the external bias circuit and used for amplifying the second video signal to obtain a third video signal; the signal separation circuit is connected with the signal amplification circuit and is used for separating the synchronous signal from the third video signal and outputting the synchronous signal; and the signal output circuit is connected with the signal amplifying circuit and used for outputting the third video signal. The method and the device solve the technical problems that in the related technology, the quality of synchronous signals in a synchronous phase-locked system is poor, and multistage cascade is difficult to realize.
Description
Technical Field
The application relates to the technical field of video display, in particular to a signal processing circuit, a synchronous phase-locking system and video processing equipment.
Background
The Genlock system is a frame synchronization technology, usually used in video post-processing, non-linear editing (NLE) and studio, and can synchronize the output signal of workstation image system with the externally generated signal, thus ensuring effective cooperation between all devices (such as video camera, video recorder, animation or caption machine, etc.) in the studio, i.e. it can use multiple sets of video systems and one path of video source to realize synchronous output. However, in the related circuit, when the synchronous input signal receives interference or the quality is deteriorated, the quality of the subsequent synchronous signal is affected, and in addition, when the circuit is adopted to realize the cascade output of the multi-stage synchronous signals, the output loss of the output signals of the synchronous ring is superposed step by step, and finally the synchronous stage number is affected.
In view of the above problems, no effective solution has been proposed.
SUMMERY OF THE UTILITY MODEL
The embodiment of the application provides a signal processing circuit, a genlock system and a video processing device, which at least solve the technical problems that the quality of synchronous signals in the genlock system is poor and multistage cascade is difficult to realize in the related technology.
According to an aspect of an embodiment of the present application, there is provided a signal processing circuit including: a signal input circuit for inputting a first video signal; the external bias circuit is connected with the input circuit and is used for adjusting the bias voltage of the first video signal to be matched with the central point voltage of the effective input voltage range of the signal amplification circuit to obtain a second video signal; the signal amplification circuit is connected with the external bias circuit and used for amplifying the second video signal to obtain a third video signal; a signal separation circuit connected to the signal amplification circuit for separating the synchronization signal from the third video signal and outputting the synchronization signal; and the signal output circuit is connected with the signal amplifying circuit and used for outputting the third video signal.
Optionally, the external bias circuit includes: and the first resistor is used for adjusting the bias voltage of the first video signal, wherein the first end of the first resistor is connected with the voltage input source, and the second end of the first resistor is connected with the input end of the signal amplification circuit.
Optionally, the resistance of the first resistor is a preset resistance, and is configured to adjust the bias voltage of the first video signal to a target amplitude, where the target amplitude is not less than a center point voltage of an effective input voltage range of the signal amplification circuit, and a difference between the target amplitude and the center point voltage is less than a preset threshold.
Optionally, the signal processing circuit further includes: and the output coupling circuit is connected between the signal amplifying circuit and the signal output circuit, wherein the output coupling circuit is a direct current coupling circuit.
Optionally, the output coupling circuit includes: the first end of the second resistor is connected with the output end of the signal amplification circuit, and the second end of the second resistor is connected with the first end of the third resistor; the second end of the third resistor is connected with the input end of the signal output circuit; the first end of the first capacitor is connected with the output end of the signal amplification circuit, and the second end of the first capacitor is connected with the ground; a first end of the fourth resistor is connected with the second end of the second resistor, and a second end of the fourth resistor is connected with the ground; and a second capacitor, wherein a first end of the second capacitor is connected with a second end of the third resistor, and a second end of the second capacitor is connected with the ground.
Optionally, the signal processing circuit further includes: and the input coupling circuit is connected between the signal input circuit and the signal amplification circuit, wherein the input coupling circuit is an alternating current coupling circuit.
Optionally, the input coupling circuit includes: a first end of the fifth resistor is connected with the output end of the input circuit, and a second end of the fifth resistor is connected with the first end of the second capacitor; the second end of the second capacitor is connected with the input end of the signal amplification circuit; a first end of the third capacitor is connected with the second end of the fifth resistor, and a second end of the third capacitor is connected with the ground; and a first end of the sixth resistor is connected with the second end of the fifth resistor, and a second end of the sixth resistor is connected with the ground.
According to another aspect of the embodiments of the present application, there is also provided a genlock system, including: the signal processing circuit is cascaded in a plurality of stages, wherein the signal processing circuit is the signal processing circuit.
Alternatively, for any two adjacent stages of signal processing circuits, the signal input circuit of the lower stage signal processing circuit is connected to the signal output circuit of the upper stage signal processing circuit.
According to another aspect of the embodiments of the present application, there is also provided a video processing apparatus, including: the input module, the output module and the control module are respectively connected with the processing module; the control module and/or the input module are/is provided with a synchronization module, and the synchronization module is provided with the signal processing circuit.
In an embodiment of the present application, a signal input circuit for inputting a first video signal; the external bias circuit is connected with the input circuit and is used for adjusting the bias voltage of the first video signal to be matched with the central point voltage of the effective input voltage range of the signal amplification circuit to obtain a second video signal; the signal amplification circuit is connected with the external bias circuit and used for amplifying the second video signal to obtain a third video signal; the signal separation circuit is connected with the signal amplification circuit and is used for separating the synchronous signal from the third video signal and outputting the synchronous signal; and the signal output circuit is connected with the signal amplifying circuit and is used for outputting a third video signal. Through effective arrangement of an external bias circuit, the tolerance of the signal amplification circuit to input signals can be increased, and the transmission performance of a system is improved; meanwhile, a direct-current coupling capacitor is adopted for a synchronous ring output signal passing through the signal amplification circuit, the processing capacity of the circuit for the synchronous signal is improved, the loss of the ring output signal is reduced, and the technical problems that in the related technology, the quality of the synchronous signal in a synchronous phase-locked system is poor and multistage cascade is difficult to realize are solved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
FIG. 1 is a schematic diagram of an alternative signal processing circuit according to the related art;
FIG. 2 is a waveform diagram of an alternative sync ring-out signal according to the related art;
FIG. 3 is a schematic diagram of a signal processing circuit according to an embodiment of the present application;
FIG. 4 is a schematic diagram of an alternative external bias circuit and signal amplification circuit according to an embodiment of the present application;
FIG. 5 is a schematic diagram of another signal processing circuit according to an embodiment of the present application;
FIG. 6 is a schematic diagram of an input coupling circuit according to an embodiment of the present application;
FIG. 7 is a schematic diagram of an output coupling circuit according to an embodiment of the present application;
FIG. 8 is a block diagram of a signal processing system according to an embodiment of the present application;
fig. 9 is a schematic structural diagram of a video processing device according to an embodiment of the present application.
Detailed Description
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the accompanying drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Example 1
The Genlock Genlock system is widely applied to the field of video display, and the technology can realize synchronous output of a plurality of sets of video systems and one path of video source. In the related art, the whole circuit is generally composed of a signal input circuit, a signal amplifying circuit, a signal separating circuit, a coupling circuit, and a signal output circuit, as shown in fig. 1. However, when the circuit is used to realize synchronous output, when the synchronous input signal is interfered or has poor quality, the quality of the subsequent synchronous signal can be affected, and in addition, when the circuit is used to realize the cascade output of multi-stage synchronous signals, the output loss of the output signals of the synchronous ring can be overlapped step by step, and finally the synchronous stage number is affected. Fig. 2 is a schematic diagram showing a waveform of a sync-loop-out signal output by a signal output circuit, where a portion circled by a square frame is a waveform distortion caused by multi-stage cascade link superposition using the circuit to the sync-loop-out signal.
In order to solve the above problem, embodiments of the present application provide a signal processing circuit, wherein, with an effective external bias circuit arrangement, the tolerance of a signal amplification circuit to an input signal can be increased, and the system transmission performance can be increased; meanwhile, the direct current coupling capacitor is adopted for the synchronous ring output signal passing through the signal amplification circuit, the processing capacity of the circuit on the synchronous signal can be improved, and the loss of the ring output signal is reduced.
Fig. 3 is a schematic structural diagram of an alternative signal processing circuit according to an embodiment of the present application, and as shown in fig. 3, the circuit includes at least a signal input circuit 31, an external bias circuit 32, a signal amplification circuit 33, a signal separation circuit 34, and a signal output circuit 35, where:
a signal input circuit 31 for inputting a first video signal;
an external bias circuit 32 connected to the signal input circuit 31 for adjusting a bias voltage of the first video signal to match a center point voltage of an effective input voltage range of the signal amplifying circuit 33 to obtain a second video signal;
a signal amplifying circuit 33 connected to the external bias circuit 32, for amplifying the second video signal to obtain a third video signal;
a signal separation circuit 34 connected to the signal amplification circuit 33, for separating the synchronization signal from the third video signal and outputting the synchronization signal;
and a signal output circuit 35 connected to the signal amplification circuit 33 for outputting the third video signal.
The specific structure of each unit in the signal processing circuit is described in detail below with reference to the accompanying drawings.
First, considering that the video signal voltage input to the signal amplifying circuit 33 is not a fixed amplitude and may fluctuate due to external interference, and when the amplitude of the video signal of the ac waveform is biased to the upper limit or the lower limit, it is easy to exceed the range of the amplitude of the signal amplifying circuit, therefore, the present embodiment proposes to provide an effective external bias circuit 32 between the signal input circuit 31 and the signal amplifying circuit 33 to adjust the bias voltage of the first video signal to be matched with the voltage of the center point of the effective input voltage range of the signal amplifying circuit 33, so as to ensure that the video signal voltage still stays within the effective range of the signal amplifying circuit 33 when the fluctuation range of the amplitude of the first video signal is large.
As an alternative embodiment, the external bias circuit 32 includes a first resistor for adjusting a bias voltage of the first video signal, wherein a first terminal of the first resistor is connected to the voltage input source, and a second terminal of the first resistor is connected to the input terminal of the signal amplifying circuit 33.
Specifically, the resistance of the first resistor is a preset resistance, and is configured to adjust the bias voltage of the first video signal to a target amplitude, where the target amplitude is not less than a center-point voltage of an effective input voltage range of the signal amplification circuit, and a difference between the target amplitude and the center-point voltage is less than a preset threshold.
FIG. 4 shows a schematic diagram of the connection of an external bias circuit 32 and a signal amplification circuit 33, where R in Is a first resistance, C in Determining the first resistance R for the coupling capacitance for coupling the input first video signal is described below in conjunction with FIG. 4 in And (4) resistance value process.
First, a valid input voltage range of the signal amplifying circuit 33 is determined, which requires calculation of an internal voltage offset of the signal amplifying circuit 33, for example, when the input voltage V is S+ At 3.3V, the effective input voltage range of the signal amplification circuit 33 is 0V-1.5V.
In order to improve the tolerance range of the signal amplifying circuit 33 to the input signal quality, the bias voltage of the input first video signal needs to be adjusted by the external bias circuit 32, i.e. by the first resistor R in Setting the voltage of the dc bias point of the first video signal at 1/2 of the effective input voltage range of the signal amplifying circuit 33 (i.e. 0.75V), considering that the dc bias point of the output signal of the actual signal amplifying circuit 33 is the same as the input first video signal, the dc bias point of the first video signal can be raised appropriately according to the actual test, for example, the input dc bias point is raised to 0.94V in the embodiment of the present application, because the input voltage V of the signal amplifying circuit 33 is set to 0.75V in Is calculated by the formula V in ＝3.3V*[800K/(800K+R in )]I.e. passing through 0.94V = 3.3V/(800K + R) in )]Calculating to obtain a first resistance R in ＝2MΩ。
By setting the external bias circuit 32, the tolerance range of the signal amplification circuit 33 to the quality of the input signal can be increased, and the quality of the synchronization signal can be improved, thereby increasing the transmission performance of the system.
Alternatively, the signal amplifying circuit 33 may also select an amplifier chip, which enhances the video synchronization signal mainly by amplifying the video signal.
The signal separation circuit 34 is configured to separate a synchronization signal from the third video signal and output the synchronization signal to a target port, such as an upper computer; the signal output circuit 35 is configured to output a third video signal, where the third video signal is output in a dc manner, so as to ensure that the third video signal can be transmitted without distortion.
Fig. 5 shows a schematic diagram of another alternative signal processing circuit based on the signal processing circuit shown in fig. 3, and as shown in fig. 5, the circuit further includes an input coupling circuit 36 and an output coupling circuit 37.
In order to filter out the dc component in the input signal and ensure that the external bias circuit arranged at the subsequent stage is not affected by the input dc component, in the embodiment of the present application, an input coupling circuit 36 is arranged in the signal processing circuit, and is connected between the signal input circuit 31 and the signal amplification circuit 33, and the input coupling circuit 36 is an ac coupling circuit.
Specifically, the input coupling circuit 36 includes: the first end of the fifth resistor is connected with the output end of the input circuit, the second end of the fifth resistor is connected with the first end of the second capacitor, the second end of the second capacitor is connected with the input end of the signal amplification circuit, the first end of the third capacitor is connected with the second end of the fifth resistor, the second end of the third capacitor is connected with the ground, the first end of the sixth resistor is connected with the second end of the fifth resistor, and the second end of the sixth resistor is connected with the ground.
FIG. 6 shows a schematic diagram of an alternative input coupling circuit, in which a fifth resistor R 9 Set to 4k omega, a second capacitance C 28 Set to 0.1uF, third capacitance C 10 Set to 10pF, a sixth resistor R 11 Set to 75 omega.
Meanwhile, in order to improve the attenuation of the signal caused by the coupling capacitance, in the embodiment of the present application, an output coupling circuit 37 is further provided in the signal processing circuit, and is connected between the signal amplifying circuit 33 and the signal output circuit 35, and the output coupling circuit 37 is a dc coupling circuit.
Specifically, the output coupling circuit 37 includes: the first end of the second resistor is connected with the output end of the signal amplifying circuit, the second end of the first capacitor is connected with the ground, the first end of the fourth resistor is connected with the second end of the second resistor, the second end of the fourth resistor is connected with the ground, the first end of the second capacitor is connected with the second end of the third resistor, and the second end of the second capacitor is connected with the ground.
FIG. 7 shows a schematic diagram of an alternative output coupling circuit, in which a second resistor R 7 Setting 75 omega, third resistance R 10 Set to 75 omega, a first capacitance C 7 Set to 10pF, fourth resistor R 40 Set to 4k omega, a second capacitance C 8 Set to 10uF.
It should be noted that, in the multi-stage signal transmission, the dc component generated by the dc coupling is filtered out at the input ac coupling part of the next stage, so as to ensure the validity of the synchronous output signal of the signal amplification circuit.
The input coupling circuit and the output coupling circuit are added in front of and behind the signal amplification circuit, so that the problem of circuit loss of the synchronous signals output by the input preceding stage output loop is solved, signal transmission is more stable, signal stability is higher, and the number of video systems in which the synchronous signals are cascaded is also obviously increased.
In the entire signal processing circuit of the embodiment of the present application, a signal input circuit for inputting a first video signal; the external bias circuit is connected with the input circuit and is used for adjusting the bias voltage of the first video signal to be matched with the central point voltage of the effective input voltage range of the signal amplification circuit to obtain a second video signal; the signal amplification circuit is connected with the external bias circuit and used for amplifying the second video signal to obtain a third video signal; the signal separation circuit is connected with the signal amplification circuit and is used for separating the synchronous signal from the third video signal and outputting the synchronous signal; and the signal output circuit is connected with the signal amplifying circuit and is used for outputting a third video signal. Through effective arrangement of an external bias circuit, the tolerance of the signal amplification circuit to input signals can be increased, and the transmission performance of a system is improved; meanwhile, a direct-current coupling capacitor is adopted for a synchronous ring output signal passing through the signal amplification circuit, the processing capacity of the circuit for the synchronous signal is improved, the loss of the ring output signal is reduced, and the technical problems that in the related technology, the quality of the synchronous signal in a synchronous phase-locked system is poor and multistage cascade is difficult to realize are solved.
Example 2
In addition to the signal processing circuit provided in embodiment 1, an embodiment of the present application further provides a genlock system, as shown in fig. 8, the system includes signal processing circuits 81 to 8n cascaded in multiple stages, where, for any two adjacent signal processing circuits, a signal input circuit of a lower signal processing circuit is connected to a signal output circuit of an upper signal processing circuit.
Specifically, each stage of signal processing circuit includes: signal input circuit, external bias circuit, signal amplification circuit, separating circuit and signal output circuit, wherein:
a signal input circuit for inputting a first video signal;
the external bias circuit is connected with the signal input circuit and is used for adjusting the bias voltage of the first video signal to be matched with the central point voltage of the effective input voltage range of the signal amplification circuit to obtain a second video signal;
the signal amplification circuit is connected with the external bias circuit and used for amplifying the second video signal to obtain a third video signal;
the signal separation circuit is connected with the signal amplification circuit and is used for separating the synchronous signal from the third video signal and outputting the synchronous signal;
and the signal output circuit is connected with the signal amplifying circuit and used for outputting the third video signal.
The specific structure of each unit in the signal processing circuit is explained in detail below.
First, considering that the video signal voltage input to the signal amplification circuit is not a fixed amplitude and can float up and down due to external interference, and when the amplitude of the video signal with the alternating current waveform is biased to the upper limit or the lower limit, the amplitude of the video signal is easily beyond the range of the amplitude of the signal amplification circuit, the embodiment of the application provides that an effective external bias circuit is arranged between the signal input circuit and the signal amplification circuit to adjust the bias voltage of the first video signal to be matched with the central point voltage of the effective input voltage range of the signal amplification circuit, so that the video signal voltage is still within the effective range of the signal amplification circuit when the upper and lower floating ranges of the amplitude of the first video signal are larger.
As an optional implementation manner, the external bias circuit includes a first resistor, and the first resistor is used for adjusting a bias voltage of the first video signal, wherein a first terminal of the first resistor is connected to the voltage input source, and a second terminal of the first resistor is connected to the input terminal of the signal amplifying circuit.
Specifically, the resistance value of the first resistor is a preset resistance value, and is used for adjusting the bias voltage of the first video signal to a target amplitude value, wherein the target amplitude value is not less than the center point voltage of the effective input voltage range of the signal amplification circuit, and the difference value between the target amplitude value and the center point voltage is less than a preset threshold value.
Through the arrangement of the external bias circuit, the tolerance range of the signal amplification circuit to the quality of the input signal can be enlarged, the quality of the synchronous signal is improved, and the transmission performance of the system is improved.
Alternatively, the signal amplification circuit may employ an amplifier chip that enhances the video synchronization signal mainly by amplifying the video signal.
The signal separation circuit is used for separating a synchronous signal from the third video signal and outputting the synchronous signal to a target port; the signal output circuit is used for outputting a third video signal, wherein the third video signal is output in a direct current mode, and distortion-free transmission of the third video signal is guaranteed.
Optionally, in order to filter a dc component in the input signal and ensure that an external bias circuit arranged at a subsequent stage is not affected by the input dc component, in an embodiment of the present application, an input coupling circuit is arranged in the signal processing circuit, and is connected between the signal input circuit and the signal amplifying circuit, and the input coupling circuit is an ac coupling circuit.
Specifically, the input coupling circuit comprises: the first end of the fifth resistor is connected with the output end of the input circuit, the second end of the fifth resistor is connected with the first end of the second capacitor, the second end of the second capacitor is connected with the input end of the signal amplification circuit, the first end of the third capacitor is connected with the second end of the fifth resistor, the second end of the third capacitor is connected with the ground, the first end of the sixth resistor is connected with the second end of the fifth resistor, and the second end of the sixth resistor is connected with the ground.
Meanwhile, in order to improve the attenuation of the signal caused by the coupling capacitor, the signal processing circuit is further provided with an output coupling circuit which is connected between the signal amplifying circuit and the signal output circuit, and the output coupling circuit is a direct current coupling circuit.
Specifically, the output coupling circuit includes: the first end of the second resistor is connected with the output end of the signal amplifying circuit, the second end of the first capacitor is connected with the ground, the first end of the fourth resistor is connected with the second end of the second resistor, the second end of the fourth resistor is connected with the ground, the first end of the second capacitor is connected with the second end of the third resistor, and the second end of the second capacitor is connected with the ground.
It should be noted that, in the multi-stage signal transmission, the dc component generated by the dc coupling is filtered out at the input ac coupling part of the next stage, so as to ensure the validity of the synchronous output signal of the signal amplifying circuit.
The input coupling circuit and the output coupling circuit are added in front of and behind the signal amplification circuit, so that the problem of circuit loss of the synchronous signals input from the output ring of the front stage is solved, the signal transmission is more stable, the signal stability is higher, and the number of video systems in which the synchronous signals are cascaded is also obviously increased.
It should be noted that the signal processing circuit in the signal processing system in the embodiment of the present application is the same as the signal processing circuit in embodiment 1, and since the detailed description has been already made in embodiment 1, some details that are not shown in this embodiment may refer to embodiment 1, and are not described herein again.
Example 3
On the basis of the signal processing circuit provided in embodiment 1, an embodiment of the present application further provides a video processing apparatus, as shown in fig. 9, the apparatus includes: an input module 91, an output module 92, a control module 93, and a processing module 94, wherein:
the input module 91, the output module 92 and the control module 93 are respectively connected with the processing module 94; the control module 93 and/or the input module 91 are provided with a synchronization module, and the signal processing circuit in embodiment 1 is provided in the synchronization module.
Specifically, the signal processing circuit includes at least a signal input circuit, an external bias circuit, a signal amplification circuit, a signal separation circuit, and a signal output circuit,
a signal input circuit for inputting a first video signal;
the external bias circuit is connected with the input circuit and is used for adjusting the bias voltage of the first video signal to be matched with the central point voltage of the effective input voltage range of the signal amplification circuit to obtain a second video signal;
the signal amplification circuit is connected with the external bias circuit and is used for amplifying the second video signal to obtain a third video signal;
the signal separation circuit is connected with the signal amplification circuit and is used for separating the synchronous signal from the third video signal and outputting the synchronous signal;
and the signal output circuit is connected with the signal amplifying circuit and is used for outputting a third video signal.
It should be noted that the signal processing circuit in the video processing apparatus in the embodiment of the present application is the same as the signal processing circuit in embodiment 1, and as the detailed description has been already made in embodiment 1, some details that are not shown in this embodiment may refer to embodiment 1, and are not described herein again.
The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.
In the embodiments of the present application, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to the related descriptions of other embodiments.
In the embodiments provided in the present application, it should be understood that the disclosed technical content can be implemented in other manners. The above-described apparatus embodiments are merely illustrative, and for example, a division of a unit may be a logical division, and in actual implementation, there may be another division, for example, multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or may not be executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, units or modules, and may be in an electrical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit may be implemented in the form of hardware, or may also be implemented in the form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a separate product, may be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application, or portions or all or portions of the technical solutions that contribute to the prior art, may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a Read-only memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk, and various media capable of storing program codes.
The foregoing is only a preferred embodiment of the present application and it should be noted that those skilled in the art can make various improvements and modifications without departing from the principle of the present application, and these improvements and modifications should also be considered as the protection scope of the present application.
Claims (10)
1. A signal processing circuit, comprising:
a signal input circuit for inputting a first video signal;
the external bias circuit is connected with the input circuit and is used for adjusting the bias voltage of the first video signal to be matched with the voltage of the central point of the effective input voltage range of the signal amplification circuit to obtain a second video signal;
the signal amplifying circuit is connected with the external biasing circuit and used for amplifying the second video signal to obtain a third video signal;
the signal separation circuit is connected with the signal amplification circuit and is used for separating a synchronous signal from the third video signal and outputting the synchronous signal;
and the signal output circuit is connected with the signal amplifying circuit and is used for outputting the third video signal.
2. The circuit of claim 1, wherein the external bias circuit comprises:
and the first resistor is used for adjusting the bias voltage of the first video signal, wherein a first end of the first resistor is connected with a voltage input source, and a second end of the first resistor is connected with an input end of the signal amplifying circuit.
3. The circuit of claim 2,
the resistance value of the first resistor is a preset resistance value and is used for adjusting the bias voltage of the first video signal to a target amplitude value, wherein the target amplitude value is not smaller than the central point voltage of the effective input voltage range of the signal amplification circuit, and the difference value between the target amplitude value and the central point voltage is smaller than a preset threshold value.
4. The circuit of claim 1, further comprising:
and the output coupling circuit is connected between the signal amplifying circuit and the signal output circuit, wherein the output coupling circuit is a direct current coupling circuit.
5. The circuit of claim 4, wherein the output coupling circuit comprises:
the first end of the second resistor is connected with the output end of the signal amplification circuit, and the second end of the second resistor is connected with the first end of the third resistor;
the second end of the third resistor is connected with the input end of the signal output circuit;
a first capacitor, wherein a first end of the first capacitor is connected to the output end of the signal amplification circuit, and a second end of the first capacitor is connected to ground;
a fourth resistor, wherein a first end of the fourth resistor is connected to a second end of the second resistor, and a second end of the fourth resistor is connected to ground;
and a second capacitor, wherein a first end of the second capacitor is connected with a second end of the third resistor, and a second end of the second capacitor is connected with ground.
6. The circuit according to any one of claims 1 or 4, further comprising:
and the input coupling circuit is connected between the signal input circuit and the signal amplifying circuit, wherein the input coupling circuit is an alternating current coupling circuit.
7. The circuit of claim 6, wherein the input coupling circuit comprises:
a fifth resistor, wherein a first end of the fifth resistor is connected to the output end of the input circuit, and a second end of the fifth resistor is connected to the first end of the second capacitor;
the second end of the second capacitor is connected with the input end of the signal amplification circuit;
a third capacitor, wherein a first end of the third capacitor is connected to a second end of the fifth resistor, and a second end of the third capacitor is connected to ground;
and a first end of the sixth resistor is connected with the second end of the fifth resistor, and a second end of the sixth resistor is connected with the ground.
8. A genlock system, comprising: a signal processing circuit cascaded in multiple stages, wherein the signal processing circuit is the signal processing circuit of any one of claims 1 to 7.
9. The system of claim 8,
for any two adjacent signal processing circuits, the signal input circuit of the lower signal processing circuit is connected with the signal output circuit of the upper signal processing circuit.
10. A video processing apparatus, characterized by comprising: the device comprises an input module, an output module, a control module and a processing module, wherein the input module, the output module and the control module are respectively connected with the processing module; a synchronization module is arranged in the control module and/or the input module, and the signal processing circuit of any one of claims 1 to 7 is arranged in the synchronization module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222132312.0U CN218041488U (en) | 2022-08-12 | 2022-08-12 | Signal processing circuit, synchronous phase locking system and video processing equipment |
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| CN202222132312.0U CN218041488U (en) | 2022-08-12 | 2022-08-12 | Signal processing circuit, synchronous phase locking system and video processing equipment |
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