CN218003647U - Reliability test board and system - Google Patents
Reliability test board and system Download PDFInfo
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- CN218003647U CN218003647U CN202222190972.4U CN202222190972U CN218003647U CN 218003647 U CN218003647 U CN 218003647U CN 202222190972 U CN202222190972 U CN 202222190972U CN 218003647 U CN218003647 U CN 218003647U
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Abstract
The utility model provides a reliability testing board and system, include: the Socket module and the peripheral auxiliary test module; the Socket module and the peripheral auxiliary test module are connected through internal wiring; when the reliability test of the chip is carried out, the Socket module is located in the high-temperature test oven, the peripheral auxiliary test module is located outside the high-temperature test oven, the Socket module is used for placing the chip, and the peripheral auxiliary test module is connected with an upper computer to receive a control signal of the upper computer to carry out an aging test and an electrification test. The utility model discloses a survey test panel improves high temperature aging testing connection reliability and stability, improves the life who surveys test panel simultaneously greatly, practices thrift the test cost.
Description
Technical Field
The utility model relates to a test technical field indicates a reliability test board and system especially.
Background
Accelerated aging tests at high temperatures are required for reliability of chips (including on-board products) including: and (4) testing high-temperature erasing and reading functions. In the conventional testing method, a testing chip board and a peripheral auxiliary testing device (such as a MCU (microprogrammed control unit), a capacitor and a resistor) board are inserted in opposite directions through a patch board to separate a testing chip from the peripheral auxiliary testing device, so that the purpose of respectively placing the testing chip board and the peripheral auxiliary testing device board for testing under the conditions of high temperature and normal temperature is achieved. This structure has the following disadvantages:
1, because the inner test board and the outer test board are connected in a plug-in mode through the adapter plate, poor contact and unstable test states exist after the plug-in times are increased, and test result judgment is influenced.
2, after the plugging times are increased, poor contact is caused, so that the test board is scrapped in advance, resources are wasted, and the test cost is increased.
3, because the number of the inserted golden fingers of the adapter plate is limited (influenced by the structure and the position of the test oven), the requirement of simultaneously testing a large number of chips with multiple PIN PINs is difficult to meet.
4, because the inner test board and the outer test board are connected in a plug-in mode through the adapter plate, the high-frequency requirement of the test chip is influenced.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a reliability testing board and system can solve above-mentioned problem through this scheme.
The utility model provides a technical scheme as follows:
a reliability test board, comprising:
the Socket module and the peripheral auxiliary test module;
the Socket module and the peripheral auxiliary test module are connected through internal wiring;
when the reliability of the chip is tested, the Socket module is located in the high-temperature testing oven, the peripheral auxiliary testing module is located outside the high-temperature testing oven, the Socket module is used for placing the chip, and the peripheral auxiliary testing module is connected with an upper computer to receive a control signal of the upper computer to perform aging testing and live-line testing.
In some embodiments:
a peripheral auxiliary test device is placed in the peripheral auxiliary test module, and a peripheral power supply interface and a test interface are installed on one side of the peripheral auxiliary test module;
the peripheral power supply interface is used for connecting an external power supply and supplying power to the reliability test board; and the test interface is used for connecting the upper computer so as to drive the reliability test board to carry out reliability test on the chip.
In some embodiments, the peripheral auxiliary test device comprises an MCU, a capacitor and a resistor.
In some embodiments, further comprising: a heat insulation module;
the heat insulation module is arranged between the Socket module and the peripheral auxiliary test module.
In some embodiments:
the heat insulation module comprises a first heat insulation plate, a second heat insulation plate and a heat insulation groove; the heat insulation groove is arranged between the first heat insulation plate and the second heat insulation plate;
when the reliability of the chip is tested, the first heat insulation plate and the heat insulation groove are located in the high-temperature test oven, and the second heat insulation plate is located outside the high-temperature test oven.
In some embodiments:
high-temperature heat insulation cotton is placed in the heat insulation groove and used for isolating the temperature inside and outside the high-temperature test oven when the chip is subjected to high-temperature test.
A reliability test system comprises the reliability test board, a high-temperature test oven and an upper computer;
before a chip is subjected to reliability test, a Socket module of the reliability test board, a first heat insulation board and a heat insulation groove in the heat insulation module are placed in the high-temperature test oven; the peripheral auxiliary test module of the reliability test board and the second heat insulation board in the heat insulation module are placed outside the high-temperature test oven; and the peripheral auxiliary test module is connected with the upper computer.
In some embodiments, further comprising:
and the test board bracket is arranged inside and on the back surface of the high-temperature test oven and is used for placing the reliability test board.
In some embodiments, the back of the high temperature test oven is provided with a test board socket for insertion of the reliability test board.
In some embodiments, the test board socket mounts a test board fastening handle for securing the reliability test board.
Through the utility model provides a pair of reliability test panel and system can realize following technological effect at least:
1) The utility model discloses a survey test panel improves high temperature aging testing connection reliability and stability, improves the life who surveys test panel simultaneously greatly, practices thrift the test cost.
2) The utility model discloses a survey test panel and avoid having improved high temperature aging testing and connect reliability and stability through the keysets switching, avoided in the testing process because the erroneous judgement of contact problem to the test result.
3) The utility model discloses a survey test panel and avoid too much and lead to inside and outside bad contact who surveys test panel through the plug number of times of keysets, avoid surveying the test panel condition of scrapping in advance, improve the life who surveys test panel greatly, practice thrift the test cost.
4) The utility model discloses a survey test panel and avoid receiving the restriction of switching sheet metal finger quantity, can improve and survey test panel chip test quantity, improve efficiency of software testing.
5) The utility model discloses a survey test panel and avoided the influence of keysets and lead to testing chip's high frequency requirement can not satisfy the phenomenon.
Drawings
The above features, technical characteristics, advantages and implementation modes of a reliability test board will be further described in the following detailed description of preferred embodiments in a clearly understandable way by combining with the accompanying drawings.
Fig. 1 is a schematic diagram of an embodiment of a reliability testing board of the present invention;
FIG. 2 is a schematic diagram of a reliability test board of the prior art;
fig. 3 is a diagram illustrating simulation results of low and medium power supply voltages according to the present invention;
fig. 4 is a schematic diagram of simulation results of the medium and high power supply voltage of the present invention.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
For the sake of simplicity, only the parts relevant to the present invention are schematically shown in the drawings, and they do not represent the actual structure as a product. In addition, in order to make the drawings concise and understandable, components having the same structure or function in some of the drawings are only schematically illustrated or only labeled. In this document, "one" means not only "only one" but also a case of "more than one".
It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
In addition, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not intended to indicate or imply relative importance.
In order to more clearly illustrate embodiments of the present invention or technical solutions in the prior art, specific embodiments of the present invention will be described below with reference to the accompanying drawings. It is obvious that the drawings in the following description are only examples of the invention, and that for a person skilled in the art, other drawings and embodiments can be obtained from these drawings without inventive effort.
In one embodiment, the present invention provides a reliability test board, as shown in fig. 1, comprising:
The Socket module 1 and the peripheral auxiliary test module 2 are connected through internal wiring.
When the reliability test of the chip is carried out, the Socket module 1 is located in the high-temperature test oven, the peripheral auxiliary test module 2 is located outside the high-temperature test oven, the Socket module 1 is used for placing the chip, and the peripheral auxiliary test module 2 is connected with an upper computer to receive a control signal of the upper computer to carry out an aging test and an electrification test.
Specifically, the utility model discloses to place test chip's socket and peripheral auxiliary test device on same both sides of surveying the test panel, the centre is connected through the wiring, realizes the communication of test chip and peripheral device.
Specifically, in this embodiment, the reliability survey test panel is an organic whole and surveys test panel and pass through the utility model discloses an organic whole surveys test panel, can realize the aging testing demand of SPINOR product that high temperature, high frequency required steadily.
Additionally, through the utility model discloses a survey test panel integratively, can realize the electrified demand of testing of high temperature, low temperature, high humidity steadily.
Meanwhile, the read-write function aging test of electronic chips such as an EEPROM (electrically erasable programmable read-Only memory), a Flash and the like can be realized by burning programs with different test requirements on the MCU (micro control unit) of the peripheral test control device.
Exemplarily, socket module 1 and peripheral auxiliary test module 2 have been avoided because the quantity restriction of keysets leads to the problem that chip test quantity reduces after through the internal wiring connection, the utility model discloses an among the reliability test process of chip, through the utility model discloses a reliability test board can test all chips of placing on Socket module 1 simultaneously, has improved efficiency of software testing.
Meanwhile, due to the fact that the integrated board is adopted, switching through the adapter plate is avoided, connection reliability and stability of a high-temperature aging test are improved, and misjudgment of a test result due to contact problems in a test process is avoided.
The utility model discloses MCU can not support high temperature environment and the survey test panel scheme of a high reliability that designs when testing to chip high temperature reliability.
Since the reliability of the chip (including the on-board product) requires an accelerated aging test at high temperature: including high temperature erase and write, read functional tests. In order to solve the problem that peripheral auxiliary test device (devices such as MCU, electric capacity, resistance) can not high temperature for a long time, the utility model discloses when will testing chip and the separation of peripheral auxiliary test device, avoid traditional mode to the plugboard, adopt the design of test chip and peripheral auxiliary test device intergral template. The scheme greatly improves the contact reliability, simultaneously ensures the high-speed requirement of the test chip and ensures the high-temperature and high-reliability test.
In one embodiment, peripheral auxiliary test devices are placed on the peripheral auxiliary test module 2, and a peripheral power supply interface and a test interface are installed on one side of the peripheral auxiliary test module 2.
The peripheral power supply interface is used for connecting an external power supply and supplying power to the reliability test board; and the test interface is used for connecting the upper computer so as to drive the reliability test board to carry out reliability test on the chip.
In one embodiment, the peripheral auxiliary test device comprises an MCU, a capacitor and a resistor.
In one embodiment, as shown in fig. 2, further includes: a heat insulation module 3; the heat insulation module 3 is arranged between the Socket module 1 and the peripheral auxiliary test module 2.
Illustratively, a method for testing a chip in a high-temperature area and a peripheral auxiliary testing device (devices such as an MCU (microprogrammed control unit), a capacitor and a resistor) in a normal-temperature area is realized on an integral testing board by using a testing chip and the peripheral auxiliary testing device, so that the high-reliability aging test is completed.
Specifically, the utility model discloses heat insulating board and heat-proof slot design have been increased in the centre of surveying the test panel. Through the design of the two layers of heat insulation plates and the middle heat insulation groove 33 (high-temperature heat insulation cotton is placed in the heat insulation groove 33), the isolation inside and outside the high-temperature test oven 4 is effectively ensured, and the implementation of a high-temperature test scheme is successfully realized.
In one embodiment, as shown in fig. 3, the insulation module 3 includes a first insulation panel 31, a second insulation panel 32, and an insulation slot 33; the insulation groove 33 is disposed between the first insulation board 31 and the second insulation board 32.
When the reliability of the chip is tested, the first heat insulation plate 31 and the heat insulation groove 33 are located in the high temperature test oven 4, and the second heat insulation plate 32 is located outside the high temperature test oven 4.
In one embodiment, the heat insulation slot 33 is filled with high temperature insulation cotton for isolating the temperature inside and outside the high temperature test oven 4 when the chip is subjected to high temperature test.
In one embodiment, as shown in fig. 4, the present invention further provides a reliability testing system, which comprises the reliability testing board, the high temperature testing oven 4, and the upper computer 5.
Before a chip is subjected to a reliability test, a Socket module 1 of the reliability test board, a first heat insulation board 31 and a heat insulation groove 33 in a heat insulation module 3 are placed in the high-temperature test oven 4; the peripheral auxiliary test module 2 of the reliability test board and the second heat insulation board 32 in the heat insulation module 3 are placed outside the high-temperature test oven 4; the peripheral auxiliary test module 2 is connected with the upper computer 5.
In one embodiment, further comprising: and the test board bracket is arranged inside and on the back surface of the high-temperature test oven 4 and used for placing the reliability test board.
In one embodiment, the back of the high temperature test oven 4 is provided with a test board socket for the reliability test board to be inserted.
In one embodiment, the test board socket is mounted with a test board fastening handle for securing the reliability test board.
Exemplary, the utility model discloses mainly improve the reliability that high temperature aging testing connects, break through the restriction of switching sheet metal finger quantity, reach many PIN foot chip large quantity concurrent test's purpose:
1. the socket for placing the test chip and peripheral auxiliary test devices (MCU, capacitor, resistor and other devices) are placed on the left side and the right side of a whole test board (peripheral power supply and test USB interfaces are placed on one side of the peripheral auxiliary test devices), and the purpose of not using a patch board is achieved through wiring connection inside the board.
2. And designing a test board according to the structural size of the high-temperature test oven 4.
3. According to the groove size of the back of the high-temperature test oven 4, a middle heat insulation plate and a heat insulation groove 33 of the test board are designed (high-temperature heat insulation cotton is placed in the heat insulation groove 33).
4. Inside and on the back of the high temperature test oven 4, test board holders are mounted.
5. And a test board fastening handle is arranged at the test board socket on the back of the high-temperature test oven 4.
The test board is inserted into the high-temperature test oven 4 through the back, placed on the test board support, fixed through the oven back fastening handle, inside the high-temperature oven, the socket for placing the test chip on the test board, the peripheral auxiliary test device outside the high-temperature oven, and the heat insulation board and the heat insulation groove 33 (high-temperature heat insulation cotton is placed in the heat insulation groove 33) in the middle for internal and external heat insulation, so that the high-temperature aging test is realized.
The utility model discloses a survey test panel improves high temperature aging testing connection reliability and stability, improves the life who surveys test panel simultaneously greatly, practices thrift the test cost.
The utility model discloses a survey test panel and avoid having improved high temperature aging testing connection reliability and stability through the keysets switching, avoided in the testing process because the erroneous judgement of contact problem to the test result.
The utility model discloses a survey test panel and avoid too much and lead to inside and outside bad contact who surveys test panel through the plug number of times of keysets, avoid surveying the test panel condition of scrapping in advance, improve the life who surveys test panel greatly, practice thrift the test cost.
The utility model discloses a survey test panel and avoid receiving the restriction of adapter plate gold finger quantity, can improve and survey test panel chip test quantity, improve efficiency of software testing.
The utility model discloses a survey test panel and avoided the influence of keysets and lead to testing chip's high frequency requirement can not satisfy the phenomenon.
It will be apparent to those skilled in the art that, for convenience and simplicity of description, the above division of the program modules is merely used as an example, and in practical applications, the above distribution of functions may be performed by different program modules according to needs, that is, the internal structure of the apparatus may be divided into different program units or modules to perform all or part of the above-described functions. Each program module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one processing unit, and the integrated unit may be implemented in a form of hardware, or may be implemented in a form of software program unit. In addition, the specific names of the program modules are only used for distinguishing the program modules from one another, and are not used for limiting the protection scope of the application.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or recited in detail in a certain embodiment.
Those of ordinary skill in the art will appreciate that the various illustrative elements described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the technical solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiments provided in the present application, it should be understood that the disclosed system may be implemented in other ways. The above-described embodiments are merely illustrative, and the division of the modules or units is merely illustrative, and the actual implementation may have another division, and a plurality of units or components may be combined or integrated into another system, or some features may be omitted or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit may be implemented in the form of hardware, or may also be implemented in the form of a software functional unit.
It should be noted that the above embodiments can be freely combined as necessary. The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A reliability test board, comprising:
the Socket module and the peripheral auxiliary test module;
the Socket module and the peripheral auxiliary test module are connected through internal wiring;
when the reliability test of the chip is carried out, the Socket module is located in the high-temperature test oven, the peripheral auxiliary test module is located outside the high-temperature test oven, the Socket module is used for placing the chip, and the peripheral auxiliary test module is connected with an upper computer to receive a control signal of the upper computer to carry out an aging test and an electrification test.
2. The reliability test plate according to claim 1, wherein:
a peripheral auxiliary test device is placed in the peripheral auxiliary test module, and a peripheral power supply interface and a test interface are installed on one side of the peripheral auxiliary test module;
the peripheral power supply interface is used for connecting an external power supply and supplying power to the reliability test board; and the test interface is used for connecting the upper computer so as to drive the reliability test board to carry out reliability test on the chip.
3. The reliability test board according to claim 2, wherein the peripheral auxiliary test devices comprise MCU, capacitor, resistor.
4. The reliability test board according to any one of claims 1 to 3, further comprising: a heat insulation module;
the heat insulation module is arranged between the Socket module and the peripheral auxiliary test module.
5. The reliability test plate of claim 4, wherein:
the heat insulation module comprises a first heat insulation plate, a second heat insulation plate and a heat insulation groove; the heat insulation groove is arranged between the first heat insulation plate and the second heat insulation plate;
when the reliability of the chip is tested, the first heat insulation plate and the heat insulation groove are located in the high-temperature test oven, and the second heat insulation plate is located outside the high-temperature test oven.
6. The reliability test plate according to claim 5, wherein:
high-temperature heat insulation cotton is placed in the heat insulation groove and used for isolating the temperature inside and outside the high-temperature test oven when the chip is subjected to high-temperature test.
7. A reliability testing system, comprising the reliability testing board according to any one of claims 1 to 6, a high temperature testing oven, an upper computer;
before a chip is subjected to reliability test, a Socket module of the reliability test board, a first heat insulation board and a heat insulation groove in the heat insulation module are placed in the high-temperature test oven; the peripheral auxiliary test module of the reliability test board and the second heat insulation board in the heat insulation module are placed outside the high-temperature test oven; and the peripheral auxiliary test module is connected with the upper computer.
8. The reliability testing system of claim 7, further comprising:
and the test board bracket is arranged inside and on the back surface of the high-temperature test oven and is used for placing the reliability test board.
9. The reliability testing system of claim 7, wherein the back of said high temperature testing oven is provided with a testing board socket for the insertion of said reliability testing board.
10. The reliability testing system of claim 8, wherein said test board socket is mounted with a test board fastening handle for fixing said reliability test board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222190972.4U CN218003647U (en) | 2022-08-19 | 2022-08-19 | Reliability test board and system |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202222190972.4U CN218003647U (en) | 2022-08-19 | 2022-08-19 | Reliability test board and system |
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| CN218003647U true CN218003647U (en) | 2022-12-09 |
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| CN202222190972.4U Active CN218003647U (en) | 2022-08-19 | 2022-08-19 | Reliability test board and system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116699375A (en) * | 2023-07-28 | 2023-09-05 | 中科亿海微电子科技（苏州）有限公司 | High-temperature testing method and device for FPGA chip |
-
2022
- 2022-08-19 CN CN202222190972.4U patent/CN218003647U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116699375A (en) * | 2023-07-28 | 2023-09-05 | 中科亿海微电子科技（苏州）有限公司 | High-temperature testing method and device for FPGA chip |
| CN116699375B (en) * | 2023-07-28 | 2024-01-19 | 中科亿海微电子科技（苏州）有限公司 | High-temperature testing method and device for FPGA chip |
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