CN217982843U

CN217982843U - System for accurate injection voltage is undulant in EMMC pressure test

Info

Publication number: CN217982843U
Application number: CN202221046204.5U
Authority: CN
Inventors: 孙成思; 孙日欣; 何阳; 李新春
Original assignee: Biwin Storage Technology Co Ltd
Current assignee: Biwin Storage Technology Co Ltd
Priority date: 2022-04-29
Filing date: 2022-04-29
Publication date: 2022-12-06
Anticipated expiration: 2032-04-29

Abstract

The utility model discloses a system of accurate injection voltage fluctuation in eMMC pressure test, including main control chip, first PMIC, second PMIC and eMMC chip are connected to the main control chip electricity, first PMIC and second PMIC electricity are connected the eMMC chip and are given the eMMC chip with output current. It can realize making accurate voltage fluctuation through setting up first PMIC and second PMIC, not only can simulate the condition that the voltage falls the electricity in reality, also can simulate the influence that voltage fluctuation appears the work of eMMC chip.

Description

System for accurate injection voltage is undulant in EMMC pressure test

Technical Field

The utility model relates to a chip test technical field, concretely relates to accurate system of pouring into voltage fluctuation in eMMC pressure test.

Background

The conventional eMMC chip has two paths of power supply, wherein one path is 3.3V VCC which supplies power for a Flash memory (Nand Flash), and the other path is 1.8V VCCQ which supplies power for a controller. eMMC acts as a passive semiconductor chip, whose normal and stable supply is theoretically a prerequisite for its proper operation. However, in the actual use process, due to the influence of the stability and environment of the power supply, the abnormal fluctuation and the drop of the power supply voltage are inevitable. This requires that eMMC still can guarantee the security of user data and the normal operation of Firmware (Firmware) in the power supply abnormal scene. This scenario presents a major challenge to the error handling capability and robustness of firmware (firmware).

For the situation, a mature testing method is adopted at present, and voltage drop and recovery are accurately achieved in an eMMC scene testing process by introducing a voltage control circuit (GPIO signal control). For example, it can be realized that VCC (for power supply to Nand) falls from 3.3V to 0V, and VCCQ falls from 1.8V to 0V, which is equivalent to inserting an abnormal power failure.

However, the conventional method can only switch on and off the voltage as shown in fig. 1, and cannot support the voltage fluctuation as shown in fig. 2, for example, VCC fluctuates at a middle value between 3.3V and 0V. However, in the situation of voltage fluctuation, especially for the read-write process, the operation of NAND Flash is involved, and the fluctuation of VCC causes many hidden troubles of data loss, so the test of the situation is quite necessary.

SUMMERY OF THE UTILITY MODEL

The utility model discloses the technical problem that will solve is:

in order to solve the technical problem, the utility model discloses a technical scheme be: the utility model provides a system of accurate injection voltage fluctuation in eMMC pressure test, includes main control chip, first PMIC, second PMIC and eMMC chip are connected to the main control chip electricity, first PMIC and second PMIC electricity are connected the eMMC chip with output current for the eMMC chip.

Further, the main control chip is electrically connected with the first PMIC and the second PMIC through an IIC interface.

Further, the power supply module is electrically connected with the main control chip, the first PMIC and the second PMIC.

Further, still include memory chip, memory chip electricity connects the main control chip.

Further, the model of the first PMIC is specifically TPS628610.

Further, the model of the second PMIC is specifically TPS63811.

Further, the main control chip and the eMMC are respectively located on the two PCB boards.

Further, the eMMC is fixed on the PCB in a mode of inserting a socket welded on the PCB.

The beneficial effects of the utility model reside in that: through setting up first PMIC and second PMIC, can realize making accurate voltage fluctuation, not only can simulate the condition that the voltage falls the electricity in reality, also can simulate the influence that voltage fluctuation appears to the work of eMMC chip.

Drawings

FIG. 1 is a waveform diagram of a voltage switch that can be made by the prior art;

FIG. 2 is a waveform diagram of voltage fluctuations that cannot be made by the prior art;

fig. 3 is a schematic structural diagram of a system for accurately injecting voltage fluctuation in an eMMC pressure test according to the present invention;

fig. 4 is a flowchart illustrating the operation of a system for accurately injecting voltage fluctuations during eMMC pressure testing in accordance with the present invention;

fig. 5 is a waveform diagram of VCCQ voltage fluctuation according to an embodiment of the present invention;

fig. 6 is a waveform diagram of VCC voltage fluctuation according to an embodiment of the present invention.

Detailed Description

In order to explain the technical content, the objects and the effects of the present invention in detail, the following description is made with reference to the accompanying drawings in combination with the embodiments.

Please refer to fig. 3, an embodiment of the present invention provides a system for accurately measuring injection voltage fluctuation in an eMMC pressure test, including a main control chip, a first PMIC, a second PMIC and an eMMC chip, wherein the main control chip is electrically connected to the first PMIC, the second PMIC and the eMMC chip, and the first PMIC and the second PMIC are electrically connected to the eMMC chip to output current to the eMMC chip.

As can be seen from the above description, the utility model has the advantages that: through setting up first PMIC and second PMIC, can realize making accurate voltage fluctuation, not only can simulate the condition that the voltage falls the electricity in reality, also can simulate the influence that voltage fluctuation appears to the work of eMMC chip.

As can be seen from the above description, the main control chip connects the first PMIC and the second PMIC through the IIC interface, and can communicate with the first PMIC and the second PMIC through fewer channels.

From the above description, the power module can supply power to the main control chip, the first PMIC and the second PMIC.

From the above description, the memory chip is used for storing the test program and the test case, and can store more test cases and more complex test programs.

Further, the model of the first PMIC is specifically TPS628610.

As can be seen from the above description, the TPS628610 output voltage ranges from 0.4V to 1.9875V, the step is 0.0125V, and the slope of the voltage variation can be adjusted from 10mV/us to 0.1 mV/us.

Further, the model of the second PMIC is specifically TPS63811.

As can be seen from the above description, the TPS63811 has an input voltage range of 2.2V-5.5V, an output voltage range of 1.8V-5.2V, and a step size of 0.025V, and the slope of the voltage variation can be adjusted between 1.0V/ms and 10.0V/ms.

As can be seen from the above description, the main control chip and the eMMC are respectively located on independent PCBs, and can be independently replaced and maintained, thereby facilitating subsequent maintenance.

Further, the eMMC is fixed on the PCB by inserting a socket soldered on the PCB.

As can be seen from the above description, the eMMC chip is connected with the PCB board through the socket, and different eMMC chips can be conveniently replaced, so that the test carrier can be repeatedly used.

The utility model discloses a system of accurate injection voltage fluctuation in eMMC pressure test, it is used for testing the eMMC chip, thereby makes the stability of accurate voltage fluctuation test eMMC chip under the fluctuating condition of voltage work in the test process of eMMC chip.

Example one

Referring to fig. 3, a system for accurately injecting voltage fluctuation during an eMMC pressure test according to an embodiment of the present invention includes a main control chip, an IIC interface, a first PMIC (Power Management IC), a second PMIC, and an eMMC chip, where the main control chip is in communication connection with the first PMIC and the second PMIC through the IIC interface, and the main control chip is electrically connected to the eMMC chip.

Therefore, the master control chip controls the work of the eMMC and simultaneously controls the output voltage of the first PMIC and the second PMIC through the IIC bus, so that the voltage of the input eMMC chip is accurately controlled, and the voltage fluctuation simulation shown in the figure 3 is realized.

Example two

Referring to fig. 3, the embodiment is further limited based on the first embodiment and includes a development board and an eMMC test carrier, where the development board includes a first signal transmission interface, a first power interface, a power module, a main control chip, an IIC interface, a data transmission circuit, and a memory chip, and the eMMC test carrier includes a second power interface, a second signal transmission interface, a first PMIC, a second PMIC, and an eMMC chip to be tested.

The main control chip is electrically connected with the first signal transmission interface, the power module, the memory chip, the IIC interface and the data transmission circuit respectively, the data transmission circuit is electrically connected with an external upper computer to realize communication between the main control chip and the upper computer, the first power interface is electrically connected with the second power interface, the second power interface is electrically connected with the first PMIC and the second PMIC respectively, the first PMIC and the second PMIC are electrically connected with the eMMC chip, so that the first PMIC and the second PMIC get power from the power module and output set voltage to the eMMC chip, the first PMIC and the second PMIC are electrically connected with the IIC bus, the main control chip transmits signals through the IIC interface to control output of the first PMIC and the second PMIC, the first signal transmission interface is electrically connected with the second signal transmission interface, the second signal transmission interface is electrically connected with the eMMC chip, the first signal transmission interface and the second signal transmission interface comprise a plurality of communication lines such as CMD, CLK, DAT0-7, string, RST and the like, the main control signal transmission interface transmits signals and data transmission signals to the eMMC chip to control the work of the eMMC chip.

In this embodiment, master control board and eMMC test carrier all are socket PCB (PCB socket) of independent design to conveniently change the test procedure of carrying on in the memory chip in the test, and if there is the part damage, it is also more convenient to maintain and change, and conveniently changes the test to the eMMC chip.

In this embodiment, the first PMIC is specifically TPS628610, the output voltage range is 0.4V-1.9875V, the step is 0.0125V, and the slope of the voltage variation can be adjusted between 10mV/us and 0.1 mV/us; the second PMIC is specifically TPS63811 with an input voltage range of 2.2V-5.5V, an output voltage range of 1.8V-5.2V, and a step of 0.025V, wherein the slope of the voltage variation can be adjusted between 1.0V/ms and 10.0V/ms.

During testing, please refer to fig. 4:

firstly, a pre-written test program is burnt by an upper computer, only a memory chip is put into an eMMC chip to be tested, the eMMC chip to be tested is put into a slot on an eMMC test carrier, a first power interface is electrically connected with a second power interface, a first signal transmission interface is electrically connected with a second signal transmission interface, and an IIC bus is electrically connected with a first PMIC and a second PMIC;

then, a power supply of the development board is started, a test program is loaded, according to the test program, the main control chip outputs IIC signals to the first PMIC and the second PMIC, the first PMIC outputs 1.8V voltage, the second PMIC outputs 3.3V voltage, then the main control chip sends a command to the eMMC to initialize the eMMC, after the initialization is completed, the eMMC can be tested, and logs (logs) generated in the process can be transmitted to the upper computer and displayed in the upper computer;

after the tester sees the initialization operation from the upper computer, the tester can input an instruction through the upper computer, run the test program, and start to execute the test according to the corresponding test case in the test program;

the main control board sends a control command and read-write data to the eMMC according to the test case, and controls the output voltage of the first PMIC and the output voltage of the second PMIC to fluctuate through IIC communication;

the test of the eMMC can be completed under the condition of voltage fluctuation, and a test result and log are transmitted to an upper computer so that a tester can check the test result and the log.

The test procedure in practice produces in particular voltage fluctuations as in fig. 5-6.

To sum up, the utility model provides a pair of accurate system of injecting voltage fluctuation in eMMC pressure test, it is through setting up first PMIC and second PMIC, can realize making accurate voltage fluctuation, not only can simulate the condition that voltage falls the electricity in the reality, also can simulate the influence that voltage fluctuation appears the work of eMMC chip.

The above mentioned is only the embodiment of the present invention, and not the limitation of the patent scope of the present invention, all the equivalent transformations made by the contents of the specification and the drawings, or the direct or indirect application in the related technical field, are included in the patent protection scope of the present invention.

Claims

1. A system for accurately injecting voltage fluctuation in an eMMC pressure test is characterized in that: including main control chip, first PMIC, second PMIC and eMMC chip are connected to the main control chip electricity, first PMIC and second PMIC electricity are connected the eMMC chip and are given the eMMC chip with output current.

2. The system of claim 1, wherein the system is configured to refine injection voltage fluctuations during an eMMC pressure test, and wherein: the main control chip is electrically connected with the first PMIC and the second PMIC through an IIC interface.

3. The system of claim 1, for precision injection of voltage fluctuations in an eMMC pressure test, wherein: the power supply module is electrically connected with the main control chip, the first PMIC and the second PMIC.

4. The system of claim 1, wherein the system is configured to refine injection voltage fluctuations during an eMMC pressure test, and wherein: the storage chip is electrically connected with the main control chip.

5. The system of claim 1, wherein the system is configured to refine injection voltage fluctuations during an eMMC pressure test, and wherein: the model of the first PMIC is TPS628610.

6. The system of claim 1, wherein the system is configured to refine injection voltage fluctuations during an eMMC pressure test, and wherein: the model of the second PMIC is TPS63811.

7. The system of claim 1, wherein the system is configured to refine injection voltage fluctuations during an eMMC pressure test, and wherein: the main control chip and the eMMC are respectively positioned on the two PCB boards.

8. The system of claim 7, wherein the injection voltage fluctuation is refined in an eMMC pressure test by: the eMMC is fixed on the PCB in a mode of inserting and welding a socket on the PCB.