CN211905590U - Integrated circuit testing device - Google Patents
Integrated circuit testing device Download PDFInfo
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- CN211905590U CN211905590U CN202020298026.XU CN202020298026U CN211905590U CN 211905590 U CN211905590 U CN 211905590U CN 202020298026 U CN202020298026 U CN 202020298026U CN 211905590 U CN211905590 U CN 211905590U
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Abstract
The utility model provides an integrated circuit testing device, which comprises a control module, a power management module, a testing board, a special module and a general module, wherein the control module is respectively connected with the power management module, the special module and the general module and is used for controlling each module to execute corresponding operation according to corresponding instructions; the power management module is respectively connected with the control module and the test board and is used for supplying power to the special module; the test board is connected with the power management module and the special module and is different test boards special for different test procedures; the special module is respectively connected with the control module, the test board and the general module and is used for configuring necessary peripheral circuits of the chip to be tested; the universal module is respectively connected with the special module and the control module and is used for configuring a universal circuit of the chip to be tested. The testing device does not need to customize different special testing circuit boards, is low in design cost, does not need to frequently plug or weld a chip to be tested, and reduces the risk of pin damage.
Description
Technical Field
The utility model relates to an electronic circuit field, concretely relates to integrated circuit testing arrangement.
Background
With the development of electronic technology, the integration degree of electronic products is higher and higher, the structures are finer and finer, the processes are more and more, and the manufacturing process is more and more complex, so that the defects generated in the manufacturing process can be enlarged. For a qualified electronic product, not only higher performance indexes but also higher stability are required, and the stability of the electronic product depends on factors such as the reasonability of design, the performance of components, the whole machine manufacturing process and the like. At present, high-temperature aging technology is generally adopted at home and abroad to improve the stability and reliability of electronic products, defects of components and parts, hidden dangers existing in the production processes of welding, assembling and the like can be exposed in advance through high-temperature aging, and the products leaving factory can be guaranteed to withstand the time.
After the integrated circuit chip is packaged, multiple FT (Final Test) tests are usually performed before mass production to ensure the outgoing quality of the chip, and for each Test procedure of FT, a special Test circuit board, such as an burn-in board, a logic Test board, a memory Test board, and the like, is required. In addition, the chip is a small-sized product, and frequent plugging or soldering replacement brings a risk of damaging pins for a multi-pin packaged chip like QFP (Quad Flat package).
SUMMERY OF THE UTILITY MODEL
To above-mentioned prior art's shortcoming or not enough, the utility model provides an integrated circuit testing arrangement, it need not customize different special test circuit board, and design cost is low, and need not frequent plug or welding and await measuring the chip, reduces pin damage risk.
The utility model discloses a following technical scheme realizes:
an integrated circuit testing device comprises a control module, a power management module, a testing board, a special module and a general module, wherein,
the control module is respectively connected with the power management module, the special module and the general module and is used for controlling each module to execute corresponding operation according to corresponding instructions;
the power management module is respectively connected with the control module and the test board and is used for supplying power to the special module;
the test board is connected with the power management module and the special module and is different test boards special for different test procedures;
the special module is respectively connected with the control module, the test board and the general module and is used for configuring necessary peripheral circuits of the chip to be tested;
the universal module is respectively connected with the special module and the control module and is used for configuring a universal circuit of the chip to be tested.
Specifically, the test board comprises a plurality of channels, each channel comprises a plurality of special stations, and the special stations are used for placing the special modules.
Specifically, the special modules used in the same test procedure are universal, and the special modules used in different test procedures are not universal.
Specifically, the test board is an aging test board.
Specifically, the chips to be tested corresponding to the same channel are the same, and the chips to be tested corresponding to different channels are different or the same.
Specifically, the control module monitors an IO signal of the chip to be tested and a power supply voltage of the dedicated module.
Specifically, the test board is a chip memory test board.
Specifically, the control module controls the test voltage output of the power management module and the flash operation of the chip to be tested.
Specifically, the testing device further comprises a memory connected with the control module, and the memory is used for storing the testing information of the chip to be tested.
The utility model provides an integrated circuit testing arrangement will have special test panel now to the awaiting measuring chip of different models, with the necessary circuit separation among them, form the dedicated special module of different models, be applicable to the general test of multiple different encapsulation products, reuse rate is high, need not to customize dedicated ageing-resistant plate according to the product of different encapsulation types again, save the cost; and the universal circuits of different FT test procedures are configured in the universal module, so that the plugging and pulling frequency of a chip or the welding frequency is reduced, and the risk of pin damage is reduced. Meanwhile, multi-chip testing is simultaneously carried out through multiple channels and multiple special stations, so that large-batch testing is realized, testing time is shortened, and testing period is shortened.
Drawings
Fig. 1 is a circuit module structure diagram of the integrated circuit testing device provided by the present invention.
Fig. 2 is a planar circuit structure diagram of the test board provided by the present invention.
Fig. 3 is a circuit module structure diagram of the integrated circuit testing apparatus provided in the first and second embodiments.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Thus, the following detailed description of the embodiments of the present invention, presented in the accompanying drawings, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. Based on the embodiment of the present invention, all other embodiments obtained by the person skilled in the art without creative work belong to the protection scope of the present invention.
The utility model provides an integrated circuit testing device, as shown in figure 1, which comprises a control module, a power management module, a testing board, a special module and a general module, wherein,
the control module is respectively connected with the power management module, the special module and the general module and is used for controlling each module to execute corresponding operation according to corresponding instructions;
the power management module is respectively connected with the control module and the test board and is used for supplying power to the special module;
the test board is connected with the power management module and the special module and is different test boards special for different test procedures;
the special module is respectively connected with the control module, the test board and the general module and is used for configuring necessary peripheral circuits of the chip to be tested;
the universal module is respectively connected with the special module and the control module and is used for configuring a universal circuit of the chip to be tested.
The test board is a special board for functional test, and different test boards are used in different test procedures, such as a test board for burn-in, a test board for memory, and the like. The test board comprises a plurality of channels, each channel comprises a plurality of special stations, and the special stations are used for placing the special modules. Referring to fig. 2, it shows N channels on the test board and a plurality of dedicated stations on each channel, where the chips to be tested corresponding to different channels are different or the same, and the chips to be tested corresponding to the same channel are the same or different.
The special module is a circuit module special for a certain test procedure in the FT, comprises peripheral circuits necessary for executing test work in the procedure, is universal for the same test procedure, and is not universal for different test procedures. For example, the dedicated module for burn-in test and the dedicated module for memory test are not common, and their circuit structures are different according to different test requirements. In addition, in the same testing procedure, the corresponding special modules may be different according to different types of chips to be tested. So, with the dedicated circuit that different models await measuring chip institute is dedicated from surveying test panel separation, be equipped with different special module by same survey test panel and test, and needn't test the chip and customize different survey test panel to different models, reduced design cost, when special module trouble simultaneously, needn't maintain the monoblock and survey test panel, reduced the fault maintenance cost, in addition, special module's trouble does not influence whole test work, has promoted test speed indirectly.
The universal module is a circuit module universal for multiple testing procedures in the FT, and includes a universal circuit for executing different testing operations, specifically, the universal modules used by chips to be tested in the same Package type are the same, that is, the chips to be tested in the same Package type are packaged, the universal module is universal, for example, the chips to be tested in QFN (Quad Flat No-lead Package) Package can be universal with the same type of universal module, the chips to be tested in QFP (Quad Flat Package) Package can be universal with another type of universal module, but cannot be universal with the universal module universal for QFN Package. Therefore, after the chip to be tested completes one testing procedure, the universal module and the chip to be tested carried on the universal module can be integrally moved to a special testing plate of the next testing procedure, the plugging or welding frequency of the chip to be tested is reduced, and the pin damage risk is reduced.
The first embodiment is as follows:
in this embodiment, as an example of the test board, referring to fig. 2 and 3, the test board is a burn-in test board, the specific module on the test board is dedicated for burn-in, the necessary circuits for burn-in are configured for carrying the general modules, and the general modules carrying the chips to be tested are configured with the general circuits for different test procedures. In this embodiment, the chips to be tested corresponding to the same channel on the test board are the same, and the chips to be tested corresponding to different channels are the same, or the chips to be tested corresponding to the same channel are the same, and the chips to be tested corresponding to different channels are different.
For example, in the plurality of dedicated stations on the first channel, the chip to be tested placed in each dedicated station is the same, in the plurality of dedicated stations on the other channels, the chip to be tested placed in each dedicated station is the same, and the chip to be tested on the first channel is the same as the chip to be tested on the other channels. The chips to be tested in different channels and different special stations in the example are the same, so that the voltage supplied to each channel by the power management module is consistent, and the example can be applied to high-temperature aging test work of large-scale chips to be tested in the same type.
For another example, in the plurality of dedicated stations on the first channel, the chip to be tested placed in each dedicated station is the same, and in the plurality of dedicated stations on other channels, the chip to be tested placed in each dedicated station is the same, and the chip to be tested on the first channel is different from the chip to be tested on other channels, or the chip to be tested on the first channel is different from the chip to be tested on some other channels and is different from the chip to be tested on other channels. In the example, the chips to be tested in the same channel are the same, and the chips to be tested in different channels are different, so that the voltages supplied to the channels by the power management module are different, the channels with different voltage requirements need to be further subjected to voltage management, and the example can be applied to high-temperature aging test work of the chips to be tested in large scale and different models.
The control module monitors IO signals of the chips to be tested, the power management module supplies power to excite pins of the chips to be tested on each special station of each channel through the special module, the control module captures the IO signals, and whether the working state of the chips is normal or not is judged according to results.
When the control module judges according to the chip pin reaction result, the working state of the chip to be tested is possibly abnormal due to the fault of the power management module or the special module. Therefore, the control module further monitors the power supply voltage of the special module, so that the chip problem and other circuit problems are accurately distinguished, and the accuracy of chip testing is improved.
Example two:
as a further example of the first embodiment, referring to fig. 2 and fig. 3, after the chip to be tested in the first embodiment finishes the burn-in test, the universal module and the chip to be tested mounted thereon are integrally moved to the special module of the test board in the present embodiment, the test board in the present embodiment is a memory test board, the special module on the test board is dedicated for memory test, and a circuit necessary for memory test is configured to mount the universal module. Different from the first embodiment, the first embodiment does not make specific requirements on the types of the chips to be tested corresponding to different channels or the same channel.
In this embodiment, the control module controls the test voltage output of the power management module, and according to the test requirement of the FT memory, the chip memory needs to ensure the reliability thereof in the unstable state of the supply voltage, so that the test voltage is in a fluctuating state, and is not limited to continuous rising or falling, cliff-type falling, power-off connection, and the like. The test voltage of the chip memory is in a fluctuation state, and the fluctuation range of the test voltage covers the working voltages of chips of different models, so that the voltage management module does not need to output different test voltages pertinently due to different models of chips to be tested.
And during the voltage output period of the fluctuation state, the control module controls the flash module of the chip to be tested to respectively carry out erasing/writing/reading operations, and after each test, the comparison result is used for comparing whether the test data is consistent with the source data. The testing frequency can be freely set, the testing is automatically stopped after the set value is reached, the control module counts the testing result, and the reliability of the flash module of the chip to be tested in the testing mode is verified.
The utility model discloses in the testing arrangement that above-mentioned embodiment provided, still include the memory of being connected with control module, this memory is used for the test information of the storage examination chip that awaits measuring, include and be not limited to the examination chip ageing time that awaits measuring, IO signal, flash read/erase/write in program comparison key parameter such as result, make things convenient for the tester to look over, and be favorable to the later stage to trail.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. The integrated circuit testing device is characterized by comprising a control module, a power management module, a testing board, a special module and a general module, wherein,
the control module is respectively connected with the power management module, the special module and the general module and is used for controlling each module to execute corresponding operation according to corresponding instructions;
the power management module is respectively connected with the control module and the test board and is used for supplying power to the special module;
the test board is connected with the power management module and the special module and is different test boards special for different test procedures;
the special module is respectively connected with the control module, the test board and the general module and is used for configuring necessary peripheral circuits of the chip to be tested;
the universal module is respectively connected with the special module and the control module and is used for configuring a universal circuit of the chip to be tested.
2. The test apparatus of claim 1, wherein the test board comprises a plurality of channels, each channel comprising a plurality of dedicated stations for receiving the dedicated modules.
3. The test apparatus of claim 1, wherein the dedicated modules for the same test procedure are common, and the dedicated modules for different test procedures are not common.
4. A test device according to any one of claims 1 to 3, wherein the test board is a burn-in board.
5. The testing apparatus of claim 4, wherein the chips to be tested corresponding to the same channel are the same, and the chips to be tested corresponding to different channels are different or the same.
6. The test apparatus of claim 4, wherein the control module monitors IO signals of the chip under test and a supply voltage of the dedicated module.
7. A test device as claimed in any one of claims 1 to 3, wherein the test board is a chip memory test board.
8. The test apparatus of claim 7, wherein the control module controls a test voltage output of the power management module and a flash operation of the chip to be tested.
9. The test apparatus of claim 1, further comprising a memory coupled to the control module, the memory for storing test information for the chip under test.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020298026.XU CN211905590U (en) | 2020-03-11 | 2020-03-11 | Integrated circuit testing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020298026.XU CN211905590U (en) | 2020-03-11 | 2020-03-11 | Integrated circuit testing device |
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| Publication Number | Publication Date |
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| CN211905590U true CN211905590U (en) | 2020-11-10 |
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| CN202020298026.XU Active CN211905590U (en) | 2020-03-11 | 2020-03-11 | Integrated circuit testing device |
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