CN217847119U - Intelligent core board and equipment - Google Patents

Abstract

The utility model relates to an intelligent core board and equipment, wherein the core board comprises a processor, a memory module, a power management module, a reset module, a wireless network module and four board-to-board connectors which are symmetrically arranged; the board-to-board connector is connected with the bottom board interface of the core board, and pins of the board-to-board connector are arranged in a preset mode; the four symmetrically arranged board-to-board connectors are respectively positioned at four end points of the same plane of the core board; each board-to-board connector comprises 80 pins; the pin pitch of each board-to-board connector is 0.5mm; equipment includes the equipment bottom plate, is equipped with as above on the equipment bottom plate intelligent core plate. The utility model discloses a board sets up according to predetermineeing the pin mode of arranging to the board connector, through pin interval between the different speed interfaces of rational arrangement, same function interface unified place draw forth, increase prevent that reverse plug protection, CPU pin are whole draws forth the method such as, let the user design out different products fast simply, reduce the design cost and reduce the development degree of difficulty.

Description

Intelligent core board and equipment

Technical Field

The utility model relates to a nuclear core plate technical field especially relates to an intelligence nuclear core plate and equipment.

Background

The core board is an electronic main board which packages and encapsulates the core functions of the MINI PC. Most of core boards integrate a CPU, a storage device and pins, and are connected with a matched bottom board through the pins so as to realize a system chip in a certain field. People often refer to such a set of system as a single chip microcomputer or an embedded development platform. Because the core board integrates the general function of the core, the universal base board has the universality that the core board can customize various different base boards, and the development efficiency of the single chip microcomputer is greatly improved. Because the core board is separated as an independent module, the development difficulty is reduced, and the stability and maintainability of the system are improved.

When the traditional core board is used for base board development, many unreasonable or defective places can cause problems of difficult PCB wiring, crosstalk between interfaces with different rates, burning out of the core board when the direction is wrong and the like, and the development difficulty and the cost can be increased.

SUMMERY OF THE UTILITY MODEL

Not enough to prior art, the utility model provides an intelligence nuclear core plate and equipment to the problem of proposing in the above-mentioned background art has been solved.

On one hand, the utility model provides an intelligent core board, which comprises a processor (1), a memory module (2), a memory module (3), a power management module (4), a reset module (5), a wireless network module (6) and four board-to-board connectors which are symmetrically arranged; the processor (1) is respectively connected with the memory module (2), the storage module (3), the power management module (4), the reset module (5) and the wireless network module (6); the board-to-board connector is connected with the bottom board interface of the core board, and pins of the board-to-board connector are arranged in a preset mode; the four symmetrically arranged board-to-board connectors are respectively positioned at four end points of the same plane of the core board; each board-to-board connector comprises 80 pins; the pin pitch of each board-to-board connector is 0.5mm.

Further, the processor (1) is a core-relaxation D9 series processor.

Furthermore, the four symmetrically arranged board-to-board connectors are divided into a first board-to-board connector (101), a second board-to-board connector (102), a third board-to-board connector (103) and a fourth board-to-board connector (104);

the first board-to-board connector (101) is provided with a plurality of GPIO interfaces, RGMII interfaces, UART interfaces, CANFD interfaces, SD card interfaces, I2C interfaces, OSPI interfaces and JTAG interfaces; the GPIO interfaces, the RGMII interface, the UART interface, the CANFD interface, the SD card interface, the I2C interface, the OSPI interface and the JTAG interface are all electrically connected with the processor (1);

the second board-to-board connector (102) is provided with a plurality of OSPI interfaces, SD card interfaces, DSI interfaces, CSI interfaces and RGMII interfaces; the OSPI interfaces, the SD card interface, the DSI interface, the CSI interface and the RGMII interface are all electrically connected with the processor (1);

the third board-to-board connector (103) is provided with a plurality of USB interfaces, PCIE interfaces, GPIO interfaces, UART interfaces, I2S interfaces and ADC interfaces; the USB interfaces, the PCIE interface, the GPIO interface, the UART interface, the I2S interface and the ADC interface are electrically connected with the processor (1);

the fourth board-to-board connector (104) is provided with a plurality of I2C interfaces, GPIO interfaces, UART interfaces, LVDS interfaces, IIS interfaces and PWM interfaces; the I2C interfaces, the GPIO interface, the UART interface, the LVDS interface, the IIS interface and the PWM interface are all electrically connected with the processor (1).

Further, the second pin, the twenty-first pin, the twenty-seventh pin, the twenty-eighth pin, the … … and the thirty-eighth pin of the first board-to-board connector (101) are RGMII interfaces, the forty-first pin, the forty-second pin, the … … and the forty-sixth pin are OSPI interfaces, the forty-ninth pin, the fifty-fifth pin, the … … and the fifty-third pin are JTAG interfaces, and the twenty-fifth pin, the twenty-sixth pin, the thirty-ninth pin, the forty-fourth pin, the forty-seventh pin, the forty-eighth pin, the fifty-fifth pin, the fifty-sixth pin, the sixty-seventh pin and the sixty-eighth pin of the first board-to-board connector are grounded.

Further, the first pin, the second pin, the … … and the twelfth pin of the second board-to-board connector (102) are OSPI interfaces, the fifteenth pin, the sixteenth pin, the … … and the twenty-sixth pin are SD card interfaces, the twenty-ninth pin, the thirty-eleventh pin, the thirty-third pin, the thirty-fifth pin, the thirty-seventh pin, the thirty-ninth pin, the forty-first pin, the forty-third pin, the forty-fifth pin and the forty-seventh pin are DSI interfaces, the thirty-third pin, the thirty-second pin, the thirty-fourth pin, the thirty-sixth pin, the thirty-eighth pin, the forty-fifty-second pin, the forty-fourth pin, the forty-sixth pin, the forty-eighth pin and the forty-seventh pin are CSI interfaces, the first pin, the thirty-fifty-fourth pin, the … … and the sixty-second pin are RGMII interfaces, the thirteenth pin, the fourteenth pin, the twenty-seventh pin, the twenty-eighth pin, the twenty-ninth pin, the forty-sixth pin, the sixteenth pin and the tenth pin are grounded.

Further, the first pin, the second pin, the third pin, the fourth pin, the seventh pin, the eighth pin, the ninth pin, the tenth pin, the thirteenth pin, the fourteenth pin, the fifteenth pin, the sixteenth pin, the nineteenth pin, the twentieth pin, the twenty-first pin and the twenty-second pin of the third board-to-board connector (103) are USB interfaces, the twenty-fifth pin, the twenty-sixth pin, the twenty-seventh pin, the twenty-eighth pin, the thirty-eleventh pin, the thirty-second pin, the thirty-third pin, the thirty-fourth pin, the thirty-seventh pin and the thirty-ninth pin are PCIE interfaces, the fortieth pin, the forty-second pin, the forty-fourth pin, the forty-sixth pin, the forty-eighth pin, and the fifty-sixth pin are I2S interfaces, and the fifth pin, the sixth pin, the eleventh pin, the twelfth pin, the seventeenth pin, the eighteenth pin, the twenty-third pin, the twenty-fourth pin, the twenty-ninth pin, the thirty-fifth pin, the thirty-sixth pin, the forty-first pin, the sixtieth pin, the seventy-fifth pin, and the seventy-sixth pin are grounded.

Further, the first pin, the second pin, … …, the eighth pin, the tenth pin, the twelfth pin, the fourteenth pin and the sixteenth pin of the fourth board-to-board connector (104) are I2C interfaces, the ninth pin, the eleventh pin, the seventeenth pin, the nineteenth pin, the twentieth pin, … …, the twenty-fifth pin, the twenty-seventh pin, the twenty-eighth pin, the twenty-ninth pin, the thirty-eleventh pin and the thirty-second pin are GPIO interfaces, the thirteenth pin and the fifteenth pin are UART interfaces, the twenty-sixth pin and the thirty-fifth pin are IIS interfaces, the thirty-fifth pin, the thirty-sixth pin, … … and the fifty-fourth pin are LVDS interfaces, and the thirty-third pin and the thirty-fourth pin are grounded.

Further, the memory module (3) is a FLASH memory.

On the other hand, the utility model also provides a device, which comprises a device bottom plate; be equipped with as above intelligent core plate on the equipment bottom plate.

Compared with the prior art, the utility model provides a pair of nuclear core plate of intelligence and equipment possesses following beneficial effect:

(1) The utility model provides a pair of intelligence nuclear core plate, including four boards to the board connector, every board contains 80 pins to the board connector, and every board is 0.5mm to the pin interval of board connector, and the board sets up according to predetermineeing the pin mode of arranging to the board connector, the utility model discloses a pin interval between the different speed interfaces of rational arrangement, same function interface are unified to be placed and are drawn forth, increase and prevent reverse plug protection, the whole methods of drawing forth of CPU pin, let the user design different products fast simply, reduce the design cost, reduce the development degree of difficulty and save development time.

(2) The utility model provides a pair of nuclear core plate of intelligence, rationally distributed, ductility is strong, has fine practical value.

Drawings

Fig. 1 is a schematic block diagram of an intelligent core board according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of an intelligent core board according to an embodiment of the present application;

fig. 3 is a circuit schematic diagram of a first board-to-board connector provided by an embodiment of the present application;

fig. 4 is a circuit schematic diagram of a second board-to-board connector provided by an embodiment of the present application;

fig. 5 is a circuit schematic diagram of a third board-to-board connector provided by an embodiment of the present application;

fig. 6 is a schematic circuit diagram of a fourth board-to-board connector provided in an embodiment of the present application.

Detailed Description

The following detailed description of the preferred embodiments of the invention, which is to be read in connection with the accompanying drawings, forms a part of this application, and together with the embodiments of the invention, serve to explain the principles of the invention and not to limit its scope.

Fig. 1 is a schematic block diagram of an intelligent core board according to an embodiment of the present disclosure, and as shown in fig. 1, the intelligent core board includes a processor 1, a memory module 2, a memory module 3, a power management module 4, a reset module 5, a wireless network module 6, and four board-to-board connectors symmetrically arranged; the processor 1 is respectively connected with the memory module 2, the storage module 3, the power management module 4, the reset module 5 and the wireless network module 6; the board-to-board connector is connected with the bottom board interface of the core board, and pins of the board-to-board connector are arranged in a preset mode; the four symmetrically arranged board-to-board connectors are respectively positioned at four end points of the same plane of the core board; each board-to-board connector comprises 80 pins; the pin pitch of each board-to-board connector is 0.5mm. It should be noted that the modules in the smart core board may be deleted or added according to actual needs, and the main protection is the board-to-board connector arrangement. The memory module 3 is preferably a FLASH memory, and the power management module 4 is preferably a PMIC power management module and a PMIC power management module, and is responsible for the power-on time sequence of the CPU and the output of various voltages required by the CPU.

Fig. 2 is a schematic structural diagram of an intelligent core board provided in an embodiment of the present application, where the processor 1 is a core D9 series processor, and four symmetrically arranged board-to-board connectors are a first board-to-board connector 101, a second board-to-board connector 102, a third board-to-board connector 103, and a fourth board-to-board connector 104, respectively; the first board-to-board connector 101 and the third board-to-board connector 103 are arranged on the same side of the core board, and the second board-to-board connector 102 and the fourth board-to-board connector 104 are arranged on the other side of the core board; the first board-to-board connector 102 and the fourth board-to-board connector 104 are symmetrically arranged, and the second board-to-board connector 102 and the third board-to-board connector 103 are symmetrically arranged; the positions of the four board-to-board connectors can be arranged according to actual conditions, and the arrangement mode is not limited to the arrangement mode.

As shown in fig. 2, the board-to-board connector on the lower left side is a first board-to-board connector 101, and first pins of the first board-to-board connector are arranged downward from the upper right corner to the left side alternately, and the total number of the first pins is 80; the board-to-board connector on the upper right side is a second board-to-board connector 102, and first pins of the second board-to-board connector are alternately arranged downwards from the upper right corner to the left side in turn, so that 80 pins are total; the board-to-board connector on the lower right side is a third board-to-board connector 103, and first pins of the third board-to-board connector are alternately arranged downwards from the upper right corner to the left side in turn, so that the total number of the pins is 80; the board-to-board connector on the upper left side is a fourth board-to-board connector 104, and first pins of the fourth board-to-board connector are alternately arranged downwards from the upper right corner to the left side in turn, so that the total number of the pins is 80; four board-to-board connectors have a total of 320 pins.

Specifically, the first board-to-board connector 101 and the third board-to-board connector 103 are disposed on the same side of the core board, and the second board-to-board connector 102 and the fourth board-to-board connector 104 are disposed on the other side of the core board; the first board-to-board connector 102 and the fourth board-to-board connector 104 are symmetrically arranged, and the second board-to-board connector 102 and the third board-to-board connector 103 are symmetrically arranged, so that the phenomenon that a user is reversely inserted in the using process can be prevented.

Fig. 3 is a schematic circuit diagram of the first board-to-board connector 101 according to an embodiment of the present application, and fig. 3 shows a specific pin circuit of the first board-to-board connector 101, where the pin positions and definitions of the pin circuits are specially designed to solve the problems of crosstalk and wiring difficulty. The first board-to-board connector 101 comprises a plurality of GPIO interfaces, RGMII interfaces, UART interfaces, a CANFD interface, an SD card interface, an I2C interface, an OSPI interface and a JTAG interface; the GPIO interfaces, the RGMII interface, the UART interface, the CANFD interface, the SD card interface, the I2C interface, the OSPI interface and the JTAG interface are all electrically connected with the processor 1. Referring to fig. 3, the first board-to-board connector includes a 1-way GPIO interface, a 1-way RGMII interface, a 3-way UART interface, a 1-way CANFD interface, a 1-way SD card interface, a 1-way I2C interface, a 1-way OSPI interface, and a 1-way JTAG interface; the 1-path GPIO interface, the 1-path RGMII interface, the 3-path UART interface, the 1-path CANFD interface, the 1-path SD card interface, the 1-path I2C interface, the 1-path OSPI interface and the 1-path JTAG interface are all electrically connected with the processor 1.

Notably, the OSPI interface represents a serial peripheral interface; the GPIO interface represents a general input/output interface; the interface type defined in this embodiment is common knowledge, and the interface definitions not mentioned in this embodiment can refer to the following table and fig. 3, which are not described herein again.

Illustratively, the second pin, the twenty-first pin, the twenty-seventh pin, the twenty-eighth pin, the … … and the thirty-eighth pin of the first board-to-board connector 101 are RGMII interfaces, the forty-first pin, the forty-second pin, the … … and the forty-sixth pin are OSPI interfaces, the forty-ninth pin, the fifty-fifth pin, the … … and the fifty-third pin are JTAG interfaces, and the twenty-fifth pin, the twenty-sixth pin, the thirty-ninth pin, the forty-fourth pin, the forty-seventh pin, the forty-eighth pin, the fifty-fifth pin, the fifty-sixth pin, the sixty-seventh pin and the sixty-eighth pin of the first board-to-board connector 101 are grounded. A fourth pin, a sixth pin, a twelfth pin, a fourteenth pin, a fifteenth pin and a twentieth pin are UART interfaces; the eleventh pin and the thirteenth pin are I2C interfaces. The above is only an example of the selected representative pins, and other pin positions and definition relations refer to the following table and fig. 3, which are not described herein again.

Fig. 4 is a schematic circuit diagram of the second board-to-board connector 102 according to an embodiment of the present application, and fig. 4 shows a specific pin circuit of the second board-to-board connector 102, where the pin positions and definitions of the pin circuits are specially designed to solve the problems of crosstalk and wiring difficulty. The second board-to-board connector 102 has several OSPI interfaces, SD card interfaces, DSI interfaces, CSI interfaces, and RGMII interfaces; the OSPI interfaces, the SD card interface, the DSI interface, the CSI interface and the RGMII interface are all electrically connected with the processor 1. As shown in fig. 4, the second board-to-board connector 102 includes a 1-way OSPI interface, a 2-way SD card interface, a 1-way DSI interface, a 1-way CSI interface, and a 1-way RDMII interface, where the 1-way OSPI interface, the 2-way SD card interface, the 1-way DSI interface, the 1-way CSI interface, and the 1-way RDMII interface are all electrically connected to the processor 1.

Notably, the OSPI interface represents a synchronous peripheral interface; the DSI interface represents a display interface; the CSI interface represents a camera serial interface; the interface type defined in this embodiment is common knowledge, and the interface definitions not mentioned in this embodiment can refer to the following table and fig. 4, which are not described herein again.

Illustratively, the first pin, the second pin, the … … and the twelfth pin of the second board-to-board connector 102 are OSPI interfaces, the fifteenth pin, the sixteenth pin, the … … and the twenty-sixth pin are SD card interfaces, the twenty-ninth pin, the thirty-eleventh pin, the thirty-third pin, the thirty-fifth pin, the thirty-seventh pin, the thirty-ninth pin, the forty-first pin, the forty-third pin, the forty-fifth pin and the forty-seventh pin are DSI interfaces, the thirty-third pin, the thirty-second pin, the thirty-fourth pin, the thirty-sixth pin, the thirty-eighth pin, the forty-fourth pin, the forty-sixth pin, the forty-eighth pin and the forty-seventh pin are CSI interfaces, the thirty-first pin, the forty-second pin, the … … and the sixty-twelfth pin are RGMII interfaces, the thirteenth pin, the fourteenth pin, the seventh pin, the twenty-eighth pin, the ninth pin, the twenty-sixth pin, the sixteenth pin and the sixteenth pin are grounded. The above is only an example of the selected representative pins, and other pin positions and definition relations refer to the following table and fig. 4, which are not described herein again.

Fig. 5 is a schematic circuit diagram of the third board-to-board connector 103 according to an embodiment of the present application, and fig. 5 shows a specific pin circuit of the third board-to-board connector 103, where the pin positions and definitions in the circuit are specially designed to solve the problems of crosstalk and wiring difficulty. The third board-to-board connector 103 has a plurality of USB interfaces, PCIE interfaces, GPIO interfaces, UART interfaces, I2S interfaces, and ADC interfaces; the USB interfaces, the PCIE interface, the GPIO interface, the UART interface, the I2S interface and the ADC interface are electrically connected with the processor 1. Referring to fig. 5, the third board-to-board connector 103 includes a 2-way USB interface, a 2-way PCIE interface, a 1-way GPIO interface, a 1-way UART interface, a 1-way I2S interface, and a 1-way ADC interface; the 2-channel USB interface, the 2-channel PCIE interface, the 1-channel GPIO interface, the 1-channel UART interface, the 1-channel I2S interface and the 1-channel ADC interface are all electrically connected with the processor 1.

It is worth noting that the PCIE interface is a high-speed serial bus interface; the GPIO interface is a general input/output interface; the I2S interface represents a digital audio interface; the interface type defined in this embodiment is common knowledge, and the interface definitions not mentioned in this embodiment can refer to the following table and fig. 5, which are not described herein again.

Illustratively, the first pin, the second pin, the third pin, the fourth pin, the seventh pin, the eighth pin, the ninth pin, the tenth pin, the thirteenth pin, the fourteenth pin, the fifteenth pin, the sixteenth pin, the nineteenth pin, the twentieth pin, the twenty-first pin, and the twenty-second pin of the third board-to-board connector 103 are USB interfaces, the twenty-fifth pin, the twenty-sixth pin, the twenty-seventh pin, the twenty-eighth pin, the thirty-eleventh pin, the thirty-second pin, the thirty-third pin, the thirty-fourth pin, the thirty-seventh pin, and the thirty-ninth pin are PCIE interfaces, the forty-fourth pin, the forty-sixth pin, the forty-eighth pin, and the fifty-fifth pin are I2S interfaces, the fifth pin, the sixth pin, the eleventh pin, the twelfth pin, the seventeenth pin, the eighteenth pin, the twenty-third pin, the twenty-fourth pin, the twenty-ninth pin, the thirty-fifth pin, the sixth pin, the thirty-sixth pin, the sixteenth pin, the twelfth pin, the seventeenth pin, and the seventeenth pin are grounded. The above is only an example of the selected representative pins, and other pin positions and definition relations refer to the following table and fig. 5, which are not described herein again.

Fig. 6 is a schematic circuit diagram of the fourth board-to-board connector 104 according to an embodiment of the present application, and fig. 6 shows a specific pin circuit of the fourth board-to-board connector 104, where the pin positions and definitions of the pin circuits are specially designed to solve the problems of crosstalk and wiring difficulty. The fourth board-to-board connector 104 has a plurality of I2C interfaces, GPIO interfaces, UART interfaces, LVDS interfaces, IIS interfaces, and PWM interfaces; the I2C interfaces, the GPIO interface, the UART interface, the LVDS interface, the IIS interface and the PWM interface are electrically connected with the processor 1. Referring to fig. 6, the fourth board-to-board connector 104 includes 6 paths of I2C interfaces, 1 path of GPIO interfaces, 1 path of UART interfaces, 3 paths of LVDS interfaces, 1 path of IIS interfaces, and 1 path of PWM interfaces; the 6I 2C interfaces, the 1 GPIO interface, the 1 UART interface, the 3 LVDS interfaces, the 1 IIS interface and the 1 PWM interface are all electrically connected with the processor 1. It is noted that twenty-sixth pin and thirty-third pin represent the IIS interface, and the eighteenth pin represents the PWM pulse output interface.

Notably, the GPIO interface represents a general purpose input output interface; the LVDS interface is a display screen interface; the interface type defined in this embodiment is common knowledge, and the interface definitions not mentioned in this embodiment can refer to the following table and fig. 6, which are not described herein again.

Illustratively, the first pin, the second pin, the … …, the eighth pin, the tenth pin, the twelfth pin, the fourteenth pin and the sixteenth pin of the fourth board-to-board connector 104 are I2C interfaces, the ninth pin, the eleventh pin, the seventeenth pin, the nineteenth pin, the twentieth pin, … …, the twenty-fifth pin, the twenty-seventh pin, the twenty-eighth pin, the twenty-ninth pin, the thirty-eleventh pin and the thirty-second pin are GPIO interfaces, the thirteenth pin and the fifteenth pin are UART interfaces, the twenty-sixth pin and the thirty-fifth pin are IIS interfaces, the thirty-fifth pin, the thirty-sixth pin, … … and the fifty-fourth pin are LVDS interfaces, and the thirty-third pin and the thirty-fourth pin are grounded. The above is only an example of the selected representative pins, and other pin positions and definition relations refer to the following table and fig. 6, which are not described herein again.

In the specific pin position setting and definition, the high-speed interface pins are arranged on two sides of the chip close to the outside, such as pins corresponding to a USB interface, and meanwhile, data transmission pins of different types are separated by GND grounding pins, so that the crosstalk phenomenon between the data transmission pins and the GND grounding pins is prevented, meanwhile, the pins of the same type are arranged together, and functional pins such as an I2C interface and a UART interface are arranged at adjacent positions. The pins of the board-to-board connector in the following table correspond to the CPU pins in the processor one-to-one, and the specific correspondence is shown in the following table and will not be described herein.

On the other hand, the embodiment further provides a device, which includes a device base plate; the equipment bottom plate is provided with the intelligent core board.

The utility model provides a pair of intelligence nuclear core plate, including four boards to the board connector, every board contains 80 pins to the board connector, and every board is 0.5mm to the pin interval of board connector, and the board sets up according to predetermineeing the pin mode of arranging to the board connector, the utility model discloses a pin interval between the different speed interfaces of rational arrangement, same function interface are unified to be placed and are drawn forth, increase and prevent reverse plug protection, the whole methods of drawing forth of CPU pin, let the user design different products fast simply, reduce the design cost, reduce the development degree of difficulty and save development time.

The utility model provides a pair of core plate of intelligence, rationally distributed, ductility is strong, has fine practical value.

The core board pin functions are defined as follows:

first board-to-board connector 101:

second board-to-board connector 102:

third board-to-board connector 103:

fourth board-to-board connector 104:

in the scheme, the method for reasonably arranging the pin intervals among the interfaces with different speeds through setting the pin positions of the board-to-board connectors and the specific connection relation is realized, the same functional interface is uniformly placed and led out, the reverse plug prevention protection is increased, the CPU pins are all led out, and the like, so that a user can quickly and simply design different products and reduce the design cost, the multiplexing function of the CPU pins maintains the original definition, the expansion or conversion function is redefined and is led out through the board-to-board connectors, and the user can refer to the evaluation board to design so as to match the development of product standard drive. The nuclear core plate that this scheme provided is rationally distributed, and ductility is good, and same function interface is unified to be placed and is drawn forth, is favorable to the user to improve the development efficiency of product, reduces development and maintenance cost. The problem of current nuclear core plate module do PCB wiring difficulty, the different speed interface that produce when the pin is drawn forth between have crosstalk, burn out nuclear core plate when the direction is wrong is solved, can let the user simply carry out product development fast, reduce development and maintenance cost, when designing field products such as AIoT, intelligent recognition, degree of depth study, can make the design according to different application occasions fast.

In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", and the like, indicate the orientation or positional relationship indicated based on the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore, should not be construed as limiting the present invention.

In the present invention, unless otherwise expressly stated or limited, the terms "disposed," "mounted," "connected," "secured," and the like are to be construed broadly, e.g., as meaning fixedly connected, detachably connected, or integrally formed; they may be mechanically coupled, directly coupled, or indirectly coupled through intervening agents, both internally and/or in any other manner known to those skilled in the art. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically limited otherwise.

It is noted that in the present disclosure, unless otherwise explicitly specified or limited, a first feature "on" or "under" a second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.

The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention should be covered by the present invention.

Claims (8)

1. An intelligent core board is characterized in that the core board comprises a processor (1), a memory module (2), a memory module (3), a power management module (4), a reset module (5), a wireless network module (6) and four board-to-board connectors which are symmetrically arranged; the processor (1) is respectively connected with the memory module (2), the storage module (3), the power management module (4), the reset module (5) and the wireless network module (6); the board-to-board connector is connected with the bottom board interface of the core board, and pins of the board-to-board connector are arranged in a preset mode; the four symmetrically arranged board-to-board connectors are respectively positioned at four end points of the same plane of the core board; each board-to-board connector comprises 80 pins; the pin pitch of each board-to-board connector is 0.5mm; the processor (1) is a core D9 series processor; the four symmetrically arranged board-to-board connectors are divided into a first board-to-board connector (101), a second board-to-board connector (102), a third board-to-board connector (103) and a fourth board-to-board connector (104); the first board-to-board connector (101) is provided with a plurality of GPIO interfaces, RGMII interfaces, UART interfaces, CANFD interfaces, SD card interfaces, I2C interfaces, OSPI interfaces and JTAG interfaces; the GPIO interfaces, the RGMII interface, the UART interface, the CANFD interface, the SD card interface, the I2C interface, the OSPI interface and the JTAG interface are all electrically connected with the processor (1); the second board-to-board connector (102) is provided with a plurality of OSPI interfaces, SD card interfaces, DSI interfaces, CSI interfaces and RGMII interfaces; the OSPI interfaces, the SD card interface, the DSI interface, the CSI interface and the RGMII interface are all electrically connected with the processor (1); the third board-to-board connector (103) is provided with a plurality of USB interfaces, PCIE interfaces, GPIO interfaces, UART interfaces, I2S interfaces and ADC interfaces; the USB interfaces, the PCIE interface, the GPIO interface, the UART interface, the I2S interface and the ADC interface are electrically connected with the processor (1); the fourth board-to-board connector (104) is provided with a plurality of I2C interfaces, GPIO interfaces, UART interfaces, LVDS interfaces, IIS interfaces and PWM interfaces; the I2C interfaces, the GPIO interface, the UART interface, the LVDS interface, the IIS interface and the PWM interface are electrically connected with the processor (1).

2. The smart core board of claim 1, wherein the second pin, the twenty-first pin, the twenty-seventh pin, the twenty-eighth pin, the … …, the thirty-eighth pin of the first board-to-board connector (101) are RGMII interfaces, the forty-first pin, the forty-second pin, the … …, the forty-sixth pin are OSPI interfaces, the forty-ninth pin, the fifty-fifth pin, the … …, the fifty-third pin are JTAG interfaces, the twenty-fifth pin, the twenty-sixth pin, the thirty-ninth pin, the forty-fourth pin, the forty-seventh pin, the forty-eighth pin, the fifty-fifth pin, the fifty-sixth pin, the sixty-seventh pin, and the sixty-eighth pin are grounded.

3. The smart core board of claim 1, wherein the first pin, the second pin, the … … and the twelfth pin of the second board-to-board connector (102) are OSPI interfaces, the fifteenth pin, the sixteenth pin, the … … and the twenty-sixth pin are SD card interfaces, the twenty-ninth pin, the thirty-eleventh pin, the thirty-third pin, the thirty-fifth pin, the thirty-seventh pin, the thirty-ninth pin, the forty-first pin, the forty-third pin, the forty-fifth pin, the forty-seventh pin are DSI interfaces, the thirty-fifth pin, the thirty-second pin, the thirty-fourth pin, the thirty-sixth pin, the thirty-eighth pin, the forty-fourth pin, the forty-sixth pin, the forty-eighth pin and the forty-eighth pin are CSI interfaces, the first pin, the second pin, the … …, the sixty-twenty-second pin is a twenty-second pin, the thirteen-third pin, the twenty-fourth pin, the twenty-eighth pin, the twenty-ninth pin, the twenty-sixth pin, and the twenty-tenth pin are rgninth pins.

4. The smart core board of claim 1, wherein the first pin, the second pin, the third pin, the fourth pin, the seventh pin, the eighth pin, the ninth pin, the tenth pin, the thirteenth pin, the fourteenth pin, the fifteenth pin, the sixteenth pin, the nineteenth pin, the twentieth pin, the twenty-first pin, and the twenty-second pin of the third board-to-board connector (103) are USB interfaces, the twenty-fifth pin, the twenty-sixth pin, the twenty-seventh pin, the twenty-eighth pin, the thirty-eleventh pin, the thirty-second pin, the thirty-third pin, the thirty-fourth pin, the thirty-seventh pin, and the thirty-ninth pin are PCIE interfaces, the forty-fourth pin, the forty-sixth pin, the forty-eighth pin, and the thirty-fourth pin are I2S interfaces, the fifth pin, the sixth pin, the eleventh pin, the twelfth pin, the seventeenth pin, the eighteenth pin, the twenty-third pin, the twenty-fourth pin, the twenty-ninth pin, the twenty-eighth pin, the thirty-sixth pin, the twenty-sixth pin, the thirty-fifth pin, the tenth pin, the twenty-ninth pin, the tenth pin, the twenty-tenth pin and the tenth pin are grounded.

5. The smart core board of claim 1, wherein the first pin, the second pin, the … …, the eighth pin, the tenth pin, the twelfth pin, the fourteenth pin, and the sixteenth pin of the fourth board-to-board connector (104) are I2C interfaces, the ninth pin, the eleventh pin, the seventeenth pin, the nineteenth pin, the twentieth pin, the … …, the twenty fifth pin, the twenty seventh pin, the twenty eighth pin, the twenty ninth pin, the thirty eleventh pin, and the thirty second pin are GPIO interfaces, the thirteenth pin and the fifteenth pin are UART interfaces, the twenty sixth pin and the thirty fifth pin are IIS interfaces, the thirty fifth pin, the thirty sixth pin, the … …, the fourth pin is an LVDS interface, and the thirty third pin and the thirty fourth pin are grounded.

6. An intelligent core board as claimed in claim 1, wherein the memory modules (3) are FLASH memories.

7. An intelligent core board as claimed in claim 1, wherein the power management module (4) is a PMIC power management module.

8. An apparatus, comprising an apparatus chassis;

the device backplane is provided with an intelligent core board as claimed in any one of claims 1 to 7.

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