CN217821590U - Multi-type digital signal receiving and transmitting conversion circuit - Google Patents
Multi-type digital signal receiving and transmitting conversion circuit Download PDFInfo
- Publication number
- CN217821590U CN217821590U CN202221827010.9U CN202221827010U CN217821590U CN 217821590 U CN217821590 U CN 217821590U CN 202221827010 U CN202221827010 U CN 202221827010U CN 217821590 U CN217821590 U CN 217821590U
- Authority
- CN
- China
- Prior art keywords
- level
- signal
- conversion circuit
- circuit
- digital signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Logic Circuits (AREA)
Abstract
The utility model discloses a polymorphic type digital signal receiving and dispatching transform circuit relates to digital signal receiving and dispatching transform technical field, and this polymorphic type digital signal receiving and dispatching transform circuit includes: TTL level conversion circuit, ECL level conversion circuit and bipolar coding signal conversion circuit. The TTL level conversion circuit, the ECL level conversion circuit and the bipolar coding signal conversion circuit respectively receive the digital signals with corresponding levels to carry out level conversion, and lay a foundation for realizing data extraction and cache from subsequent output to the digital signal processing conversion circuit, or convert the LVDS level signals sent by the digital signal processing conversion circuit into digital signals with specified level types according to requirements and output the digital signals.
Description
Technical Field
The utility model relates to a digital signal receiving and dispatching transform technical field especially relates to a polymorphic type digital signal receiving and dispatching transform circuit.
Background
At present, when the demodulator outputs demodulation decoding data, the demodulation decoding data are output through a digital output port of the demodulator, and a TTL level signal, an ECL level signal, a bipolar coding signal and the like are often adopted. The prior technical scheme is realized by a computer and a digital signal acquisition card. Due to the limited board card area, the technical scheme generally has the problems of few types of received signals and incapability of simultaneously supporting the transceiving function, and generally can only receive one of the digital signals.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a polymorphic type digital signal receiving and dispatching converting circuit can receive different level type digital signal and unify the transform to LVDS level signal, perhaps converts LVDS level signal into appointed level type digital signal and output as required.
In order to achieve the above object, the utility model provides a following scheme:
a multi-type digital signal transceiving conversion circuit, comprising: the circuit comprises a TTL level conversion circuit, an ECL level conversion circuit and a bipolar coding signal conversion circuit;
the TTL level conversion circuit is used for:
at least receiving a path of TTL level signal or at least sending a path of TTL level signal;
converting the received TTL level signal into an LVDS level signal and outputting the LVDS level signal to a digital signal processing conversion circuit;
converting the LVDS level signals sent by the digital signal processing and converting circuit into the TTL level signals and outputting the TTL level signals to the connector;
the ECL level conversion circuit is used for:
at least receiving an ECL level signal or at least sending an ECL level signal;
converting the received ECL level signal into an LVDS level signal and outputting the LVDS level signal to a digital signal processing and converting circuit;
converting the LVDS level signal sent by the digital signal processing and converting circuit into the ECL level signal and outputting the ECL level signal to a connector;
the bipolar coded signal conversion circuit is used for:
at least one path of bipolar coding signal is received or at least one path of bipolar coding signal is sent;
converting the bipolar coding signal into an LVDS level signal and outputting the LVDS level signal to a digital signal processing and converting circuit;
and converting the LVDS level signal sent by the digital signal processing and converting circuit into the bipolar coding signal and outputting the bipolar coding signal to the connector.
Optionally, when receiving or sending a path of TTL level signal, the TTL level conversion circuit at least includes:
the first receiving interface adaptation circuit is used for sequentially carrying out receiving impedance matching and bias adjustment on the received TTL level signal to obtain a single-ended signal after bias adjustment;
the first receiving level conversion circuit is connected with the first receiving interface adaptation circuit and used for converting the single-ended signal after bias adjustment into an LVDS level signal and outputting the LVDS level signal to the digital signal processing conversion circuit;
and the first output level conversion circuit is used for converting the LVDS level signals sent by the digital signal processing conversion circuit into TTL level signals and outputting the TTL level signals to the connector.
Optionally, the first receiving interface adapting circuit includes a termination matching circuit, an ac coupling circuit, and a bias adjusting circuit; the termination matching circuit adopts a parallel termination mode to ensure the integrity of an input TTL level signal; the alternating current coupling circuit is used for removing a direct current part of an input TTL level signal so as to change the TTL level signal into an alternating current digital signal which is symmetrical based on 0V voltage and simultaneously keep the input voltage of a long-time invariant signal, thereby keeping the information of the input TTL level signal unchanged; the bias adjusting circuit is used for adjusting the alternating current digital signal into a digital signal with positive bias voltage; the digital signal with the positive bias voltage is a single-ended signal after bias adjustment.
Optionally, the first receiving level conversion circuit at least comprises a SY55855VKG two-way level conversion chip, and a negative pin of a D0 channel and a negative pin of a D1 channel of the SY55855VKG two-way level conversion chip are respectively connected with a fixed level.
Optionally, the first output level conversion circuit at least comprises an SN75ALS191D two-way differential driving chip.
Optionally, when receiving or sending an ECL level signal, the ECL level conversion circuit at least includes:
the second receiving interface adaptive circuit is used for sequentially carrying out receiving impedance matching and bias adjustment on the received ECL level signal to obtain a single-ended positive level signal after bias adjustment;
the second receiving level conversion circuit is connected with the second receiving interface adaptation circuit and used for converting the single-ended positive level signal after bias adjustment into an LVDS level signal and outputting the LVDS level signal to the digital signal processing conversion circuit;
the sending level conversion circuit is used for converting the LVDS level signals sent by the digital signal processing conversion circuit into PECL level signals;
the ECL bias adjusting circuit is connected with the transmitting level conversion circuit and is used for adjusting the PECL level signal positive voltage bias to the ECL level signal of negative voltage bias;
and the output driving circuit is connected with the ECL bias adjusting circuit and is used for outputting the ECL level signal to a connector.
Optionally, the transmission level conversion circuit at least comprises a SY55857LKG dual-channel level conversion chip.
Optionally, when two paths of bipolar encoded signals are received, the bipolar encoded signal conversion circuit at least includes:
the third receiving interface adaptive circuit is used for sequentially carrying out receiving impedance matching and bias adjustment on the received bipolar coding signals to obtain bias-adjusted bipolar coding signals;
the bipolar coding detection circuit is connected with the third receiving interface adapting circuit and is used for converting the bias-adjusted bipolar coding signal into two LVDS level signals and outputting the two LVDS level signals to the digital signal processing and converting circuit;
and the second output level conversion circuit is used for converting the LVDS level signal sent by the digital signal processing conversion circuit into a bipolar coding signal and outputting the bipolar coding signal to the connector.
Optionally, the bipolar encoding and detecting circuit at least includes an SN65LVDS33PW differential-to-single-ended chip, and negative pins of a 1B channel, a 2B channel, a 3B channel, and a 4B channel of the SN65LVDS33PW differential-to-single-ended chip are respectively connected to different reference comparison levels.
Optionally, a power supply circuit is also included;
the power supply circuit is used for providing power supply support for the TTL level conversion circuit, the ECL level conversion circuit and the bipolar coding signal conversion circuit.
According to the utility model provides a concrete embodiment, the utility model discloses a following technological effect:
the utility model provides a polymorphic type digital signal receiving and dispatching converting circuit, include: TTL level conversion circuit, ECL level conversion circuit and bipolar coding signal conversion circuit. The TTL level conversion circuit, the ECL level conversion circuit and the bipolar coding signal conversion circuit respectively receive the digital signals with corresponding levels to carry out level conversion, and lay a foundation for realizing data extraction and cache from subsequent output to the digital signal processing conversion circuit, or convert LVDS level signals sent by the digital signal processing conversion circuit into digital signals with specified level types according to requirements and output the digital signals.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the embodiments will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive labor.
Fig. 1 is a block diagram of the multi-type digital signal transceiving conversion circuit of the present invention;
fig. 2 is a schematic diagram of a receiving circuit portion of the TTL level shifter of the present invention;
fig. 3 is a schematic diagram of a transmitting circuit portion of the TTL level shifter circuit of the present invention;
fig. 4 is a schematic diagram of a receiving circuit portion of the ECL level shift circuit of the present invention;
fig. 5 is a schematic diagram of a transmitting circuit portion of the ECL level shift circuit of the present invention;
fig. 6 is a schematic diagram of a transmitting circuit part of the bipolar coded signal converting circuit according to the present invention;
fig. 7 is a schematic diagram of a receiving circuit portion of the bipolar coded signal conversion circuit according to the present invention;
fig. 8 is a schematic diagram of the power circuit of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts all belong to the protection scope of the present invention.
In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention is described in detail with reference to the accompanying drawings and the detailed description.
The embodiment provides a multi-type digital signal transceiving conversion circuit which comprises a TTL level conversion circuit, an ECL level conversion circuit, a bipolar coding signal conversion circuit and a corresponding power circuit. The multi-type digital signal transceiving conversion circuit is mainly used for converting TTL level signals or ECL level signals into LVDS level signals or converting bipolar coding signals (ternary) such as HDB3/AMI/B8ZS and the like into two LVDS level signals (binary). The TTL level conversion circuit, the ECL level conversion circuit and the bipolar coding signal conversion circuit respectively receive digital signals with corresponding levels to perform level conversion, and a foundation is laid for data extraction and cache of the digital signals which are subsequently output to the digital signal processing conversion circuit and then forwarding of the digital signals through a gigabit network; the power supply circuit is used for providing power supply support for the signal conversion circuit.
As shown in fig. 1, the multi-type digital signal transceiving conversion circuit provided by the present embodiment includes a TTL level conversion circuit, an ECL level conversion circuit, a bipolar coded signal conversion circuit, and a corresponding power circuit.
The TTL level conversion circuit is used for:
at least receiving a path of TTL level signal or at least sending a path of TTL level signal; for example, four TTL level signals may be received or transmitted;
converting the received TTL level signal into an LVDS level signal and outputting the LVDS level signal to a digital signal processing conversion circuit;
converting the LVDS level signal sent by the digital signal processing and converting circuit into the TTL level signal and outputting the TTL level signal to the connector;
the ECL level conversion circuit is used for:
at least receiving an ECL level signal or at least sending an ECL level signal; for example, four ECL level signals may be received or transmitted;
converting the received ECL level signal into an LVDS level signal and outputting the LVDS level signal to a digital signal processing and converting circuit;
and converting the LVDS level signal sent by the digital signal processing and converting circuit into the ECL level signal and outputting the ECL level signal to the connector.
The bipolar coded signal conversion circuit is used for:
at least one path of bipolar coding signal is received or at least one path of bipolar coding signal is sent; for example, two bipolar coded signals can be received or transmitted;
converting the bipolar coding signal into an LVDS level signal and outputting the LVDS level signal to a digital signal processing and converting circuit;
and converting the LVDS level signal sent by the digital signal processing and converting circuit into the bipolar coding signal and outputting the bipolar coding signal to the connector.
The main functions and performance indexes of the multi-type digital signal transceiving conversion circuit are as follows:
the device has the receiving and sending functions of 4 paths of TTL level signals and clocks, and the maximum speed is 80Mbps;
the device has the receiving and sending functions of 4 paths of ECL level signals and clocks, and the maximum speed is 140Mbps;
the device has the receiving and sending functions of 2 paths of HDB3/AMI/B8ZS bipolar coding signals, and can adapt to three rates of 1.544Mbps/2.048Mbps/8.448 Mbps;
the method comprises the steps of converting a data signal and a clock signal of an ECL level or a TTL level into a data signal and a clock signal of an LVDS level;
the device is provided with a function of converting bipolar coding (ternary) signals such as HDB3/AMI/B8ZS and the like into two LVDS level signals (binary).
The method comprises the steps of converting a data signal and a clock signal of an LVDS level into a data signal and a clock signal of an ECL level or a TTL level;
the device is provided with a function of converting two LVDS level signals (binary) into 1-path bipolar coding (ternary) signals such as HDB3/AMI/B8 ZS.
Further, the TTL level shift circuit described in this embodiment has the following components and working principles:
the TTL level conversion circuit is composed of a first receiving interface adapter circuit, a first receiving level conversion circuit, and a first output level conversion circuit, wherein a transceiver circuit principle of a TTL level signal (including a clock signal and a data signal) is shown in fig. 2 and 3.
The first receiving interface adaptation circuit is used for realizing receiving impedance matching and bias adjustment functions of TTL level signals; the first receiving level conversion circuit is used for realizing the conversion function from the single-ended signal after bias adjustment to the LVDS level signal; the first output level conversion circuit is used for realizing the functions of converting LVDS level signals into TTL level signals and driving output.
The first receiving interface adaptation circuit is used for sequentially carrying out receiving impedance matching and bias adjustment on the received TTL level signal to obtain a single-ended signal after bias adjustment; the first receiving level conversion circuit is connected with the first receiving interface adaptation circuit and used for converting the single-ended signal after bias adjustment into an LVDS level signal and outputting the LVDS level signal to the digital signal processing conversion circuit; and the first output level conversion circuit is used for converting the LVDS level signals sent by the digital signal processing conversion circuit into TTL level signals and outputting the TTL level signals to the connector.
The first receiving interface adapting circuit comprises a termination matching circuit, an alternating current coupling circuit and a bias adjusting circuit. The termination matching circuit adopts a parallel termination mode, the input end is connected with reference voltage (the reference voltage is 0V when the TTL level signal is input) in parallel through a 56-ohm resistor, and the input end is ensured to realize the best termination matching on the TTL level signal, so that the integrity of the input signal is ensured. The AC coupling circuit can remove the DC part of the input TTL level signal, change the TTL level signal into an AC digital signal which is symmetrical based on 0V voltage, and simultaneously keep the input voltage of a long-time invariant signal (long 1 signal), thereby keeping the information of the input signal unchanged. The bias adjustment circuit adjusts the ac digital signal to a digital signal having a positive bias voltage of 1.5V.
The core of the first receiving level conversion circuit is a Micrel SY55855VKG two-way level conversion chip. Its common usage is that the differential CML/PECL/LVPECL level signal who inserts the double-circuit input and convert it into LVDS level signal, but in the utility model discloses in, through the fixed level of receiving 1.886V respectively with the D0 passageway of SY55855VKG chip and the negative pin of D1 passageway, successfully make two way differential input interfaces of this chip become the high-low level comparison interface of two way TTL level signal to realize that the high level and the low level of single-ended input TTL level signal successfully convert into the high level and the low level that accord with LVDS level signal requirement.
The first output level conversion circuit is built by an SN75ALS191D double-path differential driving chip of TI company, and as long as an input signal, namely the high level of an LVDS level signal is more than 2V and the low level is less than 0.8V, the chip can output a TTL level signal with the high level of 3.3V and the low level of less than 0.5V when VCC is 5V.
Further, the ECL level shift circuit described in this embodiment has the following components and working principle:
the ECL level conversion circuit consists of a second receiving interface adapter circuit, a second receiving level conversion circuit, a sending level conversion circuit, an ECL bias adjustment circuit and an output driving circuit. The principle of the transceiver circuit of one path of ECL level signals (including clock data and data signals) is shown in fig. 4 and 5.
The second receiving interface adaptation circuit is used for realizing receiving impedance matching and bias adjustment functions of the ECL level signal; the second receiving level conversion circuit is used for realizing the function of converting the single-ended positive level signal after bias adjustment into an LVDS level signal; the sending level conversion circuit is used for converting the LVDS level signal into the PECL level signal; the ECL bias adjusting circuit is used for adjusting the positive voltage bias of the PECL level signal to the negative voltage bias of the ECL level signal; the output driving circuit is used for realizing the driving output function of the ECL level signal.
The second receiving interface adaptive circuit is used for sequentially carrying out receiving impedance matching and bias adjustment on the received ECL level signal to obtain a single-ended positive level signal after bias adjustment; the second receiving level conversion circuit is connected with the second receiving interface adaptation circuit and used for converting the single-ended positive level signal after bias adjustment into an LVDS level signal and outputting the LVDS level signal to the digital signal processing conversion circuit; the sending level conversion circuit is used for converting the LVDS level signals sent by the digital signal processing conversion circuit into PECL level signals; the ECL bias adjusting circuit is connected with the transmitting level conversion circuit and is used for adjusting the PECL level signal positive voltage bias to the ECL level signal of negative voltage bias; and the output driving circuit is connected with the ECL bias adjusting circuit and is used for outputting the ECL level signal to a connector.
The second receiving interface adapting circuit comprises a termination matching circuit, an alternating current coupling circuit and a bias adjusting circuit. The termination matching circuit adopts a parallel termination mode, the input end is connected with a reference voltage (the reference voltage is-2V when the ECL level signal is input) in parallel through a 56-ohm resistor, and the input end is ensured to realize the best termination matching on the ECL level signal, so that the integrity of the input signal is ensured. The AC coupling circuit can remove the DC part of the input digital signal, change it into an AC digital signal symmetrical based on the voltage of 0V, and simultaneously maintain the input voltage of the long-time invariant signal (long 1 signal), thereby keeping the information of the input signal unchanged. The bias adjusting circuit can adjust the alternating current digital signal into a digital signal with a positive bias voltage of 1.5V.
The core of the second receiving level conversion circuit is a Micrel SY55855VKG two-way level conversion chip. Its common usage is that the differential CML/PECL/LVPECL level signal who inserts the double-circuit input and convert it into LVDS level signal, but in the utility model discloses in, the fixed level of 1.886V is received respectively through the negative pin with the D0 passageway of SY55855VKG chip and D1 passageway, successfully makes the two way differential input interfaces of this chip become the high low level comparison interface of two way ECL level signal conversion back positive level signal to successfully convert the high level and the low level of back positive level signal of ECL level signal conversion into the high level and the low level that accord with LVDS level signal requirement.
The sending level conversion circuit adopts a SY55857LKG two-way level conversion chip of Micrel company to realize the conversion from the LVDS level signal to the differential PECL level signal.
The ECL bias adjusting circuit comprises an alternating current coupling circuit and a negative bias adjusting circuit, wherein the alternating current coupling circuit adjusts positive voltage bias of the PECL level signal into an alternating current digital signal based on 0V voltage symmetry, and the negative bias adjusting circuit pulls the alternating current digital signal into an ECL level signal with negative voltage bias through a voltage dividing resistor.
The output driving circuit adopts an ONSemi MC100EP17DTG four-way differential ECL level driving chip to realize the driving output of ECL level signals.
Furthermore, the bipolar coded signal conversion circuit of the present embodiment is composed and operates according to the principle
The bipolar coding signal conversion circuit is composed of a third receiving interface adaptation circuit, a bipolar coding detection circuit and a second output level conversion circuit, wherein the two HDB3/AMI/B8ZS bipolar coding signal receiving and transmitting circuit principles are as shown in fig. 6 and 7 (the HDB3/AMI/B8ZS bipolar coding signals are only different in coding rules, and physically adopt a bipolar ternary coding mode of a positive level, a zero level and a negative level).
The third receiving interface adapting circuit is used for realizing receiving impedance matching and bias adjustment functions of the bipolar coding signal; the bipolar coding detection circuit is used for converting each path of HDB3/AMI/B8ZS bipolar coding signal (ternary) into two LVDS level signals (binary); the second output level conversion circuit is used for realizing the function of converting two groups of LVDS level signals (binary) into two paths of HDB3/AMI/B8ZS bipolar coding signals.
The third receiving interface adaptive circuit is used for sequentially carrying out receiving impedance matching and bias adjustment on the received bipolar coding signals to obtain bias-adjusted bipolar coding signals; the bipolar coding detection circuit is connected with the third receiving interface adapting circuit and is used for converting the bias-adjusted bipolar coding signal into two LVDS level signals and outputting the two LVDS level signals to the digital signal processing and converting circuit; and the second output level conversion circuit is used for converting the LVDS level signal sent by the digital signal processing conversion circuit into a bipolar coding signal and outputting the bipolar coding signal to the connector.
The third receiving interface adapting circuit comprises a termination matching circuit, an alternating current coupling circuit and a bias adjusting circuit. The termination matching circuit adopts a parallel termination mode, and the input end is connected with a reference voltage (the reference voltage is 0V when the HDB3/AMI/B8ZS bipolar coding signal is input) in parallel through a 75-ohm resistor, so that the input end is ensured to realize the best termination matching on the HDB3/AMI/B8ZS bipolar coding signal, and the integrity of the input signal is ensured. The AC coupling circuit can remove the DC part of the input digital signal, change it into an AC digital signal symmetrical based on the voltage of 0V, and simultaneously maintain the input voltage of the long-time invariant signal (long-time positive and negative level signal), thereby keeping the information of the input signal unchanged. The bias adjustment circuit can pull up the AC digital signal through a resistor Cheng Pianzhi to be a positive level AC signal with the voltage of 2V.
The core of the bipolar encoding detection circuit is a TI company SN65LVDS33PW differential-to-single-ended chip. The normal usage is to access four input LVDS level signals and convert them into four single-ended LVDS level signals for output, but in the present invention, by connecting the negative pins of the 1B, 2B, 3B, 4B channels of the SN65LVDS33PW chip to different reference comparison levels (V + reference voltage is 2.67V, V-reference voltage is 1.33V), the four differential input interfaces of the chip are successfully changed into ternary detection interfaces of two positive level AC signals, so as to convert the single input HDB3/AMI/B8ZS bipolar coded signals into 2 LVDS level signals (one LVDS level signal contains '1' and '0' information in the HDB3/AMI/B8ZS bipolar coded signals, such as HDB3_ AH and HDB3_ BH signals in FIG. 6, and the other LVDS level signal contains '1' and '0' information in the HDB3/AMI/B8ZS bipolar coded signals, such as HDB3_ AL and HDB3_ BL in FIG. 6).
The second output level conversion circuit is built by an SN75452BD double-path differential drive chip and a PE-65968NL transformer of TI company, so that two groups of LVDS level signals (binary systems) are converted into two paths of HDB3/AMI/B8ZS bipolar coding signals to be output.
Further, the multi-type digital signal transceiving conversion circuit provided by the embodiment further comprises a power circuit; the power supply circuit is used for providing power supply support for the TTL level conversion circuit, the ECL level conversion circuit, the bipolar coded signal conversion circuit and the digital signal processing conversion circuit, and the principle of the power supply circuit is as shown in fig. 8.
The power circuit comprises a chip input 9-36V power output +5V power supply using E2405UHBD-15W, a chip input +5V power output +3.3V power supply using LTM4644IY, a chip input +5V power output +3V power supply using LTM4622IY, a chip input +3.3V power output +2.67V power supply using TPS7A9101DSKR, a chip input +3.3V power output +1.33V power supply using TPS7A9101DSKR, a chip input +5V power output-5V power supply using B0505LS-1WR3, and a chip input-5V power output-2V power supply using TPS 72301.
In the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The principle and the implementation of the present invention are explained herein by using specific examples, and the above description of the embodiments is only used to help understand the method and the core idea of the present invention; meanwhile, for the general technical personnel in the field, according to the idea of the present invention, there are changes in the concrete implementation and the application scope. In summary, the content of the present specification should not be construed as a limitation of the present invention.
Claims (10)
1. A multi-type digital signal transceiving conversion circuit, comprising: the circuit comprises a TTL level conversion circuit, an ECL level conversion circuit and a bipolar coding signal conversion circuit;
the TTL level conversion circuit is used for:
at least receiving a path of TTL level signal or at least sending a path of TTL level signal;
converting the received TTL level signal into an LVDS level signal and outputting the LVDS level signal to a digital signal processing conversion circuit;
converting the LVDS level signal sent by the digital signal processing and converting circuit into the TTL level signal and outputting the TTL level signal to the connector;
the ECL level conversion circuit is used for:
at least receiving an ECL level signal or at least sending an ECL level signal;
converting the received ECL level signal into an LVDS level signal and outputting the LVDS level signal to a digital signal processing and converting circuit;
converting the LVDS level signal sent by the digital signal processing and converting circuit into the ECL level signal and outputting the ECL level signal to a connector;
the bipolar coded signal conversion circuit is used for:
at least one path of bipolar coding signal is received or at least one path of bipolar coding signal is sent;
converting the bipolar coding signal into an LVDS level signal and outputting the LVDS level signal to a digital signal processing and converting circuit;
and converting the LVDS level signal sent by the digital signal processing and converting circuit into the bipolar coding signal and outputting the bipolar coding signal to the connector.
2. The multi-type digital signal transceiving conversion circuit according to claim 1, wherein when receiving or transmitting a path of TTL level signal, the TTL level conversion circuit at least includes:
the first receiving interface adaptation circuit is used for sequentially carrying out receiving impedance matching and bias adjustment on the received TTL level signal to obtain a single-ended signal after bias adjustment;
the first receiving level conversion circuit is connected with the first receiving interface adaptation circuit and used for converting the single-ended signal after bias adjustment into an LVDS level signal and outputting the LVDS level signal to the digital signal processing conversion circuit;
and the first output level conversion circuit is used for converting the LVDS level signals sent by the digital signal processing conversion circuit into TTL level signals and outputting the TTL level signals to the connector.
3. The multi-type digital signal transceiving conversion circuit according to claim 2, wherein the first receiving interface adaptation circuit comprises a termination matching circuit, an ac coupling circuit and a bias adjustment circuit; the termination matching circuit adopts a parallel termination mode to ensure the integrity of an input TTL level signal; the alternating current coupling circuit is used for removing a direct current part of an input TTL level signal so as to change the TTL level signal into an alternating current digital signal which is symmetrical based on 0V voltage and simultaneously keep the input voltage of a long-time invariant signal, thereby keeping the information of the input TTL level signal unchanged; the bias adjusting circuit is used for adjusting the alternating current digital signal into a digital signal with positive bias voltage; the digital signal with the positive bias voltage is a single-ended signal after bias adjustment.
4. The multi-type digital signal transceiving conversion circuit according to claim 2, wherein the first receiving level conversion circuit at least comprises a SY55855VKG dual level conversion chip, and a negative pin of a D0 channel and a negative pin of a D1 channel of the SY55855VKG dual level conversion chip are respectively connected with a fixed level.
5. The multi-type digital signal transceiving conversion circuit according to claim 2, wherein the first output level conversion circuit comprises at least an SN75ALS191D two-way differential driver chip.
6. The multi-type digital signal transceiving conversion circuit according to claim 1, wherein when receiving or transmitting an ECL level signal, the ECL level conversion circuit at least comprises:
the second receiving interface adaptive circuit is used for sequentially carrying out receiving impedance matching and bias adjustment on the received ECL level signal to obtain a single-ended positive level signal after bias adjustment;
the second receiving level conversion circuit is connected with the second receiving interface adaptive circuit and is used for converting the single-ended positive level signal after bias adjustment into an LVDS level signal and outputting the LVDS level signal to the digital signal processing conversion circuit;
the transmission level conversion circuit is used for converting the LVDS level signal transmitted by the digital signal processing conversion circuit into a PECL level signal;
the ECL bias adjusting circuit is connected with the transmitting level conversion circuit and is used for adjusting the PECL level signal positive voltage bias to the ECL level signal of negative voltage bias;
and the output driving circuit is connected with the ECL bias adjusting circuit and is used for outputting the ECL level signal to a connector.
7. The multi-type digital signal transceiving conversion circuit according to claim 6, wherein the transmission level conversion circuit comprises at least a SY55857LKG two-way level conversion chip.
8. The multi-type digital signal transceiving conversion circuit according to claim 1, wherein when receiving two bipolar encoded signals, the bipolar encoded signal conversion circuit at least comprises:
the third receiving interface adaptive circuit is used for sequentially carrying out receiving impedance matching and bias adjustment on the received bipolar coding signals to obtain bias-adjusted bipolar coding signals;
the bipolar coding detection circuit is connected with the third receiving interface adaptive circuit and is used for converting the bipolar coding signal after bias adjustment into two LVDS level signals and outputting the two LVDS level signals to the digital signal processing conversion circuit;
and the second output level conversion circuit is used for converting the LVDS level signal sent by the digital signal processing conversion circuit into a bipolar coding signal and outputting the bipolar coding signal to the connector.
9. The multi-type digital signal transceiving conversion circuit according to claim 8, wherein the bipolar encoding detection circuit at least comprises an SN65LVDS33PW differential-to-single-ended chip, and negative pins of a 1B channel, a 2B channel, a 3B channel, and a 4B channel of the SN65LVDS33PW differential-to-single-ended chip are respectively connected to different reference comparison levels.
10. The multi-type digital signal transceiving conversion circuit according to claim 1, further comprising a power supply circuit;
the power supply circuit is used for providing power supply support for the TTL level conversion circuit, the ECL level conversion circuit and the bipolar coding signal conversion circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221827010.9U CN217821590U (en) | 2022-07-15 | 2022-07-15 | Multi-type digital signal receiving and transmitting conversion circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221827010.9U CN217821590U (en) | 2022-07-15 | 2022-07-15 | Multi-type digital signal receiving and transmitting conversion circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN217821590U true CN217821590U (en) | 2022-11-15 |
Family
ID=83964301
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202221827010.9U Active CN217821590U (en) | 2022-07-15 | 2022-07-15 | Multi-type digital signal receiving and transmitting conversion circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN217821590U (en) |
-
2022
- 2022-07-15 CN CN202221827010.9U patent/CN217821590U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8588280B2 (en) | Asymmetric communication on shared links | |
| TWI653844B (en) | Usb type-c switching circuit | |
| US20040071250A1 (en) | High-speed interconnection adapter having automated lane de-skew | |
| CN1261231A (en) | Method and system for data transmission by differiential and common mode data commands | |
| JP2002204272A (en) | Device and system for transmitting signal | |
| CN102089992A (en) | Digital equalizer for high-speed serial communications | |
| US6636166B2 (en) | Parallel communication based on balanced data-bit encoding | |
| WO2005096575A1 (en) | A circuit arrangement and a method to transfer data on a 3-level pulse amplitude modulation (pam-3) channel | |
| US7522641B2 (en) | Ten gigabit copper physical layer system | |
| CN102523436A (en) | Transmission terminal, receiving terminal, multi-channel video optical fiber transmission system and multi-channel video optical fiber transmission method | |
| CN104639899A (en) | High-definition SDI (Serial Digital Interface) digital video signal optical fiber transparent transmission device | |
| CN112865880A (en) | System and method for one-way data transmission through optical port | |
| Lancheres et al. | The MIPI C-PHY standard: A generalized multiconductor signaling scheme | |
| CN203616749U (en) | Device for realizing high-speed board level communication | |
| CN217821590U (en) | Multi-type digital signal receiving and transmitting conversion circuit | |
| CN111858425B (en) | USB-optical fiber conversion device and USB communication equipment | |
| CN110865956A (en) | RS-422 communication isolation circuit | |
| WO2022088542A1 (en) | Fpga-based usb3.0/3.1 control system | |
| CN103312407B (en) | The high accuracy transmission method of time frequency signal between a kind of satellite borne equipment | |
| CN115882883A (en) | Receiver and transmitter for high-speed data and low-speed command signal transmission | |
| EP4035321A1 (en) | Complementary data flow for noise reduction | |
| CN201689889U (en) | Cascade circuit for physical layer of Ethernet | |
| EP0811287A1 (en) | Interface isolator circuit for differential signals | |
| CN204946331U (en) | A kind of communication facilities and the system of simplification multipath signal propagation passage comprised thereof | |
| CN218676026U (en) | LVDS signal isolation circuit structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |