CN217788004U

CN217788004U - Novel gate circuit

Info

Publication number: CN217788004U
Application number: CN202221916254.4U
Authority: CN
Inventors: 吴文靖
Original assignee: Fujian Huajiacai Co Ltd
Current assignee: Fujian Huajiacai Co Ltd
Priority date: 2022-07-25
Filing date: 2022-07-25
Publication date: 2022-11-11
Anticipated expiration: 2032-07-25

Abstract

The utility model provides a novel gate circuit, novel gate circuit includes VGL, TFT device, CK, G (n), G (n + 1), G (n-1), electric capacity C1 and electric capacity C2, the TFT device includes T1, T2, T3, T4, T5, T6, T7, T8, T9, T10 and T11; the T10 is connected with ACK, G (n) and a capacitor C2, the T11 is connected with VGL, G (n-1) and T4, the T1, T7, T3, T4, T11 and C1 are all connected with a node Q, the capacitor C1 and the capacitor C2 are respectively connected with G (n), and the T2, T3, T6, T8 and T9 are all connected with a node P; the voltage low level of the ACK input signal is VGL, the high level is VGH1, the period is the same as that of CK, and the duty ratio of the high level of the ACK input signal is smaller than that of CK. The utility model discloses gate level circuit can improve the voltage of the output square wave of G (n), makes TFT can obtain higher on-state current and promote Q point discharge capacity, reduces the panel and appears the wrong risk of filling, promotes panel display effect.

Description

Novel gate circuit

Technical Field

The utility model relates to a floodgate level drive circuit technical field especially relates to a novel floodgate level circuit.

Background

With the development of display technology, people have higher and higher requirements on the display effect of display panels, and high refresh rate panels gradually become the mainstream of display, but with the improvement of the refresh rate of the panels, a series of new problems also occur. Firstly, the time for charging the in-plane pixels is shortened, and the problem of insufficient charging is easily caused; secondly, the Q point of the GIP circuit is not completely discharged, and T4 is turned on, thereby generating a mispulse phenomenon.

In view of the above, a novel gate circuit is proposed to improve the insufficient charging of pixels in the high refresh rate panel and solve the problem of multi-pulse (mis-charging) caused by incomplete discharging of Q-point.

Disclosure of Invention

The to-be-solved technical problem of the utility model lies in providing a novel gate level circuit, solves the not enough and incomplete problem of discharging of charging that traditional gate level circuit appears under high refresh rate, improves the whole display effect of panel.

The utility model provides a novel gate circuit, including VGL, TFT device, CK, G (n), G (n + 1), G (n-1) and electric capacity C1, the TFT device includes T1, T2, T3, T4, T5, T6, T7, T8 and T9, the gate circuit still includes electric capacity C2 and ACK input signal, the TFT device still includes T10 and T11;

the VGL is connected to T1 and T3 through T2, the T1 is connected to G (n-1) and FW, the VGL is connected to T6 and T7 through T3, the T7 is connected to BW and G (n-1), the VGL is connected to T8 and CKB through T9, the T8 is connected to CK, the VGL is connected to T2, T3, T9, T8 and T5 through T6, the VGL is connected to T4 and CKB through T6, and the T5 is connected to CK and between T1 and T7 through T4;

the T10 is connected to ACK, G (n) and a capacitor C2, the T11 is connected to VGL, G (n-1) and T4, the T1, T7, T3, T4, T11 and C1 are all connected to a node Q, the capacitor C1 and the capacitor C2 are respectively connected with G (n), and the T2, T3, T6, T8 and T9 are all connected to a node P;

the voltage low level of the ACK input signal is VGL, the voltage high level of the ACK input signal is VGH1, the period is the same as that of CK, and the duty ratio of the high level of the ACK input signal is smaller than that of CK.

Furthermore, the VGL is an input signal of the gate circuit and is at a low level.

Further, the CK is a gate circuit input signal and is a clock signal.

Further, G (n), G (n-1) and G (n + 1) are gate circuit output stage transmission signals and are used for controlling in-plane pixel TFTs.

The utility model has the advantages of as follows: two TFT devices of T10 and T11 are added on a traditional gate circuit, a C2 capacitor device and ACK, G (n + 1) and VGL input signals form a novel gate circuit, the voltage of the output square wave of G (n) can be improved by the circuit, the TFT can obtain higher on-state current, the Q-point discharge capacity is improved, the risk of multipulse (mis-charging) of a panel is reduced, and the display effect of the panel is improved.

Drawings

The invention will be further described with reference to the following examples with reference to the accompanying drawings.

FIG. 1 is a schematic diagram of a conventional gate level circuit.

FIG. 2 is a timing diagram of a conventional gate circuit.

FIG. 3 is a schematic diagram of in-plane pixel charging.

Fig. 4 is a schematic structural diagram of the novel gate stage circuit of the present invention.

Fig. 5 is a schematic diagram of the novel gate level circuit driving timing sequence of the present invention.

Fig. 6 is an execution flow chart of the novel gate level circuit driving method of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

The utility model discloses a novel gate stage circuit is based on the improvement on the basis of traditional gate stage circuit and drive chronogenesis as shown in fig. 1 and fig. 2. In a conventional gate circuit design, after a T4 device is turned on, a gate voltage of a display area is a gate output signal, generally called Gout or G (n), which is obtained by converting a current gate CK signal into a gate output signal after passing through the T4 device, because an in-plane pixel charging time of a panel is also fixed on the premise that a refresh rate of the panel is fixed, as shown in fig. 3, in order to improve a pixel charging effect of the display area, we need to increase the gate output voltage to obtain a higher on-state current (Ion) of a TFT device, thereby increasing a charging rate of the TFT device and improving the in-plane pixel charging effect, but simply increasing the charging rate of the pixel is not enough, so that a mispacking phenomenon easily occurs, and normal display of the panel is also affected. Because the discharge time of the Q point of the panel is shortened under the condition of high refresh rate, if the Q point has residual charges, the panel has a phenomenon of mispulse, thereby affecting the normal display of the panel.

Therefore, the utility model provides a novel floodgate level circuit, the overall design thinking is as follows: two TFT devices of T10 and T11 are added on the traditional gate circuit, a C2 capacitor device and ACK, G (n + 1) and VGL input signals form a novel gate circuit, the circuit can improve the voltage of the output square wave of G (n), the TFT can obtain higher on-state current and simultaneously can fully discharge Q points, the phenomena of insufficient pixel charging in a panel with high refresh rate and multipulse (mischarging) caused by incomplete Q point discharging are improved, and the display effect of the panel is improved.

As shown in fig. 3 to fig. 5, the novel gate circuit of the present invention specifically includes VGL, TFT device, CK, G (n), G (n + 1), G (n-1), and capacitor C1, where the TFT device includes T1, T2, T3, T4, T5, T6, T7, T8, and T9, the gate circuit further includes capacitor C2 and ACK input signal, and the TFT device further includes T10 and T11;

the T10 is connected with ACK, G (n) and a capacitor C2, the T11 is connected with VGL, G (n-1) and T4, the T1, T7, T3, T4, T11 and C1 are all connected with a node Q, the capacitor C1 and the capacitor C2 are respectively connected with G (n), and the T2, T3, T6, T8 and T9 are all connected with a node P;

the voltage low level of the ACK input signal is VGL, the high level is VGH1 (usually more than 0V), the period is the same as CK, and the duty ratio of the high level of the ACK input signal is less than that of CK.

The VGL is an input signal of the gate circuit and is at a low level.

Wherein CK is a gate input signal and is a clock signal.

And G (n), G (n-1) and G (n + 1) are gate circuit output stage transmission signals and are used for controlling in-plane pixel TFTs.

As shown in fig. 3 to fig. 6, the utility model discloses a novel driving method of gate stage circuit, based on novel gate stage circuit, the method includes the following steps:

step S1, after T4 of the gate circuit is turned on, stage (1) starts, CK signal is input to G (n), G (n) will gradually output signal with same voltage as CK, and when G (n) voltage level reaches the same level as CK, stage (2) is started to enter.

Step S2, when the stage (2) begins, because the voltage level of G (n) is the same as CK, T10 is started, after T10 is started, an ACK signal is switched from a low level to a high level, the G (n) signal is coupled through a capacitor C2, and through the coupling of the ACK signal to the G (n), the G (n) can realize the output of a voltage with a higher level, which can reach (VGH + V1) theoretically, and V1= VGH1-VGL, and the voltage of the G (n) with the higher level is obtained at the moment, so that the on-state current of the TFT of the display area is increased, and the in-plane pixel charging capability is improved;

and S3, turning to a stage (3), wherein T11 and T7 are simultaneously opened in the stage (3), the Q point is fully discharged, T4 is closed, and G (n) stops outputting. In the traditional gate stage circuit, only T7 in the stage (3) is opened to discharge the Q point, so that T4 is closed, G (n) stops outputting, and the condition of incomplete discharge is easy to occur.

The utility model discloses an increase T10, two TFT devices of T11, a C2 capacitor device and ACK, G (n + 1) and VGL input signal, form a novel gate circuit, improve the voltage of the output square wave of G (n), obtain the G (n) voltage of higher quasi-level, thereby increase the on-state current of display area TFT, and then pixel charging ability in the promotion face, the not enough problem of in-plane pixel charging has been improved, in addition, adopt T7 to the not enough problem of Q point discharge to traditional gate circuit, open the realization simultaneously through T11 device and T7 and fully discharge to Q point, prevent to appear the phenomenon of multi (fill by mistake), avoid the bad effect that panel display under the high refresh rate appears.

Although specific embodiments of the present invention have been described, it will be understood by those skilled in the art that the specific embodiments described are illustrative only and are not limiting upon the scope of the invention, and that equivalent modifications and variations can be made by those skilled in the art without departing from the spirit of the invention, which is to be limited only by the claims appended hereto.

Claims

1. A novel gate stage circuit comprises VGL, TFT devices, CK, G (n), G (n + 1), G (n-1) and a capacitor C1, wherein the TFT devices comprise T1, T2, T3, T4, T5, T6, T7, T8 and T9, and are characterized in that: the gate circuit further comprises a capacitor C2 and an ACK input signal, and the TFT device further comprises T10 and T11;

2. The novel gate circuit of claim 1, wherein: the VGL is an input signal of the gate circuit and is at a low level.

3. The novel gate circuit of claim 1, wherein: CK is a gate circuit input signal and is a clock signal.

4. The novel gate circuit of claim 1, wherein: and G (n), G (n-1) and G (n + 1) are gate circuit output stage transmission signals and are used for controlling in-plane pixel TFTs.