CN217770048U

CN217770048U - Driving circuit

Info

Publication number: CN217770048U
Application number: CN202221461691.1U
Authority: CN
Inventors: 陈军; 潘华兵
Original assignee: Hangzhou Silan Microelectronics Co Ltd
Current assignee: Hangzhou Silan Microelectronics Co Ltd
Priority date: 2022-06-10
Filing date: 2022-06-10
Publication date: 2022-11-08
Anticipated expiration: 2032-06-10

Abstract

The application discloses drive circuit includes: a first bias module providing a first bias current; the first driving module responds to an input signal and pulls down an output end of the driving circuit according to the first bias current; a second bias module providing a second bias current; the second driving module responds to the input signal and pulls up the output end according to the second bias current, wherein the first bias module is connected with the output end, and the magnitude of the first bias current is controlled by the voltage of the output end after the output end is pulled down; and/or the second bias module is connected with the output end, and the magnitude of the second bias current is controlled by the voltage of the output end after the output end is pulled up. According to the method and the device, the magnitude of the bias current is changed along with the load of the output end through output voltage feedback, and therefore unnecessary power loss is reduced.

Description

Driving circuit

Technical Field

The utility model relates to an electron electric power technical field especially relates to a drive circuit.

Background

Driver circuits in logic or switch-type integrated chips (e.g., chips integrating both CMOS and bipolar devices) may provide different drive capabilities for different load requirements. The size of the bipolar driving transistor and the required bias current in the driving circuit are usually selected according to the maximum load, and when a small load is driven, the extra bias current exceeding the required driving capability causes unnecessary power loss, which is not favorable for low-power application.

SUMMERY OF THE UTILITY MODEL

In view of the above, the present invention is directed to a driving circuit, the magnitude of the bias current of which is controlled by the voltage of the output terminal, which can match the reasonable load variation range, and ensure to keep the lowest power consumption when driving different loads.

According to an aspect of the utility model, a drive circuit is provided, include: a first bias module providing a first bias current;

the first driving module is connected with the first bias module, responds to an input signal and pulls down an output end of the driving circuit according to the first bias current;

a second bias module providing a second bias current;

a second driving module connected to the second bias module, responding to the input signal and pulling up the output terminal according to the second bias current,

the first bias module is connected with the output end, and the magnitude of the first bias current is controlled by the voltage of the output end after the output end is pulled down; and/or the second bias module is connected with the output end, and the magnitude of the second bias current is controlled by the voltage of the output end after the output end is pulled up.

Optionally, the first biasing module comprises:

the first control unit provides a first control voltage according to the level state of the input signal and the voltage of the output end; and

and the first bias unit is connected with the first control unit and provides the first bias current based on the first control voltage.

Optionally, the first control unit comprises:

a first transistor, a control end of which is connected with the input signal, a first end of which is grounded, and a second end of which outputs the first control voltage;

a control end of the second transistor is connected with the output end, a first end of the second transistor is connected with a second end of the first transistor, and the second end of the second transistor is grounded; and

and a first end of the first current source is connected with a power supply end, and a second end of the first current source is connected with the first end of the second transistor.

Optionally, the first control unit further comprises:

a third transistor, a first end of which is connected to the power supply terminal and a second end of which is connected to the second end of the first transistor;

and a first flip-flop having a first terminal receiving the input signal and a second terminal connected to the control terminal of the third transistor, wherein the first flip-flop outputs a first pulse lasting for a first time when a first transition of the input signal occurs and is in a first level state otherwise.

Optionally, the first biasing unit includes:

a control end of the fourth transistor receives the first control voltage, and a first end of the fourth transistor is grounded;

and a first end of the first current mirror is connected with a second end of the fourth transistor, and the second end of the first current mirror outputs the first bias current.

Optionally, the first current mirror comprises:

a fifth transistor, a first end of which is connected to the power supply terminal, a second end of which is connected to the second end of the fourth transistor, and a control end of which is connected to the second end of the fifth transistor;

and a control end of the sixth transistor is connected with the control end of the fifth transistor, a first end of the sixth transistor is connected with the power supply end, and a second end of the sixth transistor outputs the first bias current.

Optionally, the second biasing module comprises:

the second control unit provides a second control voltage according to the level state of the input signal and the voltage of the output end; and

and the second bias unit is connected with the second control unit and provides the second bias current based on the second control voltage.

Optionally, the second control unit comprises:

a seventh transistor, having a control terminal connected to the input signal, a first terminal connected to a power supply terminal, and a second terminal outputting the second control voltage;

a control end of the eighth transistor is connected with the output end, a first end of the eighth transistor is connected with a second end of the seventh transistor, and the second end of the eighth transistor is connected with the power supply end; and

and a first end of the second current source is connected with the first end of the eighth transistor, and a second end of the second current source is grounded.

Optionally, the second control unit further comprises:

a ninth transistor having a first terminal connected to ground and a second terminal connected to the second terminal of the seventh transistor,

and a second flip-flop, having a first terminal receiving the input signal and a second terminal connected to the control terminal of the ninth transistor, wherein the second flip-flop outputs a second pulse lasting for a second time when a second transition occurs in the input signal and is otherwise in a second level state.

Optionally, the second bias unit comprises:

a tenth transistor, a control terminal of which receives the second control voltage, and a first terminal of which is connected to the power supply terminal;

and a second current mirror, wherein a first terminal of the second current mirror is connected to a second terminal of the tenth transistor, and a second terminal of the second current mirror outputs the second bias current.

Optionally, the second current mirror comprises:

an eleventh transistor, a first terminal of which is grounded, a second terminal of which is connected to the second terminal of the tenth transistor, and a control terminal of which is connected to the second terminal of the eleventh transistor;

and a twelfth transistor, a control end of which is connected with the control end of the eleventh transistor, a first end of which is grounded, and a second end of which outputs the second bias current.

Optionally, the first driving module comprises:

a third control unit controlling whether to output the first bias current according to the input signal; and

and the first driving unit is connected with the third control unit and pulls down the output end based on the first bias current.

Optionally, the third control unit comprises:

a thirteenth transistor, having a control terminal receiving the input signal and a first terminal receiving the first bias current;

a fourteenth transistor having a control terminal receiving the input signal, a first terminal connected to ground, and a second terminal connected to the second terminal of the thirteenth transistor,

the thirteenth transistor is a P-type MOS transistor, and the fourteenth transistor is an N-type MOS transistor.

Optionally, the first drive unit comprises:

a control end of the first triode is connected with a second end of the thirteenth transistor and a second end of the fourteenth transistor, the first end of the first triode is grounded through a first resistor, and the second end of the first triode is connected with a power supply end through a second resistor;

and the control end of the second triode is connected with the first end of the first triode, the first end of the second triode is grounded, and the second end of the second triode is connected with the output end of the first triode.

Optionally, the second driving module comprises:

a fourth control unit which controls whether to output the second bias current according to the input signal; and

and the second driving unit is connected with the fourth control unit and pulls up the output end based on the second bias current.

Optionally, the fourth control unit comprises:

a fifteenth transistor having a control terminal receiving the input signal and a first terminal receiving the second bias current;

a sixteenth transistor having a control terminal receiving the input signal, a first terminal connected to a power supply terminal, a second terminal connected to the second terminal of the fifteenth transistor,

the sixteenth transistor is a P-type MOS transistor, and the fifteenth transistor is an N-type MOS transistor.

Optionally, the second drive unit comprises:

a control end of the third triode is connected with the second end of the fifteenth transistor and the second end of the sixteenth transistor, a first end of the third triode is connected with a power supply end through a third resistor, and a second end of the third triode is grounded through a fourth resistor;

and the control end of the fourth triode is connected with the first end of the third triode, the first end of the fourth triode is connected with the power supply end, and the second end of the fourth triode is connected with the output end.

The utility model provides a drive circuit adopts the self-adaptation variable current's of grid coupling mode, through the grid voltage of transistor in the voltage feedback control biasing unit of output to control first biasing current/second biasing current's mode realizes feedback control biasing current. The process requirement on the triode in the driving module can be reduced, and the tolerance on temperature and voltage deviation is improved. And reasonable load variation range can be matched, the lowest power consumption can be ensured to be kept when different loads are driven, the voltage of the output end is kept in a stable range, and the condition of logic error or switch failure is ensured not to occur.

Further, the logic circuits (the trigger and the transistor connected with the trigger) are arranged in the control unit of the bias module so as to achieve the purposes of fast edge switching, improving the driving speed and reducing the static power consumption.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

FIG. 1 shows a schematic diagram of a drive circuit;

fig. 2 shows a schematic structural diagram of a driving circuit provided according to an embodiment of the present invention;

fig. 3 shows a circuit schematic diagram of a driving circuit provided according to an embodiment of the present invention;

fig. 4 shows a waveform schematic diagram of a driving circuit provided according to an embodiment of the present invention.

Detailed Description

Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In the various figures, like elements are identified with the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.

In order to reduce the extra power consumption caused by the extra bias current under low load (such as light load, no load, etc.), it is usually necessary to introduce a feedback signal from the output terminal to monitor the change of the output terminal and adjust the bias current according to the magnitude of the output load. In particular, fig. 1 shows a schematic diagram of a driving circuit.

As shown in fig. 1, the driving circuit 100 includes a first driving module 110 and a second driving module 120.

The first driving module 110 includes a transistor M24, a transistor M25, a transistor M26, a current source I22, a diode D2, a resistor R23, a resistor R24, a transistor Q23, and a transistor Q24. The control terminal of the transistor M24 receives the input signal DP, the first terminal of the transistor M24 is connected to the power supply terminal via the current source I22 and receives the power supply voltage VDD, the second terminal of the transistor M24 is connected to the anode of the diode D2, and the cathode of the diode D2 is connected to the output terminal to receive the output signal Y. A control terminal of the transistor M25 receives the input signal DP, a first terminal of the transistor M25 is grounded, and a second terminal of the transistor M25 is connected to the anode of the diode D2. A control terminal of the transistor M26 receives the input signal DN, a first terminal of the transistor M26 is grounded, and a second terminal of the transistor M26 is connected to the cathode of the diode D2 via the resistor R23. A control terminal of the transistor Q23 is connected to an anode of the diode D2, a first terminal of the transistor Q23 is grounded via a resistor R24, and a second terminal of the transistor Q23 is connected to a power supply terminal and receives a power supply voltage VDD. The control end of the triode Q24 is connected with the first end of the triode Q23, the first end of the triode Q24 is grounded, and the second end of the triode Q24 is connected with the output end.

The second driving module 120 includes a transistor M21, a transistor M22, a transistor M23, a current source I21, a diode D1, a resistor R21, a resistor R22, a transistor Q21, and a transistor Q22. The control terminal of the transistor M21 receives the input signal DN, the first terminal of the transistor M21 is connected to the power source terminal and receives the power voltage VDD, the second terminal of the transistor M21 is connected to the anode of the diode D1 through the resistor R21, and the anode of the diode D1 is connected to the output terminal to receive the output signal Y. A control terminal of the transistor M22 receives the input signal DP, a first terminal of the transistor M22 is connected to a power supply terminal and receives the power supply voltage VDD, and a second terminal of the transistor M22 is connected to the cathode of the diode D1. A control terminal of the transistor M23 receives the input signal DP, a first terminal of the transistor M23 is grounded via the current source I21, and a second terminal of the transistor M23 is connected to the cathode of the diode D1. A control terminal of the transistor Q22 is connected to a cathode of the diode D1, a first terminal of the transistor Q22 is connected to a power supply terminal via a resistor R22 and receives a power supply voltage VDD, and a second terminal of the transistor Q22 is grounded. The control end of the triode Q21 is connected with the first end of the triode Q22, the first end of the triode Q21 is connected with the power supply end and receives the power supply voltage VDD, and the second end of the triode Q21 is connected with the output end.

The feedback loop in the driving circuit 100 in this embodiment employs a bias current shunt scheme, which shunts a portion of the current from a fixed total bias current It1 (It 2) to ground to adjust the magnitude of the bias current applied to the transistor Q23 (transistor Q22). For example, when the input signal DP =0 and the input signal DN =1, the output signal Y =0. When the output load is increased, the voltage of the output end is pulled high, the forward voltage drop of the diode D2 is further reduced, the current Id2 is reduced, and the current It1 is kept unchanged, so that the current Ib1 is increased, the driving capability of the triode Q23 and the triode Q24 is increased, the voltage of the output end is prevented from rising, and the voltage of the output end is controlled within a certain range. Similarly, when the output load is reduced, the current Id2 is increased, the current Ib1 is reduced, the driving capability of the transistor Q23 and the transistor Q24 is reduced, and the voltage variation of the output end is controlled within a certain range.

The current It1 and the current It2 in the driving circuit 100 must match the maximum driving capability, and need a larger current, so that the unnecessary power consumption is caused by the redundant current during light load and no load. In addition, the driving circuit 100 also has the disadvantages of low dynamic range, high requirement on the amplification factor of the triode, low tolerance on process deviation, large temperature coefficient, small working voltage range, slow rising and falling edges of the output end voltage, and the like.

Fig. 2 shows a schematic structural diagram of a driving circuit provided according to an embodiment of the present invention.

Fig. 3 shows a circuit schematic diagram of a driving circuit provided according to an embodiment of the present invention. Fig. 4 shows a waveform schematic diagram of a driving circuit provided according to an embodiment of the present invention.

As shown in fig. 2, the driving circuit 200 includes a first bias module 210, a first driving module 220, a second bias module 230, and a second driving module 240. The first bias module 210 provides a first bias current. The first driving module 220 is connected to the first bias module 210, and is configured to pull down an output terminal of the driving circuit 200 in response to the input signal DP and according to a first bias current. And a second bias module 230 for providing a second bias current. The second driving module 240 is connected to the second bias module 230, and pulls up the output terminal according to the second bias current in response to the input signal DP. The first bias module 210 is further connected to the output terminal, and the magnitude of the first bias current provided by the output terminal after the output terminal is pulled down is controlled by the voltage of the output terminal; and/or the second bias module 230 is further connected to the output terminal and provides a second bias current whose magnitude is controlled by the voltage at the output terminal after the output terminal is pulled up.

Further, the first bias module 210 in the driving circuit 200 is further connected to the output terminal, and provides the first bias current with a magnitude controlled by the voltage of the output terminal after the output terminal is pulled down. Referring to fig. 3, the first biasing module 210 includes a first control unit 211 and a first biasing unit 212. The first control unit 211 provides a first control voltage according to a level state of the input signal DP and a voltage of the output terminal. The first bias unit 212 is connected to the first control unit 211 and provides a first bias current based on a first control voltage. The first control unit 211 includes a first transistor M1, a second transistor M2, and a first current source I1. The control end of the first transistor M1 is connected to the input signal DP, the first end of the first transistor M1 is grounded, and the second end of the first transistor M1 outputs a first control voltage. The control end of the second transistor M2 is connected to the output end, the first end of the second transistor M2 is connected to the second end of the first transistor M1, and the second end of the second transistor M2 is grounded. A first terminal of the first current source I1 is connected to the power supply terminal and receives the supply voltage VDD, and a second terminal of the first current source I1 is connected to a first terminal of the second transistor M2. The first biasing unit 212 includes a fourth transistor M4 and a first current mirror. A control terminal of the fourth transistor M4 receives the first control voltage, and a first terminal of the fourth transistor M4 is grounded. The first terminal of the first current mirror is connected to the second terminal of the fourth transistor M4, and the second terminal of the first current mirror outputs the first bias current. Further, the first current mirror includes a fifth transistor M5 and a sixth transistor M6. A first terminal of the fifth transistor M5 is connected to the power supply terminal and receives the power supply voltage VDD, a second terminal of the fifth transistor M5 is connected to a second terminal of the fourth transistor M4 as a first terminal of the first current mirror, and a control terminal of the fifth transistor M5 is connected to a second terminal of the fifth transistor M5. A control terminal of the sixth transistor M6 is connected to the control terminal of the fifth transistor M5, a first terminal of the sixth transistor M6 is connected to the power supply terminal and receives the power supply voltage VDD, and a second terminal of the sixth transistor M6 serves as a second terminal of the first current mirror to output the first bias current. Further, the first control unit 211 controls the first bias unit 212 to provide a large current for a first time when the input signal DP makes a first jump (e.g., a high jump to a low jump), and the first driving module 220 quickly responds to the first jump to pull down the output terminal. Specifically, the first control unit 211 further includes a third transistor M3 and a first flip-flop P1. The first terminal of the third transistor M3 is connected to the power source terminal for receiving the power source voltage VDD, and the second terminal of the third transistor M3 is connected to the second terminal of the first transistor M1. The first terminal of the first flip-flop P1 receives the input signal DP, and the second terminal of the first flip-flop P1 is connected to the control terminal of the third transistor M3, wherein the first flip-flop P1 outputs a first pulse (for example, a negative pulse) lasting for a first time when the first jump of the input signal DP occurs, and is otherwise in a first level state (for example, a high level).

In other embodiments, in the case that the first bias module 210 in the driving circuit 200 is not connected to the output terminal, the second bias module 230 in the driving circuit 200 is further connected to the output terminal, and the magnitude of the second bias current provided by the second bias module is controlled by the voltage of the output terminal after the output terminal is pulled up. Referring to fig. 3, the second biasing module 230 includes a second control unit 231 and a second biasing unit 232. The second control unit 231 provides a second control voltage according to the level state of the input signal DP and the voltage of the output terminal. The second bias unit 232 is connected to the second control unit 231 and provides a second bias current based on the second control voltage. The second control unit 231 includes a seventh transistor M7, an eighth transistor M8, and a second current source I2. The control terminal of the seventh transistor M7 is connected to the input signal DP, the first terminal of the seventh transistor M7 is connected to the power source terminal to receive the power source voltage VDD, and the second terminal of the seventh transistor M7 outputs the second control voltage. The control terminal of the eighth transistor M8 is connected to the output terminal, the first terminal of the eighth transistor M8 is connected to the second terminal of the seventh transistor M7, and the second terminal of the eighth transistor M8 is connected to the power supply terminal for receiving the power supply voltage VDD. A first terminal of the second current source I2 is connected to a first terminal of the eighth transistor M8, and a second terminal of the second current source I2 is grounded. The second biasing unit 232 includes a tenth transistor M10 and a second current mirror. A control terminal of the tenth transistor M10 receives the second control voltage, and a first terminal of the tenth transistor M10 is connected to the power supply terminal to receive the power supply voltage VDD. A first terminal of the second current mirror is connected to the second terminal of the tenth transistor M10, and a second terminal of the second current mirror outputs the second bias current. Further, the second current mirror includes an eleventh transistor M11 and a twelfth transistor M12. A first terminal of the eleventh transistor M11 is grounded, a second terminal of the eleventh transistor M11 is connected to a second terminal of the tenth transistor M10 as a first terminal of the second current mirror, and a control terminal of the eleventh transistor M11 is connected to a second terminal of the eleventh transistor M11. A control terminal of the twelfth transistor M12 is connected to the control terminal of the eleventh transistor M11, a first terminal of the twelfth transistor M12 is grounded, and a second terminal of the twelfth transistor M12 serves as a second terminal of the second current mirror to output the second bias current. Further, the second control unit 231 also controls the second bias unit 232 to provide a large current for a second time when the second jump (e.g., a low-level jump to a high-level jump) occurs in the input signal DP, and the input signal enters the second driving module 240 to pull up the output terminal in response to the second jump. Specifically, the second control unit 231 further includes a ninth transistor M9 and a second flip-flop P2. A first terminal of the ninth transistor M9 is grounded, and a second terminal of the ninth transistor M9 is connected to a second terminal of the seventh transistor M7. The first terminal of the second flip-flop P2 receives the input signal DP, and the second terminal of the second flip-flop P2 is connected to the control terminal of the ninth transistor M9, wherein the second flip-flop P2 outputs a second pulse (for example, a positive pulse) lasting for a second time when the second jump of the input signal DP occurs and is in a second level state (for example, a low level) otherwise.

In other embodiments, the first bias module 210 is further connected to the output terminal, and provides the first bias current with a magnitude controlled by the voltage of the output terminal after the output terminal is pulled down. And the second bias module 230 is further connected to the output terminal, and provides a second bias current with a magnitude controlled by the voltage of the output terminal after the output terminal is pulled up. For a specific circuit structure, reference is made to the above description, and details are not repeated here.

The first driving module 220 includes a third control unit 221 and a first driving unit 222. The third control unit 221 controls whether to output the first bias current according to the input signal DP. The first driving unit 222 is connected to the third control unit 221, and pulls down an output terminal based on the first bias current. The third control unit 221 includes a thirteenth transistor M13 and a fourteenth transistor M14. A control terminal of the thirteenth transistor M13 receives the input signal DP, and a first terminal of the thirteenth transistor M13 receives the first bias current. A control terminal of the fourteenth transistor M14 receives the input signal DP, a first terminal of the fourteenth transistor M14 is grounded, and a second terminal of the fourteenth transistor M14 is connected to the second terminal of the thirteenth transistor M13. The thirteenth transistor M13 is a P-type MOS transistor, and the fourteenth transistor M14 is an N-type MOS transistor. The first driving unit 222 includes a first transistor Q1 and a second transistor Q2. A control terminal of the first triode Q1 is connected to the second terminal of the thirteenth transistor M13 and the second terminal of the fourteenth transistor M14, a first terminal of the first triode Q1 is grounded via the first resistor R1, and a second terminal of the first triode Q1 is connected to the power supply terminal via the second resistor R2 to receive the power supply voltage VDD. The control end of the second triode Q2 is connected with the first end of the first triode Q1, the first end of the second triode Q2 is grounded, and the second end of the second triode Q2 is connected with the output end. The first transistor Q1 and the second transistor Q2 are, for example, N-type transistors.

The second driving module 240 includes a fourth control unit 241 and a second driving unit 242. The fourth control unit 241 controls whether to output the second bias current according to the input signal DP. The second driving unit 242 is connected to the fourth control unit 241 and pulls up an output terminal based on the second bias current. The fourth control unit 241 includes a fifteenth transistor M15 and a sixteenth transistor M16. A control terminal of the fifteenth transistor M15 receives the input signal DP, and a first terminal of the fifteenth transistor M15 receives the second bias current. A control terminal of the sixteenth transistor M16 receives the input signal DP, a first terminal of the sixteenth transistor M16 is connected to the power source terminal to receive the power source voltage VDD, and a second terminal of the sixteenth transistor M16 is connected to the second terminal of the fifteenth transistor M15. The sixteenth transistor M16 is a P-type MOS transistor, and the fifteenth transistor M15 is an N-type MOS transistor. The second driving unit 242 includes a third transistor Q3 and a fourth transistor Q4. A control terminal of the third transistor Q3 is connected to the second terminal of the fifteenth transistor M15 and the second terminal of the sixteenth transistor M16, a first terminal of the third transistor Q3 is connected to the power source terminal via a third resistor R3 to receive the power source voltage VDD, and a second terminal of the third transistor Q3 is grounded via a fourth resistor R4. A control terminal of the fourth triode Q4 is connected to a first terminal of the third triode Q3, a first terminal of the fourth triode Q4 is connected to a power supply terminal to receive a supply voltage VDD, and a second terminal of the fourth triode Q4 is connected to an output terminal. The third transistor Q3 and the fourth transistor Q4 are, for example, P-type transistors.

It should be noted that the first current source I1 and the second current source I2 both provide a small bias current.

Referring to fig. 4, when the logic input signal DP =1, the second terminal of the first flip-flop P1 is normally 1, and the second terminal of the second flip-flop P2 is normally 0. The first transistor M1 in the first bias module 210 is turned on, the third transistor M3 is turned off, and the point a (a node where the second terminal of the first transistor M1 is connected to the first terminal of the second transistor M2, the second terminal of the third transistor, and the control terminal of the fourth transistor) is pulled down to the ground, so that the fourth transistor M4 is turned off, and the fifth transistor M5 and the sixth transistor M6 are turned off. The thirteenth transistor M13 of the first driving module 220 is turned off, and the fourteenth transistor M14 is turned on, so as to ground the control terminal of the first transistor Q1, thereby turning off the second transistor Q2. The seventh transistor M7 and the ninth transistor M9 in the second biasing module 230 are turned off. The sixteenth transistor M16 in the second driving module 240 is turned off, the fifteenth transistor M15 is turned on, and then the third transistor Q3 and the fourth transistor Q4 are turned on, so that the output signal Y =1 is output by pulling up the output terminal. The output end is pulled up and forms feedback through the eighth transistor M8, the voltage of a point B (a node where the second end of the seventh transistor M7 is connected with the first end of the eighth transistor M8, the second end of the ninth transistor M9 and the control end of the tenth transistor M10) changes along with the voltage change of the output end, further the on state of the tenth transistor M10 (the on state is variable from off to full on and the current is maximum when the tenth transistor M10 is fully on) also changes along with the voltage change of the output end, and further the provided second bias current is adjusted according to the voltage of the output end so as to stabilize the voltage of the output end within a certain range.

When the logic of the input signal DP is decreased from 1 to 0 (a first jump occurs), the second terminal of the first flip-flop P1 outputs a negative pulse lasting for a first time and then outputs a constant 1, and the second terminal of the second flip-flop P2 outputs a constant 0. In the first time, the sixteenth transistor M16 in the second driving module 240 is turned on, the fifteenth transistor M15 is turned off, and then the control terminal of the third transistor Q3 is pulled to the power voltage, and the third transistor Q3 and the fourth transistor Q4 are rapidly turned off, so as to turn off the pull-up driving. At the same time, the third transistor M3 in the first bias module 210 is turned on briefly and pulls the voltage at point a to the power voltage VDD, and the fourth transistor M4 is turned on completely, so as to provide a maximum overdrive voltage (VDD-VTHP) for the fifth transistor M5 whose control terminal is shorted with the second terminal, where VTHP is the threshold voltage of the fifth transistor, so that the fifth transistor M5 generates a brief maximum current. Meanwhile, the fourteenth transistor M14 in the first driving module 220 is turned off, and the thirteenth transistor M13 is turned on. The maximum current of the fifth transistor M5 passes through the sixth transistorThe M6 mirror image flows into the first triode Q1, and the first triode Q1 and the second triode Q2 are controlled to be completely opened so as to provide instant large-current driving capability and rapidly pull down the output end to 0. After the first time, the third transistor M3 is turned off, the second transistor M2 is turned on, the output terminal is fed back to the point a through the second transistor M2, and the feedback process is started. When the feedback process is started, the output initial voltage is 0, the initial voltage at the point A is VDD, when the output is unloaded, the output end can maintain the state of 0 only by micro conduction, and at the moment, the small current source I1 enables the M2 to maintain the micro conduction state, so the voltage at the point A falls back to the vicinity of the threshold voltage VTHP, the M4 is also micro conduction, and a small bias current is provided for the Q1 through the current mirror so as to maintain the output voltage close to 0. So that during idling, the current I _Y The bias current IM4 and the mirror current IM6 are close to 0, and the whole drive circuit can keep very low current to achieve the effect of reducing power consumption. When the output end is provided with a load, the load current can pull up the output voltage, the voltage of the point A is raised by the pulled-up output voltage through the second transistor M2, the opening degree of the transistor M2 is increased, and therefore larger bias current is provided for the Q1 and the Q3 through the current mirror, further rising of the output voltage is prevented, and the output voltage is stabilized within a certain range. Current I at the output _Y ＝A _V I _M15 Where Av is the combined magnification of Q1 and Q2 (i.e., the product of the Q1 and Q2 magnifications). Therefore, the quiescent bias current can be reduced to 1/A of the required output current _V 。

When the logic of the input signal DP rises from 0 to 1 (the second jump occurs), the second terminal of the first flip-flop P1 outputs a positive pulse lasting for the second time first and then outputs a constant 0 after the second terminal of the second flip-flop P2 outputs a constant 1. In the second time, the first switching tube in the first driving module 220 is turned on to pull the point a to the ground, the fourteenth transistor M14 is turned on, the thirteenth transistor M13 is turned off, the control terminal of the first triode Q1 is pulled to the ground, the first triode Q1 and the second triode Q2 are rapidly turned off, and the pull-down driving is turned off. At the same time, the ninth transistor M9 in the second bias module 230 is turned on briefly and pulls the voltage at point B to the ground, and the tenth transistor M10 is turned on completely, so as to serve as an eleventh crystal with its control terminal shorted with the second terminalThe transistor M11 provides a maximum overdrive voltage (VDD-VTHP), where VTHP is the threshold voltage of the eleventh transistor M11, causing the eleventh transistor M11 to generate a transient maximum current. Meanwhile, the sixteenth transistor M16 in the second driving module 240 is turned off, and the fifteenth transistor M15 is turned on. The maximum current of the eleventh transistor M11 flows into the third triode Q3 after being mirrored by the twelfth transistor M12, and the third triode Q3 and the fourth triode Q4 are controlled to be completely turned on, so that the driving capability of instantaneous large current is provided, and the output end is quickly pulled up to 1. After the second time, the ninth transistor M9 is turned off, the eighth transistor M8 is turned on, the output end is fed back to the point B through the eighth transistor M8, and the feedback process is started. When the feedback process is started, the initial voltage of the output end Y is VDD, and the initial voltage of the point B is 0. When the output is no-load, the output end can maintain the output VDD state only by micro conduction, at the moment, the small current source I2 enables the M8 to maintain the micro conduction state, so that the voltage at the point B rises to be close to VDD-VTHN, the M7 is also micro conduction, and a small bias current is provided for the Q3 through the current mirror so as to maintain the output voltage close to VDD. So that during no load, the current I _Y The bias current IM4 and the mirror current IM6 are close to 0, and the whole drive circuit can keep very low current to achieve the effect of reducing power consumption. When the output end has a load, the load current pulls down the output voltage, the pulled-down output voltage pulls down the voltage at the point B through the second transistor M2, the opening degree of the transistor M7 is increased, and therefore larger bias current is provided for the Q1 and the Q3 through the current mirror, the output voltage is prevented from dropping, and the output voltage is stabilized within a certain range.

The method adopts a grid coupling self-adaptive variable current mode, and controls the grid voltage of a transistor (M4/M10) in a bias unit through the voltage feedback of an output end, thereby controlling the first bias current/the second bias current and realizing the feedback control of the bias current. The transistor that this application still sets up the trigger and is connected with the trigger in order to realize quick border switching in the control unit of biasing module, realizes improving the purpose of drive speed and reduction quiescent power dissipation to reduce the technological requirement to the drive triode, improve the tolerance to temperature and voltage skew. That is, the present application can ensure that the lowest power consumption is maintained when different loads are driven by selecting a proper circuit device size and matching a reasonable load variation range, and the voltage of the output end is maintained in a stable range, thereby ensuring that no logic error or switch failure occurs.

In accordance with the embodiments of the present invention as set forth above, these embodiments are not exhaustive and do not limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and its various embodiments with various modifications as are suited to the particular use contemplated. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A driver circuit, comprising:

a first bias module providing a first bias current;

a second bias module providing a second bias current;

2. The driving circuit of claim 1, wherein the first biasing module comprises:

3. The drive circuit according to claim 2, wherein the first control unit includes:

a first transistor, wherein a control end of the first transistor is connected with the input signal, a first end of the first transistor is grounded, and a second end of the first transistor outputs the first control voltage;

4. The drive circuit according to claim 3, wherein the first control unit further comprises:

and a first flip-flop having a first terminal receiving the input signal and a second terminal connected to the control terminal of the third transistor, wherein the first flip-flop outputs a first pulse lasting a first time when a first transition of the input signal occurs and is otherwise in a first level state.

5. The driving circuit according to claim 2, wherein the first bias unit comprises:

a fourth transistor, a control terminal receiving the first control voltage, and a first terminal grounded;

6. The driver circuit of claim 5, wherein the first current mirror comprises:

a first end of the fifth transistor is connected with a power supply end, a second end of the fifth transistor is connected with a second end of the fourth transistor, and a control end of the fifth transistor is connected with a second end of the fifth transistor;

7. The driving circuit according to claim 1 or 2, wherein the second bias module comprises:

8. The drive circuit according to claim 7, wherein the second control unit includes:

9. The drive circuit according to claim 8, wherein the second control unit further comprises:

and a second flip-flop, having a first terminal receiving the input signal and a second terminal connected to the control terminal of the ninth transistor, wherein the second flip-flop outputs a second pulse lasting for a second time when a second transition occurs in the input signal and is in a second level state otherwise.

10. The driving circuit of claim 7, wherein the second biasing unit comprises:

a tenth transistor, a control terminal of which receives the second control voltage, and a first terminal of which is connected to a power supply terminal;

11. The driver circuit of claim 10, wherein the second current mirror comprises:

and a control end of the twelfth transistor is connected with the control end of the eleventh transistor, a first end of the twelfth transistor is grounded, and a second end of the twelfth transistor outputs the second bias current.

12. The driving circuit according to claim 1, wherein the first driving module comprises:

13. The drive circuit according to claim 12, wherein the third control unit comprises:

14. The drive circuit according to claim 13, wherein the first drive unit comprises:

15. The driving circuit according to claim 1, wherein the second driving module comprises:

16. The drive circuit according to claim 15, wherein the fourth control unit includes:

17. The drive circuit according to claim 16, wherein the second drive unit comprises:

a control end of the third triode is connected with the second end of the fifteenth transistor and the second end of the sixteenth transistor, the first end of the third triode is connected with a power supply end through a third resistor, and the second end of the third triode is grounded through a fourth resistor;