CN217768381U - perovskite-HBC laminated double-sided battery structure - Google Patents

Abstract

The utility model discloses a perovskite-HBC laminated double-sided battery structure, wherein the perovskite is superposed on the back surface of the HBC battery structure to form the perovskite-HBC laminated double-sided battery structure; the structure introduces a back contact technology to ensure that the front side of the battery has no shading, and simultaneously, the perovskite is superposed on the back side to ensure that both the front side and the back side are light receiving surfaces and the current of both the front side and the back side is introduced to the middle conducting layer so as to obtain higher superposition efficiency. In addition, the battery mainly uses metal oxide films or metals such as copper, aluminum, tin and the like as battery metal electrodes, is completely desilverized, and can greatly reduce the production cost by combining cast ingot single crystals without chamfers and with low cost.

Description

perovskite-HBC laminated double-sided battery structure

Technical Field

The patent relates to a perovskite-HBC laminated double-sided battery, and belongs to the technical field of solar battery production.

Background

Efficiency improvement and cost reduction are main power for development of the photovoltaic industry and are also main research directions of photovoltaic workers. High-efficiency batteries such as IBC (ion-binding copper) and HBC (high-performance cell) back contact batteries have higher photoelectric conversion efficiency due to metal-free shading on the front surface, wherein HBC batteries have excellent passivation effect besides metal-free shading on the front surface, are always representative of high-efficiency batteries and are one of the main trends of future development of photovoltaic batteries. However, the HBC cell is a single-sided cell due to its back contact structure, and still has the problem of low light receiving efficiency, and it is difficult to break the theoretical efficiency limit (about 29%) of the single crystalline silicon cell regardless of the structural design. In recent years, therefore, perovskite-silicon tandem cells have gained increasing attention due to their extremely high photoelectric conversion efficiency (> 30%), with efficiency advantages not comparable to individual cells. However, these perovskite-silicon tandem cells basically adopt a tandem stack structure, and metal shading still exists on the back or both sides of the cells, whether single-sided or double-sided. The utility model discloses a parallelly connected laminated structure, the metal conducting layer is located the battery middle part, and the photic two sides all does not have the metal shading, combines two-sided dual glass assembly technique can obtain bigger stack efficiency (35% -45%) theoretically. In addition, the conventional high-efficiency crystalline silicon cell basically adopts czochralski silicon as a substrate, silver paste printing is basically adopted for metallization, and the cell manufacturing cost is high. The utility model discloses a no chamfer, the ingot casting single crystal of with low costs removes the silverization as the crystal silicon substrate simultaneously, and this has greatly reduced the raw materials cost of battery.

SUMMERY OF THE UTILITY MODEL

In order to solve the problems in the prior art, the utility model discloses use the ingot casting single crystal to introduce perovskite-HBC stromatolite double-sided battery structure in order to reach the purpose of carrying the effect and reducing the cost as the substrate.

The utility model relates to a perovskite-HBC stromatolite double-sided battery structure, the structure includes upper and lower two-layer structure, upper strata structure is with the back contact structure that ingot casting monocrystalline silicon is the substrate, lower floor's structure is with the back contact structure that the perovskite is the substrate;

the upper layer structure sequentially comprises an antireflection layer, a first passivation layer, a front surface field layer, a crystalline silicon substrate, an intrinsic amorphous silicon layer, an n/p type doped amorphous silicon layer and an electrode conducting layer which are arranged in an interdigital manner from top to bottom;

the lower layer structure sequentially comprises an antireflection layer, a second passivation layer, a perovskite absorption layer, an electron transmission layer/hole transmission layer and an electrode conducting layer which are arranged in an alternating mode from bottom to top.

Further, the electrode conducting layer in contact with the n-type doped amorphous silicon layer and the electron transport layer is a negative electrode conducting layer;

and the electrode conducting layer in contact with the p-type doped amorphous silicon layer and the hole transport layer is a positive electrode conducting layer.

Further, the electron transport layer/hole transport layer which are alternately arranged are:

the n-type doped amorphous silicon layer and the p-type doped amorphous silicon layer are arranged in an interdigital manner, and the electron transmission layer and the hole transmission layer are correspondingly arranged in an interdigital manner;

gaps are reserved between the n-type doped amorphous silicon layer and the p-type doped amorphous silicon layer, between the negative electrode conducting layer and the positive electrode conducting layer, and between the electron transport layer and the hole transport layer, and insulating glue is filled in the gaps.

Furthermore, 2 metal welding strips are arranged at the edge position of the back surface of the battery, the first metal welding strip is in contact with the negative electrode conducting layer to collect negative current, and the second metal welding strip is in contact with the positive electrode conducting layer to collect positive current;

or when the battery is manufactured into a component, 2 metal welding strips are arranged at the edge of the back of the battery, the first metal welding strip is in contact with the negative battery conducting layer to collect negative current, and the second metal welding strip is in contact with the positive battery conducting layer to collect positive current.

Advantageous effects

Although the HBC battery does not have the positive metal shading condition, its back contact single face battery structure still makes it have photic inefficiency scheduling problem, and the utility model discloses perovskite-HBC stromatolite double-sided battery structure has not only broken the theoretical efficiency limit (about 29%) of monocrystalline silicon batteries such as HBC, and its two-sided photic and all no metal shading can obtain bigger photic efficiency in theory moreover. In addition, the crystal silicon battery such as HBC basically adopts czochralski silicon as a substrate, and the metallization basically contains silver paste materials, so that the manufacturing cost of the battery is higher. The utility model discloses a do not have the chamfer, the ingot casting single crystal of low cost removes the silverization simultaneously as the crystal silicon substrate, and this greatly reduced the cost of manufacture of battery. The utility model discloses a two-layer tandem cell independently generates electricity each other about parallelly connected structure makes, and with positive and negative electrode design inside the battery, can form the protection of certain degree to the electrode, and this has all improved the life of battery. The utility model discloses a structural design that positive and negative electrode corresponds two solder strips has simplified the encapsulation process of two-sided dual glass assembly end.

Drawings

Fig. 1 is a schematic structural diagram of a perovskite-HBC stacked double-sided battery provided by the present invention;

fig. 2 is a schematic structural diagram of a back electrode of a perovskite-HBC stacked double-sided battery provided by the present invention;

in fig. 1, 1 is an ingot single crystal (one of N-type or P-type) substrate; 2 is a front surface field layer, a doped amorphous silicon layer or; 3 is a passivation layer, such as AlOx/SiNx lamination; 4 is intrinsic amorphous silicon i-a-Si and H layer; 5 is an n-type doped amorphous silicon n-a-Si H layer, and 6 is a p-type doped amorphous silicon p-a-Si H layer; 7 is an electrode conducting layer which is a TCO layer or a TCO, cu plating layer and TCO composite layer; 8 is an electron transport layer; 9 is a hole transport layer; 10 is perovskite absorption layer; 11 is a passivation layer; 12 is an antireflection SiNx layer; 13 is insulating glue; 14 is a metal welding strip; 14-1, the metal welding strip is contacted with the negative electrode conducting layer to collect negative current and is isolated and insulated from the positive electrode conducting layer; the 14-2 metal welding strip is contacted with the positive electrode conducting layer to collect positive current and is isolated and insulated from the negative electrode conducting layer.

Detailed Description

To make the objects, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings. Based on the embodiments in the present invention, all other embodiments obtained by the skilled in the art without creative work belong to the protection scope of the present invention.

Example 1:

the present embodiment is a perovskite-HBC stacked double-sided cell structure, as shown in fig. 1, the upper layer of the structure is an HBC back contact cell structure, and the lower layer is a perovskite back contact structure. As shown in fig. 1, the front surface of the upper HBC structure comprises a front surface field, a passivation layer and an antireflection layer, the back surface of the upper HBC structure is firstly provided with an intrinsic amorphous silicon i-a-Si layer H, and then the upper HBC structure is prepared into two units, wherein one unit is respectively provided with an n-type doped amorphous silicon layer, an electrode conducting layer and an electron transmission layer from top to bottom, and the widths of all the layers are consistent (0.5-2 mm); the two units are respectively a p-type doped amorphous silicon layer, an electrode conducting layer and a hole transmission layer from top to bottom, the widths of all the layers are consistent (0.5-2 mm), and the first unit and the second unit are isolated and insulated by insulating glue, and the insulating width is 0.3-1mm. And finally, respectively forming a perovskite absorption layer, a passivation layer and an antireflection layer from top to bottom. The electrode conductive layers provided in this embodiment are two types: one with only one TCO layer as the electrode conductive layer; the other is TCO, a Cu plating layer and a TCO composite layer, wherein the Cu plating layer is arranged between two TCO layers, the TCO can increase the transverse conductivity and assist the Cu plating layer in collecting current.

The structure is formed by connecting an upper layer battery and a lower layer battery of the perovskite in parallel through an intermediate electrode conducting layer, an n + doped amorphous silicon layer and a p + doped amorphous silicon layer which are arranged in an interdigital mode on the upper layer HBC battery correspond to an electron transmission layer and a hole transmission layer which are arranged in an interdigital mode on the lower layer perovskite battery respectively, and the middle parts of the n + doped amorphous silicon layer and the p + doped amorphous silicon layer are correspondingly connected through the electrode conducting layer. In the middle electrode conducting layer, the upper side and the lower side of the middle electrode conducting layer are respectively contacted with the n + doped amorphous silicon layer and the electron transport layer to form a negative electrode conducting layer which is contacted with a negative electrode metal welding strip 14-1; the upper and lower sides of which are in contact with the p + doped amorphous silicon layer and the hole transport layer respectively are an anode conductive layer which is in contact with an anode metal solder strip 14-2, as shown in fig. 2. In FIG. 2, 1 is an ingot casting single crystal wafer without chamfer; 8 is an electron transmission layer, and a negative electrode conducting layer of 7-1 and a 5-n type doped amorphous silicon layer are correspondingly arranged below the electron transmission layer; 9 is a hole transport layer, and a 7-2 anode conducting layer and a 6-p type doped amorphous silicon layer are correspondingly arranged below the hole transport layer; 7 is a perforated exposed conducting layer, namely a TCO layer or a TCO, cu plating layer and TCO composite layer; 14 is a metal welding strip, such as tin paste, a copper coating or aluminum paste, wherein the 14-1 metal welding strip is contacted with the negative electrode conducting layer to collect negative current and is isolated and insulated from the positive electrode conducting layer; 14-2, the metal welding strip is contacted with the positive electrode conducting layer to collect positive current and is isolated and insulated from the negative electrode conducting layer; and 13 is insulating glue.

According to the perovskite-HBC laminated double-sided battery structure, a perovskite is laminated on the back of the HBC battery structure to form the perovskite-HBC laminated double-sided battery structure; the structure introduces a back contact technology to ensure that the front side of the battery has no shading, and simultaneously, the perovskite is superposed on the back side to ensure that both the front side and the back side are light receiving surfaces and the current of both the front side and the back side is introduced to the middle conducting layer so as to obtain higher superposition efficiency.

Example 2

Taking an N-type ingot casting single crystal substrate as an example, the perovskite-HBC laminated double-sided battery comprises the following preparation steps:

step S01, polishing the two sides of the silicon wafer and performing thermal oxidation treatment on the back side of the silicon wafer to form a SiO2 layer with the thickness of 2-5 nm on the back side;

s02, adding a single-sided texturing additive into the texturing groove to perform single-sided texturing treatment on the front side of the silicon wafer;

s03, depositing an intrinsic amorphous silicon (i-a-Si: H) layer with the thickness of 5-10nm on the back surface by using a PECVD (plasma enhanced chemical vapor deposition) technology;

step S04, depositing n-type doped amorphous silicon (n-a-Si: H) layers with the thickness of 5-10nm on the front side and the back side respectively by using a PECVD technology;

step S05, etching and melting the n-a-Si and H layers on the back surface of a p-a-Si and H layer area to be prepared by using laser, then depositing the p-a-Si and H layers with the thickness of 5-10nm on the back surface by using PECVD technology, and etching and melting the p-a-Si and H layers on the n-a-Si and H layer area on the back surface by using laser to form interdigital n-a-Si, H and p-a-Si and H layers;

s06, depositing TCO, a Cu plating layer and TCO with the thickness of 150 to 300nm on the back surface by using PVD and electro-coppering technologies;

step S07, preparing an interdigital electron transport layer and a hole transport layer on the back TCO by using laser or mask technology,

the electron transport layer can be one or a combination of more of LiF, C60, znO, snOx and TiOx, the thickness is 10 to 50nm, the preparation method comprises PVD, CVD and the like, and the hole transport layer can be NiOx, moOx and PTAA (poly [ bis (4-phenyl) (2,4,6-trimethylphenyl) amine]Molecular formula C ₁₀ H ₁₃ NO ₃ 。）、Spiro-TTB（2,2',7,7' -tetrakis (di-p-tolylamino) spiro-9,9 ' -bifluorene, formula C ₈₁ H ₆₈ N ₄ . ) And Spiro-OMeTAD (2,2 ',7,7' -tetraalkyl- (N, N-di-4-methoxyphenylamino) -9,9' -spirobifluorene, formula C ₈₁ H ₆₈ N ₄ O ₈ . ) Any one or a combination of a plurality of the components, the thickness is 10 to 50nm, and the preparation method comprises spin coating, evaporation and the like;

step S08, performing laser grooving to ensure that gaps are reserved between the n-type doped amorphous silicon layer and the p-type doped amorphous silicon layer, between the cathode conducting layer and the anode conducting layer, and between the electron transport layer and the hole transport layer, and filling insulating glue;

step S09, preparing a perovskite absorption layer on the back, wherein the perovskite absorption layer can be ABX3 (A = CH3NH3+, B = Pb2+, sn2+, X = I-, cl-, br-), the thickness is 200 to 1000nm, and the preparation method comprises spin coating, spray coating, vapor deposition and the like;

step S10, respectively preparing a passivation layer and a double-sided antireflection layer on the front surface and the back surface of the battery;

step S11, laser grooving or punching is carried out to expose the positive and negative conductive layers at two ends of the battery;

and S12, connecting the welding strips, namely respectively welding and connecting the metal welding strips and the positive electrode and the negative electrode which are leaked from the two ends of the battery together (the battery end or the assembly end).

The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims (4)

1. The perovskite-HBC laminated double-sided battery structure is characterized by comprising an upper layer structure and a lower layer structure, wherein the upper layer structure is a back contact structure taking ingot monocrystalline silicon as a substrate, and the lower layer structure is a back contact structure taking perovskite as the substrate;

the upper layer structure sequentially comprises an antireflection layer, a first passivation layer, a front surface field layer, a crystalline silicon substrate, an intrinsic amorphous silicon layer, an n/p type doped amorphous silicon layer and an electrode conducting layer which are arranged in an interdigital manner from top to bottom;

the lower layer structure sequentially comprises an antireflection layer, a second passivation layer, a perovskite absorption layer, an electron transmission layer/hole transmission layer and an electrode conducting layer from bottom to top.

2. The perovskite-HBC stacked double-sided battery structure as claimed in claim 1, wherein the electrode conductive layer in contact with the n-type doped amorphous silicon layer and the electron transport layer is a negative electrode conductive layer;

and the electrode conducting layer in contact with the p-type doped amorphous silicon layer and the hole transport layer is a positive electrode conducting layer.

3. The perovskite-HBC stacked double-sided cell structure of claim 1, wherein the alternating electron transport layers/hole transport layers are:

the n-type doped amorphous silicon layer and the p-type doped amorphous silicon layer are arranged in an interdigital manner, and the electron transmission layer and the hole transmission layer are correspondingly arranged in an interdigital manner;

gaps are reserved between the n-type doped amorphous silicon layer and the p-type doped amorphous silicon layer, between the negative electrode conducting layer and the positive electrode conducting layer, and between the electron transport layer and the hole transport layer, and insulating glue is filled in the gaps.

4. The perovskite-HBC laminated double-sided battery structure as claimed in claim 1, wherein 2 metal solder strips are provided at the edge positions of the back surface of the battery, a first metal solder strip is in contact with the negative electrode conductive layer to collect negative current, and a second metal solder strip is in contact with the positive electrode conductive layer to collect positive current; the metal welding strip can be prepared at a battery end and also can be prepared at an assembly end;

or when the battery is manufactured into a component, 2 metal welding strips are arranged at the edge of the back of the battery, the first metal welding strip is in contact with the negative battery conducting layer to collect negative current, and the second metal welding strip is in contact with the positive battery conducting layer to collect positive current.

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