CN217741730U - High-capacity MBUS host computer receiving circuit based on singlechip - Google Patents
High-capacity MBUS host computer receiving circuit based on singlechip Download PDFInfo
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- CN217741730U CN217741730U CN202221568616.5U CN202221568616U CN217741730U CN 217741730 U CN217741730 U CN 217741730U CN 202221568616 U CN202221568616 U CN 202221568616U CN 217741730 U CN217741730 U CN 217741730U
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Abstract
The utility model provides a large capacity MBUS host computer receiving circuit based on singlechip for solve current MBUS host computer receiving circuit when bus current is great, follow the easy technical problem who floods of response signal. The utility model discloses a signal conversion circuit, signal conversion circuit is connected with signal clamp circuit, and signal clamp circuit is connected with signal amplification circuit, and signal amplification circuit is connected with the singlechip. The utility model has the advantages of simple circuit structure, low cost, overload protection function, large supporting node quantity, compatibility of MBUS communication of MBUS two buses and four buses, and the like; the current signal is processed and amplified in a hardware circuit mode, the analysis and signal output of the amplified data are realized through a dynamic filtering algorithm of a single chip microcomputer, the characteristics of wide dynamic range of the analyzed signal, rapidness in response, no distortion and the like are realized, and the slave machine loading capacity of the MBUS bus is greatly improved.
Description
Technical Field
The utility model relates to a technical field of MBUS bus communication especially relates to a large capacity MBUS host computer receiving circuit based on singlechip.
Background
The MBUS bus gradually becomes a main communication mode of the instrument industry due to the characteristics of strong load capacity, long communication distance, low cost, strong expandability and the like, is widely used in various instrument control systems such as heat meters, gas meters, water meters, fire alarms and the like at present, and is an important digital technology for instrument data transmission. The transmission mode of the MBUS bus is mainly that data transmission is realized by changing the voltage mode through downlink communication and changing the load current size through uplink communication.
The existing MBUS host receiving circuit mainly adopts a voltage comparator principle, a phase-shifting comparator principle and the like to acquire and identify signals, is usually used in places with fewer load slave terminals or smaller bus current load, and generally has total current less than 200mA. The scheme can conveniently realize the analysis of signals, but when the bus current is greater than 200mA, the signal-to-noise ratio on the bus becomes very small, and simultaneously, because a large number of slave devices are mounted on the bus, when the master sends a polling signal with variable voltage to the slave devices, the current on the bus has low-frequency fluctuation with larger amplitude, and at the moment, the digital signal responded by the slave devices is submerged in the current signal with the low-frequency fluctuation. In order to solve the problem of large capacity, the conventional scheme is to reduce the overall power consumption of a slave instrument so as to improve the load capacity or increase the number of controller devices. However, in many cases, since the function of the slave device is complicated, it is extremely difficult to reduce the power consumption of the slave device, and the number of controllers is increased, which increases the production cost.
SUMMERY OF THE UTILITY MODEL
Aiming at the technical problem that when the current of the bus of the existing MBUS host receiving circuit is larger, the response signal of a slave computer is easy to submerge, the utility model provides a high-capacity MBUS host receiving circuit based on a single chip microcomputer, which can realize the communication loading capacity larger than 1.2A and realize the high-capacity communication function of the MBUS bus; theoretically, the access communication capacity of the slave equipment of more than 800 paths can be realized according to the consumption calculation of 1.5mA current of each path of slave.
In order to achieve the above purpose, the technical solution of the present invention is realized as follows: a high-capacity MBUS host receiving circuit based on a single chip microcomputer comprises a signal conversion circuit, wherein the signal conversion circuit is connected with a signal clamping circuit, the signal clamping circuit is connected with a signal amplification circuit, and the signal amplification circuit is connected with the single chip microcomputer.
Preferably, the signal conversion circuit is connected with the signal isolation circuit, and the signal isolation circuit is connected with the signal clamping circuit.
Preferably, the signal conversion circuit comprises a sampling resistor R1, one end of the sampling resistor R1 is connected with the MBUS current signal, and the other end is grounded; the sampling resistor R1 is connected with a diode D1 in parallel; the signal isolation circuit comprises an isolation capacitor C1, and two ends of the isolation capacitor C1 are respectively connected with the MBUS current signal and the signal clamping circuit.
Preferably, the signal clamping circuit includes a resistor R2 and a resistor R3, one end of each of the resistor R2 and the resistor R3 is connected to an isolation capacitor C1 of the signal isolation circuit, the other end of the resistor R2 is connected to the power supply, and the other end of the resistor R3 is grounded.
Preferably, the signal amplifying circuit includes an operational amplifier, a positive phase input end of the operational amplifier is respectively connected to one ends of the resistor R2 and the resistor R3 of the signal clamping circuit, a negative phase input end of the operational amplifier is respectively connected to one ends of the resistor R5 and the resistor R6, the other end of the resistor R5 is grounded, and the other end of the resistor R6 is connected to an output end of the operational amplifier.
Preferably, the non-inverting input terminal of the operational amplifier is connected to a resistor R4, and the resistor R4 is respectively connected to one end of the resistor R2 and one end of the resistor R3; the output end of the operational amplifier is connected with the resistor R7.
Preferably, the input end of the single chip microcomputer is connected with a resistor R7 of the signal amplification circuit, and the signal output end of the single chip microcomputer outputs a digital signal.
The utility model has the advantages that: the circuit has the characteristics of simple structure, low cost, overload protection function, large quantity of supporting nodes, compatibility with MBUS communication of MBUS two buses and MBUS four buses and the like. The current signal is processed and amplified in a hardware circuit mode, the analysis of the amplified data and the signal output are realized through a dynamic filtering algorithm of a single chip microcomputer, the characteristics of wide signal dynamic range, rapidness in response, no distortion and the like are realized, and the slave on-load capacity of the MBUS bus is greatly improved. The utility model discloses can use in the current signal receiving circuit of MBUS controller bus, also can be arranged in the middle of the signal remote information communication that changes with different duty cycles with the signal or the electric current of current cycle change. This practicality can greatly improve the analytic ability of small current signal to behind a large amount of slave machines of MBUS bus access, can resolve out communication data in great low-frequency interference and high-frequency noise, increase the on-load ability of MBUS bus.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the description below are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic view of the present invention.
Fig. 2 is a circuit configuration diagram shown in fig. 1.
Fig. 3 is a signal processing flow chart of the single chip microcomputer of the present invention.
In the figure, 1 is a signal conversion circuit, 2 is a signal isolation circuit, 3 is a signal clamping circuit, 4 is a signal amplification circuit, and 5 is a single chip microcomputer.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without any creative effort belong to the protection scope of the present invention.
As shown in fig. 1, the high-capacity MBUS host receiving circuit based on the single chip microcomputer comprises a signal conversion circuit 1, wherein the signal conversion circuit 1 is connected with a signal clamping circuit 3, the signal clamping circuit 3 is connected with a signal amplifying circuit 4, and the signal amplifying circuit 4 is connected with a single chip microcomputer 5. The signal conversion circuit 1 converts the MBUS current signal into a voltage signal, and the signal clamping circuit 3 superposes a fixed direct-current component on the voltage signal to improve the amplitude of the signal. The signal amplifying circuit 4 amplifies the voltage signal, the single chip microcomputer collects the amplified signal and generates a corresponding high-low level signal through a filtering algorithm, and transmission of the signal is achieved, so that a digital signal is obtained and output.
Further, the signal conversion circuit is connected with the signal isolation circuit, and the signal isolation circuit is connected with the signal clamping circuit. The signal isolation circuit is used for isolating the direct current component of the input MBUS current signal.
As shown in fig. 2, the signal conversion circuit includes a sampling resistor R1, one end of the sampling resistor R1 with a small resistance value is connected with the MBUS current signal, and the other end is grounded; the sampling resistor R1 converts the current signal returned from the MBUS signal wire into a voltage signal. The sampling resistor R1 is connected with a diode D1 in parallel, the diode D1 is a forward diode, the anode of the diode D1 is connected with a current signal, and the cathode of the diode D1 is grounded. The forward diode is a silicon diode, and the forward conducting voltage of the silicon diode is about 0.7V and is far larger than a tiny voltage signal generated on the resistor R1, so that the diode D1 does not work in the normal working process, when an MBUS signal line is in short circuit and the voltage generated on the sampling resistor R1 is larger than 0.7V, the diode D1 is conducted, and the current on the sampling resistor R1 is shunted after the diode D1 is conducted, so that the sampling resistor R1 is protected.
As shown in fig. 2, the signal isolation circuit includes an isolation capacitor C1, and two ends of the isolation capacitor C1 are respectively connected to the MBUS current signal and the signal clamping circuit. The isolation capacitor C1 is used for isolating a direct current component in a voltage signal generated by converting the MBUS signal line through the resistor R1, and in a large-capacity MBUS bus circuit, the larger the number of slaves is, the larger the direct current component is, the more adverse to the processing of a subsequent-stage signal is. Therefore, the dc component is filtered out by the isolation capacitor C1.
As shown in fig. 2, the signal clamping circuit includes a resistor R2 and a resistor R3, one end of each of the resistor R2 and the resistor R3 is connected to an isolation capacitor C1 of the signal isolation circuit, the other end of the resistor R2 is connected to a power supply, and the other end of the resistor R3 is grounded. The voltage of the power supply is 24V, the voltage signal with the DC component filtered is clamped through a resistor R2 and a resistor R3, and after clamping, a fixed DC component is superposed on the output AC signal.
As shown in fig. 2, the signal amplifying circuit includes an operational amplifier IC1, a non-inverting input terminal of the operational amplifier IC1 is connected to one ends of a resistor R2 and a resistor R3 of the signal clamping circuit, respectively, an inverting input terminal of the operational amplifier is connected to one ends of a resistor R5 and a resistor R6, respectively, the other end of the resistor R5 is grounded, and the other end of the resistor R6 is connected to an output terminal of the operational amplifier. The resistor R5, the resistor R6, and the operational amplifier IC1 constitute a forward operational amplifier, and an alternating-current voltage with a fixed direct-current component is amplified. The amplified output voltage value Vout may be represented by the formula: vout = (1 + (R6/R5)). Vi is obtained through calculation, and Vi is input voltage, so that signals input by the Vi are amplified to a range where the single chip microcomputer can normally sample through the function of the ADC.
The positive phase input end of the operational amplifier is connected with a resistor R4, and the resistor R4 is respectively connected with one end of a resistor R2 and one end of a resistor R3; the output end of the operational amplifier is connected with a resistor R7. The resistor R4 and the resistor R7 are used for input and output current limiting respectively.
The input end of the single chip microcomputer is connected with a resistor R7 of the signal amplification circuit, and the signal output end of the single chip microcomputer outputs digital signals. After the single chip microcomputer collects the amplified signals, weak interference signals are filtered through a filtering algorithm to generate corresponding high and low level signals, and signal transmission is achieved.
The initialization process of the single chip microcomputer is mainly used for configuring various peripherals of the single chip microcomputer and configuring resources such as ADC (analog to digital converter) of the single chip microcomputer, timer interruption and the like. After the singlechip finishes program initialization work in the circuit, the timer is started, and the time for performing ADC acquisition on signals at each time can be completely the same by the timer so as to conveniently analyze and process the acquired signals. The time of the timer countdown is required to be less than 1/10 of the communication rate, so that the ADC acquisition frequency of the single chip microcomputer is increased to be high enough, after the timer countdown is finished, the AD value signal amplified by the signal amplification circuit is acquired, after the ADC data acquisition is finished, the data signal is analyzed, a standard high-low level signal is generated, and the data transmission function is realized.
After the signal passes through the hardware circuit, the influence of a direct current component is shielded, so that the signal can be amplified and processed in a wider range. If the resistor R1 is set to be 0.5 omega, when the communication current of MBUS + and MBUS-reaches 1.2A, at the moment, the voltage direct-current component obtained by dividing the resistor R1 is 0.6V and is smaller than 0.7V protected and opened by the diode D1, the diode D1 is not conducted in the forward direction, effective signals on the resistor R1 enter a signal amplification circuit after being subjected to isolation point fusion C1, the operational amplification factor of an operational amplifier is set to be 60 times, the signals can be amplified to the range in which ADC sampling of a single chip microcomputer can be normally acquired, and after data are acquired by the ADC, the acquired data are processed through a filtering algorithm, so that complete analysis of the communication data can still be realized.
The analysis of the single chip microcomputer is realized by a weighted filtering method, as shown in fig. 3, after the ADC acquisition is completed, the single chip microcomputer stores the ADC value into a cache array, the length of the array should not be greater than 50, and after the ADC value is stored into the array, a dynamic filtering algorithm is started for filtering the weak interference signal on the MBUS signal line.
The dynamic filtering algorithm adopts amplitude filtering, and whether the amplitude difference of data in an array exceeds a ripple limit value is judged, namely: | X (t) -X (t-1) & gtnon-woven fabric<∆T 0 And when the singlechip detects that the singlechip is in the idle state, the singlechip outputs a level signal value of the idle state, so that clutter output caused by interference is avoided. When the single chip microcomputer works normally, the single chip microcomputer outputs high and low level digital signals after collecting data and analyzing the data through a weighted filtering algorithm, and the digital signals are analyzed. Δ T in the above formula 0 The maximum value of the actual ripple is obtained in the actual experiment. The dynamic filtering algorithm can effectively avoid small-amplitude clutter interference caused by high-frequency signals and low-frequency signals, has the characteristics of more flexible use, higher filtering efficiency and the like compared with a hardware filtering circuit, and provides more accurate original data for the extraction and conversion of data in the later period through the amplitude filtering algorithm.
After the single chip microcomputer extracts the maximum value, the minimum value and the average value in the current array, the current level information can be extracted through a dynamic comparison algorithm, and the method used by the dynamic comparison algorithm comprises the following steps: l (| A X X) (min) +B*X (max) +C*X (avg) )/D |<X (t) and: | X (t) -X (t-1) | Y>∆T 1 Wherein: d =2 (A + B + C), wherein A is the weight of the obtained minimum signal value in the calculation process, B is the weight of the obtained maximum signal value in the calculation process, C is the weight of the obtained average value in the calculation process, D is 2 times of the sum of the weights A, B and C, the threshold value of the center point of the dynamic signal can be obtained by dividing D in the formula, the weights A, B and C are properly adjusted according to the actual data acquisition waveform, and T is T 1 Obtaining the minimum threshold value when data are turned in practical experiment, wherein the threshold value is acquired according to the effective turning signal of practical testTwo thirds of the difference between two adjacent AD values of the set. After the analysis by the method, the low-frequency current interference caused by parasitic capacitance, parasitic inductance and the like on the MBUS bus can be filtered, and the corresponding communication signal data can be output through the comparison and judgment to complete the data analysis. The amplitude filtering algorithm and the dynamic comparison algorithm can be realized by the single chip microcomputer through the existing computer program.
In general, when the current of the MBUS bus of the on-site MBUS bus, such as a water meter, is calculated according to the consumption of 1.5mA current of each path of slave, the access communication capability of slave equipment with more than 800 paths can be realized. The device can also achieve better effect in the actual use process for the existing instruments with larger power, such as a gas detector and the like. The utility model discloses avoided because of the great unable condition that realizes two bus MBUS communications of instrument power, simultaneously, also for the instrument of big point position low-power consumption like water gauge, cigarette feel etc. provide the solution that the cost is lower.
The above description is only for the preferred embodiment of the present invention, and should not be taken as limiting the invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. A high-capacity MBUS host receiving circuit based on a single chip microcomputer comprises a signal conversion circuit and is characterized in that the signal conversion circuit is connected with a signal clamping circuit, the signal clamping circuit is connected with a signal amplification circuit, and the signal amplification circuit is connected with the single chip microcomputer.
2. The single-chip microcomputer-based high-capacity MBUS host receiving circuit according to claim 1, wherein the signal conversion circuit is connected with a signal isolation circuit, and the signal isolation circuit is connected with a signal clamping circuit.
3. The single-chip microcomputer-based high-capacity MBUS host receiving circuit according to claim 2, wherein the signal conversion circuit comprises a sampling resistor R1, one end of the sampling resistor R1 is connected with the MBUS current signal, and the other end is grounded; the sampling resistor R1 is connected with a diode D1 in parallel; the signal isolation circuit comprises an isolation capacitor C1, and two ends of the isolation capacitor C1 are respectively connected with the MBUS current signal and the signal clamping circuit.
4. The single-chip microcomputer-based high-capacity MBUS host receiving circuit according to claim 2 or 3, wherein the signal clamping circuit comprises a resistor R2 and a resistor R3, one end of the resistor R2 and one end of the resistor R3 are both connected with an isolation capacitor C1 of the signal isolation circuit, the other end of the resistor R2 is connected with a power supply, and the other end of the resistor R3 is grounded.
5. The single-chip microcomputer based high-capacity MBUS host receiving circuit according to claim 4, wherein the signal amplifying circuit comprises an operational amplifier, the non-inverting input terminal of the operational amplifier is connected with one end of a resistor R2 and one end of a resistor R3 of the signal clamping circuit respectively, the inverting input terminal of the operational amplifier is connected with one end of a resistor R5 and one end of a resistor R6 respectively, the other end of the resistor R5 is grounded, and the other end of the resistor R6 is connected with the output terminal of the operational amplifier.
6. The single-chip microcomputer-based high-capacity MBUS host receiving circuit according to claim 5, wherein the non-inverting input terminal of the operational amplifier is connected with a resistor R4, and the resistor R4 is respectively connected with one end of a resistor R2 and one end of a resistor R3; the output end of the operational amplifier is connected with a resistor R7.
7. The high-capacity MBUS host receiving circuit based on the single chip microcomputer according to claim 5 or 6, wherein the input end of the single chip microcomputer is connected with a resistor R7 of a signal amplifying circuit, and the signal output end of the single chip microcomputer outputs digital signals.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221568616.5U CN217741730U (en) | 2022-06-22 | 2022-06-22 | High-capacity MBUS host computer receiving circuit based on singlechip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202221568616.5U CN217741730U (en) | 2022-06-22 | 2022-06-22 | High-capacity MBUS host computer receiving circuit based on singlechip |
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| CN217741730U true CN217741730U (en) | 2022-11-04 |
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| CN202221568616.5U Active CN217741730U (en) | 2022-06-22 | 2022-06-22 | High-capacity MBUS host computer receiving circuit based on singlechip |
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