CN217739896U - Intelligent calculation module circuit, calculation board card and computer - Google Patents
Intelligent calculation module circuit, calculation board card and computer Download PDFInfo
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- CN217739896U CN217739896U CN202221948422.8U CN202221948422U CN217739896U CN 217739896 U CN217739896 U CN 217739896U CN 202221948422 U CN202221948422 U CN 202221948422U CN 217739896 U CN217739896 U CN 217739896U
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Abstract
The application discloses an intelligent computing module circuit, a computing board card and a computer, based on the implementation scheme of the embodiment of the application, the computing board card provided by the application is provided with the intelligent computing module circuit which can adapt to various logic controls and improve the reusability of the computing board card, the intelligent computing module circuit is connected with a high-speed connector through a communication bus, and then is respectively communicated with a fusion board card and a bearing plate through the high-speed connector, so that information interaction among a computing layer, the bearing layer and the fusion layer is realized, the intelligent computing module circuit is a main communication data processing circuit of the computing board card, management chips such as BMC/CPLD/PCH are configured, different logic control functions are added for the computing board card, the computing board card can adapt to various logic controls, and the reusability of the computing board card is improved. In addition, an external debugging interface is also provided for debugging the mainboard of the computing board card, so that the integrated debugging of the computing board card is facilitated, the computing board card is more open and can provide debugging conditions for various computing models more flexibly, and the adaptability is enhanced.
Description
Technical Field
The application relates to the technical field of computers, in particular to an intelligent computing module circuit, a computing board card and a computer.
Background
Many devices in the industry currently require boards to operate, such as computing boards, and basically, each computing board has a unique configuration and is different. For different devices, device integrators will have to develop different computing boards for different computers, which results in extremely low reusability of the computing boards and inability to reuse the computing boards.
For the reasons, the number of each type of computer board card is difficult to form an ultra-large scale, but a matched computer must be replaced according to different application scenarios, so as to achieve performance maximization of the whole equipment level. This means that medium and small equipment integrators have to continuously develop various boards of different computer specifications and different series. More difficult, it is possible that the small and medium device integrators do not have the technology accumulation in a certain field or fields, and then have to spend a lot of money on creating their own teams, or outsource the boards of a specific function set to a third party who is more interested in a certain computer technology or technologies. However, for outsourcing a third party board, there may be an inconsistency of the level of software and hardware cooperation optimization. For technical and business related reasons or for technical protection, most third party boards are not willing to completely open the core software and hardware interfaces inside the board to the integrating party, let alone to another third party. Such a situation easily causes partial function overlapping of third-party function boards from different homes, or causes repetition of data interaction procedures, which in fact easily causes damage to the performance of the computer.
Therefore, how to improve the reusability of the computing board and adapt to various computing environments to achieve a more intelligent, more open and more flexible solution for providing more optimized solutions for various future computing models is a technical direction that needs to be considered by the computing board at present.
SUMMERY OF THE UTILITY MODEL
The main purpose of the present application is to provide an intelligent computing module circuit, a computing board and a computer, so as to solve the current problems.
In order to achieve the above object, the present application provides the following techniques:
a first aspect of the present application provides an intelligent computing module circuit, comprising:
a memory;
a processor;
a communication bus;
a high-speed connector;
a management chip;
the memory is electrically connected with the processor;
the processor is electrically connected with the high-speed connector through the communication bus, and the high-speed connector is electrically connected with the fusion board card;
the management chip is electrically connected between the processor and the carrier plate.
As an optional implementation of the present application, optionally, the memory is a ddr a memory slot.
As an optional embodiment of the present application, optionally, the processor includes a processor-1 and a processor-2 that are arranged in parallel, and the processor-1 and the processor-2 are electrically connected to one of the memories, respectively.
As an optional embodiment of the present application, optionally, the communication bus comprises at least one PCI Express x 16 high speed bus, at least one DMI bus, at least one PCI Express x 1 high speed bus, and at least one LPC bus, wherein:
the output end of the processor is electrically connected with the high-speed connector through the PCI Express x 16 high-speed bus, and the other output end of the processor is electrically connected with the management chip through the DMI bus.
As an optional embodiment of the present application, optionally, the high-speed connector includes a high-speed connector-1 and a high-speed connector-2 that are arranged in parallel, and the high-speed connector-1 and the high-speed connector-2 are electrically connected to the fusion board respectively.
As an optional embodiment of the present application, optionally, the processor comprises a processor-1 and a processor-2 arranged in parallel, and the high-speed connector comprises a high-speed connector-1 and a high-speed connector-2 arranged in parallel; wherein:
the processor-1 is electrically connected with the high-speed connector-1 through a PCI Express x 16 high-speed bus, and the processor-2 is electrically connected with the high-speed connector-2 through a PCI Express x 16 high-speed bus.
As an optional embodiment of the present application, optionally, the management chip includes:
and the input end of the PCH chip is electrically connected with the output end of the processor-1 through the DMI bus, and the output end of the PCH chip is electrically connected with the bearing plate through a VGA-SATA-USB-PCIE pin of the PCH chip.
As an optional implementation of the present application, optionally, the communication bus further includes:
and the input end of the BMC chip is electrically connected with the side output end of the PCH chip through a PCI Express x 1 high-speed bus and an LPC bus, and the output end of the BMC chip is electrically connected with the bearing plate through an LAN-IPMI-UART pin of the BMC chip.
The second aspect of the application provides a calculation integrated circuit board, including the PCB board, be configured with the first aspect on the PCB board intelligent computing module circuit.
A third aspect of the present application provides a computer, including the computing board described in the second aspect.
Compared with the prior art, this application can bring following technological effect:
based on the implementation scheme of the embodiment of the application, the computing board provided by the application is provided with the intelligent computing module circuit which can adapt to various logic controls and improve the reusability of the computing board, the intelligent computing module circuit is connected with the high-speed connector through the communication bus and then respectively communicates with the fusion board and the bearing plate through the high-speed connector, information interaction among the computing layer, the bearing layer and the fusion layer is realized, the intelligent computing module circuit is a main communication data processing circuit of the computing board and is provided with management chips such as BMC/CPLD/PCH, different logic control functions are added for the computing board, the computing board can adapt to various logic controls, and the reusability of the computing board is improved. In addition, an external debugging interface is also provided for debugging the mainboard of the computing board card, so that the integrated debugging of the computing board card is facilitated, the computing board card is more open and can provide debugging conditions for various computing models more flexibly, and the adaptability is enhanced.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, serve to provide a further understanding of the application and to enable other features, objects, and advantages of the application to be more apparent. The drawings and their description illustrate the embodiments of the invention and do not limit it. In the drawings:
FIG. 1 is a schematic diagram of the application composition of the computer hardware of the present invention;
fig. 2 is a schematic diagram of the intelligent computing module circuit of the present invention.
Detailed Description
In order to make the technical solutions of the present application better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances in order to facilitate the description of the embodiments of the application herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In this application, the terms "upper", "lower", "left", "right", "front", "rear", "top", "bottom", "inner", "outer", "middle", "vertical", "horizontal", "lateral", "longitudinal", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings. These terms are used primarily to better describe the present application and its embodiments, and are not used to limit the indicated devices, elements or components to a particular orientation or to be constructed and operated in a particular orientation.
Moreover, some of the above terms may be used to indicate other meanings besides the orientation or positional relationship, for example, the term "on" may also be used to indicate some kind of attachment or connection relationship in some cases. The specific meaning of these terms in this application will be understood by those of ordinary skill in the art as appropriate.
In addition, the term "plurality" shall mean two as well as more than two.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
Example 1
The method redefines the computer hardware, and realizes perfect matching in the aspects of density, cost and flexibility by subdividing the computer hardware into a computing layer, a fusion layer and a bearing layer.
As shown in fig. 1, the computer hardware realizes the interaction and processing of data through a computation layer, a fusion layer and a carrying layer. When each layer of calculation layer, fusion layer and bearing layer are applied specifically, the calculation layer, the fusion layer and the bearing layer are realized through the corresponding calculation board card, fusion board card and bearing plate. Through the integrated board card application system, information interaction and high-speed network fusion are realized, various application networks can be fused and adapted, a more intelligent, more open and more flexible network scheme for various future computing models is provided, and the integration level of the fusion network card is improved.
According to the computing board card provided by the invention, the CPU processor, the memory, the high-speed connector, the power module, the BMC/CPLD/PCH management chip and the like are integrated on the PCB board, so that the data interaction butt joint can be realized through the high-speed connector, the bearing board and the fusion board card, meanwhile, different logic control functions can be added to the computing board card through the BMC/CPLD/PCH management chip and the like, the computing board card can be adaptive to various logic controls, and the reusability of the computing board card is improved. In addition, an external debugging interface is further provided for debugging the mainboard of the computing board card, so that the integrated debugging of the computing board card is facilitated, the computing board card is more open, debugging conditions are more flexibly provided for various computing models, and the adaptability is enhanced.
As shown in fig. 2, a first aspect of the present application provides a smart computing module circuit, including:
a memory; DDR4 memory slots are adopted and can be used as drive storage and data storage of the processor;
a processor; preferably, a CPU processor is adopted to process and return the information collected from the bearing plate and the melting board card through the high-speed connector, and the calculated information is stored;
a communication bus; as data lines, can be used to transmit data or as power supply lines for circuits;
a high speed connector; the communication interface of the computing board is a necessary communication interface on the board. The high-speed connector can set the interfaces thereof and the number of the interfaces corresponding to the connecting board cards according to the communication mode with different board cards. The interface of the high-speed connector needs to meet the principle of high integration, and realizes the butt-joint communication with different network board cards, and the interface definition can be set by a user;
a management chip; the intelligent computing module circuit is used as a control center of the intelligent computing module circuit and is used for logically forwarding information processed by the CPU;
the memory is electrically connected with the processor;
the processor is electrically connected with the high-speed connector through the communication bus, and the high-speed connector is electrically connected with the fusion board card;
the management chip is electrically connected between the processor and the carrier plate.
The present embodiment will describe an application in the power-on case.
As shown in fig. 2, in this embodiment, when the intelligent computing module circuit is implemented, the circuit is powered on, and the power circuit preferentially performs logic processing through the CPU processor. The high-speed connector is used as a data interface of the processor, and is used for receiving data from the fusion card (fusion layer)/the bearing plate (bearing layer), transmitting the data to the processor through a high-speed bus, storing the data in a memory bank configured in a memory slot after being processed by the processor, and returning the data to the fusion card (fusion layer)/the bearing plate (bearing layer). The data from the bearing plate can be logically operated through other independent management chips such as a PCH chip, after the data is transmitted from the bearing plate, the data is firstly processed through a processor, then the data is operated through the management chips such as the PCH chip, and the data returns to the bearing plate after operation.
The high-speed connector is used as a data interface, and the interface (pin) of the high-speed connector is defined according to the type of a processor chip or the type of a functional board card which is configured by being plugged with the high-speed connector, for example, the interface of a carrier layer and a computation layer is defined as shown in table 1 below:
TABLE 1 interface definition of bearer layer and compute layer
The definition interface is only the preferred definition interface provided in this embodiment, and may be configured by a user according to a configured board type or a configured processing chip model.
As an optional implementation of the present application, optionally, the memory is a ddr a memory slot. In order to improve the storage capacity, at least one DDRA memory slot is configured for each CPU processor.
As an optional embodiment of the present application, optionally, the processor includes a processor-1 and a processor-2 that are arranged in parallel, and the processor-1 and the processor-2 are electrically connected to one of the memories, respectively.
Preferably, as shown in FIG. 2, each CPU processor is configured with six DDRA memory slots, wherein ABCDEF- -DDRA memory slot is configured to CPU processor-1, GHJKLM- -DDRA memory slot is configured to CPU processor-2.
In this embodiment, the board card of the bearing layer is dedicated to power supply and input/output ports; the board card of the calculation layer is focused on calculation and resource allocation; therefore, 1 group of kilomega network, 8 groups of PCIE/SATA, one group of PCIE, one group of SATA,2 groups of USB3.0, one group of VGA, IPMI bus and power supply and control signal line are defined on the interface of the intelligent computing module circuit and the bearing plate. The board card of the fusion layer is focused on data transmission (how external data is transmitted to a CPU for calculation) and special data processing (graphic processing, AI training, algorithm operation and the like), so that 32 pairs of high-speed data buses are defined on the interface of the intelligent computing module circuit and the fusion card, the high-speed data buses are typically applied to 2 groups of PCI Express x 16 high-speed buses, one group of IPMI management buses, a power supply and a control signal line, and most application requirements are met. Specifically, the method comprises the following steps:
as an optional embodiment of the present application, optionally, the communication bus comprises at least one PCI Express x 16 high speed bus, at least one DMI bus, at least one PCI Express x 1 high speed bus, and at least one LPC bus, wherein:
the output end of the processor is electrically connected with the high-speed connector through the PCI Express x 16 high-speed bus, and the other output end of the processor is electrically connected with the management chip through the DMI bus.
As an optional embodiment of the present application, optionally, the high-speed connector includes a high-speed connector-1 and a high-speed connector-2 that are arranged in parallel, and the high-speed connector-1 and the high-speed connector-2 are electrically connected to the fusion board respectively.
As an optional embodiment of the present application, optionally, the processor comprises a processor-1 and a processor-2 arranged in parallel, and the high-speed connector comprises a high-speed connector-1 and a high-speed connector-2 arranged in parallel; wherein:
the processor-1 is electrically connected with the high-speed connector-1 through a PCI Express x 16 high-speed bus, and the processor-2 is electrically connected with the high-speed connector-2 through a PCI Express x 16 high-speed bus.
The high-speed connector-1 and the high-speed connector-2 are arranged in parallel in the circuit and are used as communication interfaces of the processor-1 and the processor-2 respectively.
The CPU processor chip is processed on the computing board card, and other management chips which can run independently are arranged on the computing board card. Such as PCH bridge chip, BMC board level management controller and CPLD time sequence control chip, can deal with different logic management needs and corresponding data processing calculation.
As shown in fig. 2, as an optional embodiment of the present application, optionally, the management chip includes:
and the input end of the PCH chip is electrically connected with the output end of the processor-1 through the DMI bus, and the output end of the PCH chip is electrically connected with the bearing plate through a VGA-SATA-USB-PCIE pin of the PCH chip.
The PCH chip is mainly a PCH bridge chip and is mainly used for I/O control; the input end of the PCH chip is electrically connected with the output end of a DMI bus processor-1, and the output end of the PCH chip is electrically connected with the bearing plate through VGA-SATA-USB-PCIE pins (pins mainly used in plugging).
As an optional implementation of this application, optionally, the communication bus further includes:
and the input end of the BMC chip is electrically connected with the side output end of the PCH chip through a PCI Express x 1 high-speed bus and an LPC bus, and the output end of the BMC chip is electrically connected with the bearing plate through an LAN-IPMI-UART pin of the BMC chip.
The BMC chip is mainly a BMC board level management controller, is used for basic circuit control of the intelligent computing module circuit and is mainly an independent auxiliary control circuit. The BMC chip is connected in series between the PCH bridge chip and the bearing plate, the input end of the BMC chip is electrically connected with the side output end of the PCH chip through a PCI Express x 1 high-speed bus and an LPC bus, and the output end of the BMC chip is electrically connected with the bearing plate through an LAN-IPMI-UART pin of the BMC chip.
The BMC board level management controller can handle different logic management needs and corresponding data processing calculations.
The PCH bridge chip and the BMC board level management controller may be configured and used on the computing board individually, or may be used in series, for example, the PCH chip is connected in series between the CPU processor of the computing board and the carrier board, so that the data computed by the processor is subjected to secondary logic operation by the PCH chip and then sent to the carrier board. The BMC chip can be used as an auxiliary management function of the PCH chip, and the bearing plate can be connected in series through a pin of the PCH chip.
The functions of the PCH bridge and the BMC board level management controller are not described in detail in this embodiment. The specific selection type of chips such as the PCH bridge chip and the BMC board level management controller is not limited in this embodiment.
Example 2
The second aspect of the application provides a calculation integrated circuit board, including the PCB board, be configured with the first aspect on the PCB board intelligent computing module circuit.
In this embodiment, the intelligent computing module circuit described in the first aspect is configured on the PCB of the computing board, so that the computing board has the function of the application circuit described in embodiment 1. For specific applications see the description of example 1.
Example 3
A third aspect of the present application provides a computer, including the computing board described in the second aspect.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A smart computing module circuit, comprising:
a memory;
a processor;
a communication bus;
a high-speed connector;
a management chip;
the memory is electrically connected with the processor;
the processor is electrically connected with the high-speed connector through the communication bus, and the high-speed connector is electrically connected with the fusion board card;
the management chip is electrically connected between the processor and the carrier plate.
2. The smart computing module circuit of claim 1, wherein the memory is a DDRA memory slot.
3. The smart computing module circuit of claim 1, wherein the processor comprises a processor-1 and a processor-2 arranged in parallel, each of the processor-1 and the processor-2 being electrically coupled to one of the memories.
4. The smart computing module circuit of claim 3, wherein the communication bus comprises at least one PCI Express x 16 high speed bus, at least one DMI bus, at least one PCI Express x 1 high speed bus, and at least one LPC bus, wherein:
the output end of the processor is electrically connected with the high-speed connector through the PCI Express x 16 high-speed bus, and the other output end of the processor is electrically connected with the management chip through the DMI bus.
5. The intelligent computing module circuit of claim 1, wherein the high-speed connectors comprise a high-speed connector-1 and a high-speed connector-2 arranged in parallel, and the high-speed connector-1 and the high-speed connector-2 are respectively electrically connected with the fusion board.
6. The smart computing module circuit of claim 5, wherein the processor comprises a processor-1 and a processor-2 arranged in parallel, the high speed connectors comprising a high speed connector-1 and a high speed connector-2 arranged in parallel; wherein:
the processor-1 is electrically connected with the high-speed connector-1 through a PCI Express x 16 high-speed bus, and the processor-2 is electrically connected with the high-speed connector-2 through a PCI Express x 16 high-speed bus.
7. The smart computing module circuit as recited in claim 4, wherein the management chip comprises:
and the input end of the PCH chip is electrically connected with the output end of the processor-1 through the DMI bus, and the output end of the PCH chip is electrically connected with the bearing plate through a VGA-SATA-USB-PCIE pin of the PCH chip.
8. The smart computing module circuit of claim 7, wherein the communication bus further comprises:
and the input end of the BMC chip is electrically connected with the side output end of the PCH chip through a PCI Express x 1 high-speed bus and an LPC bus, and the output end of the BMC chip is electrically connected with the bearing plate through an LAN-IPMI-UART pin of the BMC chip.
9. A computing board comprising a PCB board on which the smart computing module circuit of any of claims 1-8 is configured.
10. A computer comprising the computing board of claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221948422.8U CN217739896U (en) | 2022-07-27 | 2022-07-27 | Intelligent calculation module circuit, calculation board card and computer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221948422.8U CN217739896U (en) | 2022-07-27 | 2022-07-27 | Intelligent calculation module circuit, calculation board card and computer |
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| Publication Number | Publication Date |
|---|---|
| CN217739896U true CN217739896U (en) | 2022-11-04 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202221948422.8U Active CN217739896U (en) | 2022-07-27 | 2022-07-27 | Intelligent calculation module circuit, calculation board card and computer |
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| Country | Link |
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| CN (1) | CN217739896U (en) |
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- 2022-07-27 CN CN202221948422.8U patent/CN217739896U/en active Active
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