CN217693905U - PCIE golden finger and electroplating lead structure thereof - Google Patents

Abstract

The utility model provides a PCIE golden finger and an electroplating lead structure thereof, wherein the golden finger comprises a ground network golden finger and a non-ground network golden finger which are arranged on a PCB board, and the ground network golden finger is connected with a ground hole positioned on the first side of the ground network golden finger; the electroplating lead structure comprises: the first electroplating bus and the first electroplating branch line are arranged on the PCB; the first electroplating bus connects all ground holes on the first side of the golden finger together and extends out of a second side edge and/or a third side edge of the PCB, wherein the second side edge and the third side edge are two opposite side edges of the PCB; the first plating branch connects one or more of the non-ground network gold fingers to a first plating bus. The electroplating lead wire of the golden finger is simple in structure, and the residual lead wires on the PCB are few.

Description

PCIE golden finger and electroplating lead structure thereof

Technical Field

The utility model belongs to the electronic equipment field, concretely relates to PCIE golden finger and electroplate pin configuration thereof.

Background

This section is intended to provide a background or context to the embodiments of the invention that are recited in the claims. The description herein is not admitted to be prior art by inclusion in this section.

The gold finger (connecting finger) refers to a plurality of conductive copper sheets manufactured on the top and bottom surfaces of the PCB, and is called a gold finger because of the arrangement shape like a finger, and is used for connecting components such as a memory bar, a display card and the like with the slot. In order to improve the oxidation resistance of the gold finger and reduce the contact resistance, a layer of gold is electroplated on the surface of the copper sheet. In order to realize gold finger gold electroplating, a lead is designed on the gold finger and extends to the edge of the plate, and the lead is electrified to realize gold finger gold electroplating. However, the wire of this design needs to be removed as much as possible after the plating is completed, so as to avoid affecting the appearance or the quality of the high-speed signal.

In the prior art, the electroplated lead structure is usually long, and the residual lead of the gold finger is usually removed by a chemical etching method or a mechanical grinding method. However, the mechanical planarization method cannot effectively remove the lead residue of the short gold finger such as PCIE GEN5 gold finger, and the chemical etching process for removing the residual lead is complex and expensive.

Therefore, how to design a plating lead structure with a simple structure and a shorter length is an urgent problem to be solved.

SUMMERY OF THE UTILITY MODEL

In order to solve the problems in the prior art, a PCIE gold finger and an electroplating lead structure thereof are provided, and the problems can be solved by using the structure.

The utility model provides a following scheme.

In a first aspect, an electroplating lead structure of a PCIE gold finger is provided, where the gold finger includes a ground network gold finger and a non-ground network gold finger that are disposed on a PCB board, and the ground network gold finger is connected to a ground hole located on a first side of the ground network gold finger; the electroplating lead structure comprises: the first electroplating bus and the first electroplating branch line are arranged on the PCB; the first electroplating bus connects all ground holes on the first side of the golden finger together and extends out of a second side edge and/or a third side edge of the PCB, wherein the second side edge and the third side edge are two opposite side edges of the PCB; the first plating branch connects one or more of the non-ground network gold fingers to the first plating bus.

In one embodiment, in the case of completion of electroplating, a disconnecting structure for disconnecting the connection between the non-ground network gold finger and the first electroplating bus is arranged on the first electroplating branch line at a position close to the non-ground network gold finger.

In an embodiment, the intercepting structure comprises a pore structure.

In one embodiment, the method further comprises: the first electroplating bus is formed into an integrated metal sheet; or, the first electroplating bus is formed as a split type metal sheet, and the split type metal sheet includes: the metal sheet comprises a middle section metal sheet arranged between adjacent ground holes, a second side metal sheet extending out of one or more ground holes on the first side of the golden finger to the second side edge of the PCB board, and/or a third side metal sheet extending out of one or more ground holes on the first side of the golden finger to the third side edge of the PCB board.

In one embodiment, the first plating branch comprises: leads extending from the non-ground net fingers in a first direction and connected to the first plating bus.

In one embodiment, the PCIE gold finger includes: a PCIE GEN5 gold finger and/or a PCIE GEN6 gold finger.

In a second aspect, an electroplating lead structure of a PCIE gold finger is provided, where the gold finger includes a ground network gold finger and a non-ground network gold finger that are disposed on a PCB, and the ground network gold finger is connected to a ground via located on a first side of the ground network gold finger; the electroplating lead structure comprises: a second electroplating bus and a second electroplating branch line which are arranged on the PCB; wherein the second plating bus comprises at least: a second side electroplating bus extending from the one or more ground holes of the first side of the gold finger to a second side edge of the PCB board, and/or a third side electroplating bus extending from the one or more ground holes of the first side of the gold finger to a third side edge of the PCB board, wherein the second side edge and the third side edge are two opposite side edges of the PCB board; and the second electroplating branch line is used for connecting the non-ground network gold finger to one or more ground holes adjacent to the non-ground network gold finger so as to electrically connect the non-ground network gold finger to the second side electroplating bus and/or the third side electroplating bus.

In an embodiment, when the electroplating is completed, a disconnecting structure for disconnecting the electrical connection between the non-ground network gold finger and the second electroplating bus is arranged on the second electroplating branch line at a position close to the non-ground network gold finger.

In an embodiment, the intercepting structure is a pore structure.

In one embodiment, the second plating branch comprises: the bent lead is connected from the non-ground net gold finger to a second adjacent ground hole adjacent to the non-ground net gold finger, and/or the bent lead is connected from the non-ground net gold finger to a first adjacent ground hole adjacent to the non-ground net gold finger, wherein the first adjacent ground hole is close to the first side edge of the PCB board relative to the non-ground net gold finger (12), and the second adjacent ground hole is close to the second side edge of the PCB board relative to the non-ground net gold finger (12).

In one embodiment, the PCIE gold finger includes: a PCIE GEN5 gold finger and/or a PCIE GEN6 gold finger.

In a third aspect, a PCIE gold finger is provided, including: a lead structure as in the first or second aspect is utilized.

One of the advantages of the above-mentioned embodiment is that the structure of the plated lead structure disposed on the PCB is simple and the lead is short, so that the workload and difficulty required for subsequently cutting or removing the lead are less, and the performance of the high-speed signal carried by the gold finger is more easily prevented from being affected by excessive residual leads.

Other advantages of the present invention will be explained in more detail in conjunction with the following description and the accompanying drawings.

It should be understood that the above description is only an overview of the technical solutions of the present invention, so that the technical means of the present invention can be more clearly understood, and thus can be implemented in accordance with the contents of the specification. In order to make the above and other objects, features and advantages of the present invention more comprehensible, embodiments of the present invention are described in detail below.

Drawings

The advantages and benefits, and other advantages and benefits, herein will become apparent to those of ordinary skill in the art upon reading the following detailed description of the exemplary embodiments. The drawings are only for purposes of illustrating exemplary embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like elements throughout. In the drawings:

fig. 1 is a schematic structural diagram of a PCIE gold finger;

fig. 2 is a schematic structural diagram of a plating lead structure of a PCIE gold finger according to the prior art;

fig. 3 is a schematic structural diagram of an electroplating lead structure of a PCIE gold finger according to an embodiment of the present invention;

fig. 4 is a schematic structural view of a drilled electroplating lead structure of a PCIE gold finger according to an embodiment of the present invention;

fig. 5 is a schematic structural view of an electroplating lead structure of a PCIE gold finger according to another embodiment of the present invention;

fig. 6 is a schematic structural view of a drilled electroplating lead structure of a PCIE gold finger according to another embodiment of the present invention;

in the drawings, like or corresponding reference characters designate like or corresponding parts.

Wherein the symbols in the drawings are briefly described as follows:

a ground network golden finger-11; non-terrestrial network golden finger-12; a ground hole-13; lead-1'; copper sheet-14; third side edge-15 of PCB board; a first electroplating bus-31; a first plating branch-32; -a hole-33; a second plating bus-51; third side plating bus-511; a second plating branch-52; a first adjacent well-131; a second adjacent ground hole-132; pore-53.

DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the description of the embodiments of the present application, it is to be understood that terms such as "including" or "having" are intended to indicate the presence of the features, numbers, steps, actions, components, parts, or combinations thereof disclosed in the specification, and are not intended to preclude the presence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

A "/" indicates an OR meaning, for example, A/B may indicate A or B; "and/or" herein is merely an association describing an associated object, and means that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone.

The terms "first", "second", and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present application, the meaning of "a plurality" is two or more unless otherwise specified.

For clarity of the description of the embodiments of the present application, some concepts that may appear in subsequent embodiments will first be described.

Description of concepts

PCIE (peripheral component interconnect express) refers to an abbreviation of the high-speed serial computer expansion bus standard. PCIE GEN5 refers to the 5 th generation PCIE technology, PCIE GEN6 refers to the 6 th generation PCIE technology.

The gold finger (connecting finger) refers to a plurality of conductive copper sheets manufactured on the top and bottom surfaces of the PCB, and is called a gold finger because of the arrangement shape like a finger, and is used for connecting components such as a memory bar, a display card and the like with the slot. In order to improve the oxidation resistance of the gold finger and reduce the contact resistance, a layer of gold is electroplated on the surface of the copper sheet.

Fig. 1 shows a conventional PCIE gold finger design architecture. It can be understood that the PCIE gold finger architecture shown in fig. 1 may be a gold finger architecture specified by PCIE GEN5 version, or may also be a gold finger architecture specified by PCIE GEN6 and subsequent versions, as long as the gold finger architecture is similar to the gold finger architecture shown in fig. 1, which is not specifically limited in this application.

Referring to fig. 1, the gold finger design includes a plurality of land network gold fingers 11 and a plurality of non-land network gold fingers 12, wherein a plurality of land holes 13 are formed in a first side of the whole gold finger, two land holes 13 are formed in the first side of each land network gold finger 11, and a plurality of independent land holes 13 are formed in addition, the lengths of the land network gold fingers 11 and the non-land network gold fingers 12 are different, and therefore, the land network gold fingers 101 and the non-land network gold fingers 102 are in a state of uneven depth on the first side of the gold fingers.

In fig. 1, the lower side in the drawing is described as the "first side" by way of example, but is not limited thereto. It is understood that the "first side" in this embodiment is specifically one side of the gold finger in the length direction thereof.

It can be understood that, in order to implement gold finger electroplating, a wire needs to be designed on a gold finger to extend to the edge of a board, the wire is subjected to anti-electroplating treatment, and the wire is electrified to implement gold finger electroplating. But the wire of this design needs to be removed after plating is completed to avoid affecting the appearance or quality of the high speed signal.

Referring to fig. 2, the manner of gold plating and removal of the residual wire used in the prior art is as follows: firstly, a plating lead 1' is processed on the golden finger. The electroplating lead is led out from the lower part of each golden finger and is connected together in the transverse direction. And then, carrying out anti-electroplating treatment on the lead, and electrifying the processed electroplating lead to carry out golden finger electroplating. Finally, the residual lead of the PCIE gold finger can be removed by a chemical etching method or by a mechanical planarization method.

However, the length of the plating lead 1' is very long, which brings inconvenience to subsequent lead cutting or lead clearing work, and since all non-ground network gold fingers in a PCIE gold finger designed according to the PCIE GEN5 protocol are shorter than ground network gold fingers, lead residue of the short gold finger cannot be effectively removed by a beveling machine. The chemical etching method for removing the residual lead wire has complex processing technique and high price.

To address, at least in part, one or more of the above issues and other potential issues, an example embodiment of the present disclosure proposes a plated lead structure of a PCIE gold finger.

In this way, by changing the design mode of the gold finger electroplating lead and adopting the drilling, the PCIE gold finger is manufactured by a simple electroplating processing technology of the PCIE gold finger, and the residual lead on the PCB is less.

The present invention will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Fig. 3 shows a plating lead structure of a PCIE gold finger of the present embodiment; fig. 4 shows a structure of the embodiment after drilling the electroplating lead structure of the PCIE gold finger of fig. 3.

The following explains embodiments of the present application in detail with reference to fig. 3 and 4.

Referring to fig. 3, a PCIE gold finger is disposed on the PCB, where the gold finger includes a plurality of ground network gold fingers 11 and a plurality of non-ground network gold fingers 12, and a plurality of ground holes 13 are disposed on a first side of the whole gold finger, where two ground holes 13 are disposed on a first side of each ground network gold finger 11, and an independent ground hole 13 is further disposed on a first side of the non-ground network gold finger 12. The description will be given by taking the lower side in fig. 3 and 4 as the first side, but the invention is not limited thereto. The first side in this embodiment may refer to one side of the gold finger in the length direction thereof.

In order to construct the electroplating lead structure, the ground network golden finger 11 is connected with a ground hole 13 on the first side of the ground network golden finger, and particularly can be connected through a copper sheet 14; and, a first electroplating bus 31 is provided on the PCB, the first electroplating bus 31 connects all the ground holes 13 of the first side of the gold finger together in a transverse direction, and extends out of a second side edge (not shown) and/or a third side edge 15 of the PCB, wherein the part extending out of the second side edge or the third side edge of the PCB is used for connecting external electroplating wires, and the second side edge and the third side edge are two opposite side edges of the PCB. Thereafter, a first plating branch 32 is provided on the PCB board, the first plating branch 32 connecting each of the non-ground net gold fingers 12 to the first plating bus 31.

Thus, the structure of the plating lead can be completed. It can be seen that under this plating lead configuration, the first plating bus 31 is electrically connected to all of the non-ground network gold fingers 12 through the first plating branch 32. Moreover, compared with the prior art, the plating structure constructed in the scheme of fig. 3 has fewer leads and a simple structure.

For the plated lead structure as shown in fig. 3, an actual gold plating work may be performed, and the gold finger is plated using the first plating bus 31 and the first plating branch 32. Specifically, current can be conducted from the portion of the first plating bus 31 extending out of the edge of the PCB board, whereby gold plating of the gold finger can be achieved.

Referring to fig. 4, in the event plating is complete, a hole 33 may be drilled directly into the first plating branch 32 to sever the connection of each non-ground network gold finger 12 and the first plating bus 31. In this state, a cutoff structure for cutting off the connection between the non-geonet golden finger (11) and the first electroplating bus (31) is arranged on the first electroplating branch line (32) at a position close to the non-geonet golden finger (12).

In one embodiment, the intercepting structure is a hole (34) structure.

Thus, by constructing the gold finger plated lead structure as shown in fig. 3, it is possible to break the electrical connection of the non-ground net gold finger to the ground net using only a simple process such as drilling, and at the same time, there are fewer residual leads on the PCB board.

It is to be understood that the first plating bus 31 described above refers to a combination of conductive structures that connect all of the ground vias 13 of the first side of the gold finger together.

In one embodiment, referring to fig. 3, the first plating bus 31 is formed as a split metal sheet comprising: the connecting structure comprises a plurality of middle section metals erected between adjacent ground holes on the first side of the golden finger, a second side metal sheet extending out of the second side edge of the PCB from the ground hole on the first side of the golden finger, and a third side metal sheet extending out of the third side edge of the PCB from the ground hole on the first side of the golden finger.

Alternatively, in other embodiments, the first plating bus may be formed as a single metal sheet, two ends of which extend out of the second side edge and/or the third side edge of the PCB board, and a middle portion of which may connect each ground hole 13 of the first side of the gold finger at the same time. This is not particularly limited by the present application.

In one embodiment, the first plating branch 32 includes: the leads respectively extending from the one or more non-ground network fingers 12 in a first direction and connected to the first plating bus, e.g., in fig. 3, the first plating branch 32 is a combination of a plurality of parallel wires. The first direction is a direction from the non-terrestrial network gold finger to the first side.

In one embodiment, a hole 33 may be drilled into the first plating branch 32 at a location proximate to the non-ground network gold finger 12. Specifically, the hole is positioned as close as possible to the gold finger without damaging the gold finger, which can improve high-speed signal quality.

In an embodiment, the PCIE gold finger is a PCIE GEN5 gold finger, a PCIE GEN6 gold finger, or an upgraded PCIE gold finger having the same or similar gold finger architecture, which is not specifically limited in this application.

Fig. 5 shows another electroplating lead structure of a PCIE gold finger of the embodiment; fig. 6 shows the structure of the embodiment after the holes are drilled in the electroplated lead structure of the PCIE gold finger of fig. 5.

The following explains embodiments of the present application in detail with reference to fig. 5 and 6.

Referring to fig. 5, a PCIE gold finger is disposed on the PCB, where the gold finger includes a plurality of ground network gold fingers 11 and a plurality of non-ground network gold fingers 12, and a first side of the whole gold finger is disposed with a plurality of ground holes 13, where a first side of each ground network gold finger 11 is disposed with two ground holes 13, and a first side of the non-ground network is further disposed with an independent ground hole 13. The description will be given taking the lower side in fig. 5 and 6 as the first side, but the invention is not limited thereto. The first side in this embodiment may refer to one side of the gold finger in the length direction thereof. In order to construct the electroplating lead structure, firstly, the ground network golden finger 11 is connected with a ground hole 13 on a first side thereof, and particularly, the connection can be carried out through a copper sheet 14; a second electroplating bus 51 is disposed on the PCB, and the second electroplating bus 51 at least includes: a second side plating bus (not shown) extending from the one or more ground holes 13 of the first side of the gold finger out of the second side edge of the PCB board, and/or a third side plating bus 511 extending the one or more ground holes 13 of the first side of the gold finger out of the third side edge 15 of the PCB board. And, the second side plating bus (not shown) and the third side plating bus 511 extend out of the PCB for conducting electricity in the subsequent gold plating.

A second plating branch 52 is provided on the PCB board, the second plating branch 52 connects the non-ground net gold finger 12 to the ground hole 13 adjacent to the non-ground net gold finger 12, so that the non-ground net gold finger 12 is electrically connected to the second side plating bus and/or the third side plating bus

Specifically, the second plating branch 52 may connect the non-ground network gold finger 12 of the gold fingers to the first and/or second adjacent ground vias adjacent thereto to electrically connect the non-ground network gold finger to the second and/or third side plating buses.

For example, for a certain non-terrestrial network gold finger 12 in fig. 5, which has a first adjacent terrestrial hole 131 and a second adjacent terrestrial hole 132 adjacent to the certain non-terrestrial network gold finger, the second plating branch 52 can connect the certain non-terrestrial network gold finger 12 and the first adjacent terrestrial hole 131 and the second adjacent terrestrial hole 132 adjacent to the certain non-terrestrial network gold finger together at the same time. It will be appreciated that if each of the non-ground network gold fingers 12 is connected to adjacent first and/or second adjacent ground vias via the second plating branch 52 at the same time, the plated lead structure shown in fig. 5 will have the same electrical connection effect as the plated lead structure shown in fig. 3.

However, in the present embodiment, the second plating branch line 52 connects the non-ground net gold finger 12 and the ground via 13 in three connection manners shown as a, b, and c, i.e. a: the non-ground net gold finger 12 is connected to a second adjacent ground via 132 via a second plating branch 52, b: the non-ground net gold finger 12 connects the first adjacent ground via 131 through the second plating branch 52, and c: the non-ground network gold finger 12 connects the second adjacent ground via 132 and the first adjacent ground via 131 simultaneously through the second plating branch 52. Any manner may be selected according to the actual situation as long as it is possible to make any one of the non-ground network gold fingers 12 electrically connected to the second side plating bus (not shown) and/or the third side plating bus 511.

Thus, the plating lead structure can be completed. It can be seen that under this plated lead configuration, the second plating bus 51 is electrically connected to all of the non-ground network gold fingers 12 through the second plating branch 52. In addition, compared with the prior art, the plating lead in the scheme of fig. 5 has shorter length and simple structure.

After the plating lead structure shown in fig. 5 is constructed, the actual gold plating work is performed, and the gold finger is plated using the second plating bus 51 and the second plating branch 52. Specifically, current may be conducted from the portion of the second side plating bus (not shown) and/or the third side plating bus 511 extending out of the PCB board, whereby gold plating of the gold finger may be achieved.

Referring to fig. 6, after plating is complete, holes 53 are drilled directly into the second plating branch 52 to break the electrical connection between the ungrounded web fingers 12 and the second plating bus 51.

Therefore, by changing the structure of the gold finger electroplating lead, the electrical connection between the non-ground network gold finger and the ground network can be disconnected by using a simple process such as drilling, the electroplating processing process of the PCIE gold finger is completed, and meanwhile, the residual lead on the PCB is less. However, it will be appreciated that other removal schemes may be less labor intensive due to the shorter length of the plated lead structure.

In one embodiment, referring to fig. 5, the second plating branch 52 comprises: a meander lead connected from one or more non-ground network fingers 12 to an adjacent second adjacent ground via, respectively, and/or a meander lead connected from one or more non-ground network fingers to an adjacent first adjacent ground via 131, respectively. The first adjacent ground hole 131 is close to the first side edge of the PCB board opposite to the non-terrestrial network gold finger 12, and the second adjacent ground hole 132 is close to the second side edge of the PCB board opposite to the non-terrestrial network gold finger 12.

Specifically, before the actual gold plating work is performed, the plating resist process may also be performed on the second plating bus 51 and the second plating branch line 52.

In one embodiment, holes may be drilled in the second plating branch 52 at locations near the non-ground network fingers. Specifically, the position of the drill hole is as close to the golden finger as possible on the premise of not damaging the golden finger, so that the high-speed signal quality can be improved.

Referring to fig. 3, an embodiment of the present invention further provides an electroplating lead structure of a PCIE gold finger.

The golden fingers comprise a ground network golden finger 11 and a non-ground network golden finger 12 which are arranged on the PCB, and the ground network golden finger 11 is connected with the ground hole 13 positioned on the first side of the ground network golden finger, specifically connected through a copper sheet 14; the first side may be one side of the gold finger in the length direction.

The electroplating lead structure comprises: a first plating bus 31 and a first plating branch 32 provided on the PCB; the first electroplating bus 31 connects all the ground holes 13 on the first side of the gold finger together and extends out of the second side edge and/or the third side edge 15 of the PCB; the first plating branch 32 connects one or more of the non-ground network fingers 12 to the first plating bus 31.

It can be understood that the electroplating lead structure is simple in structure and fewer in leads, and is beneficial to lead processing after electroplating processing. For example, as described above, post-plating lead processing can be accomplished using only drilling. The lead structure is particularly suitable for the golden finger structures of PCIE GEN5 and PCIE GEN 6.

In one embodiment, in the case of the plating being completed, a cutoff structure for cutting off the connection of the non-ground network gold finger 12 and the first plating bus 31 is provided on the first plating branch 32 at a position close to the non-ground network gold finger 12.

In one embodiment, the intercepting structure is a hole 33 structure.

In one embodiment, the first plating bus 31 is formed as a unitary piece of sheet metal; alternatively, the first plating bus 31 is formed as a split type metal sheet including: the connecting structure comprises a plurality of middle section metal sheets erected between adjacent ground holes 13 on the first side of the golden finger, a second side metal sheet extending out of the second side edge of the PCB from the ground hole on the first side of the golden finger, and/or a third side metal sheet extending out of the third side edge of the PCB from the ground hole on the first side of the golden finger.

In one embodiment, the first plating branch 32 includes: leads extending from the non-ground network fingers 12 in a first direction and connected to the first plating bus 31. The first direction is a direction from the non-ground network gold finger towards the first side thereof.

In one embodiment, the PCIE gold finger includes: a PCIE GEN5 gold finger, a PCIE GEN6 gold finger, or other versions of PCIE gold fingers having the same or similar structure.

Referring to fig. 5, based on the same technical concept, an embodiment of the present invention further provides another electroplating lead structure for a PCIE gold finger.

The golden fingers comprise a ground network golden finger 11 and a non-ground network golden finger 12 which are arranged on a PCB, wherein the ground network golden finger 11 is connected with a ground hole 13 which is positioned on the first side of the ground network golden finger, and specifically can be connected through a copper sheet 14.

The electroplating lead structure comprises: the method comprises the following steps: a second plating bus 51 and a second plating branch 52 provided on the PCB; the second plating bus 52 includes at least: extending the one or more ground holes of the first side of the gold finger out of the second side plating bus of the second side edge of the PCB board, and/or extending the one or more ground holes of the first side of the gold finger out of the third side plating bus of the third side edge of the PCB board; and the second plating branch connects one or more of the non-ground network gold fingers 12 to an adjacent ground via to electrically connect the non-ground network gold fingers 12 to the second side plating bus and/or the third side plating bus.

It can be understood that the electroplating lead structure is simple in structure and fewer in leads, and is beneficial to lead processing after electroplating processing. For example, as described above, post-plating lead processing can be accomplished using only drilling. The lead structure is particularly suitable for golden finger structures such as PCIE GEN5 and PCIE GEN 6.

In one embodiment, a cutoff structure is provided on the second plating branch 52 near the non-ground network fingers 12 for cutting off the connection of the non-ground network fingers 12 and the second plating bus 51 when plating is completed.

In one embodiment, the intercepting structure is a hole 53 structure.

In one embodiment, the second plating branch 52 comprises: a bent lead respectively connected from one or more non-ground net gold fingers 12 to an adjacent second adjacent ground via and/or a bent lead respectively connected from one or more non-ground net gold fingers 12 to an adjacent first adjacent ground via, the first adjacent ground via being adjacent to a first side edge of the PCB board with respect to the non-ground net gold fingers 12, the second adjacent ground via being adjacent to a second side edge of the PCB board with respect to the non-ground net gold fingers 12.

In one embodiment, the PCIE gold finger includes: PCIE GEN5 fingers, PCIE GEN6 fingers, and similar PCIE fingers in subsequent PCIE versions.

Based on the same technical concept, the embodiment of the utility model provides a still provide a PCIE golden finger, it includes: the PCIE electroplating lead structure is provided.

While the spirit and principles of the invention have been described with reference to several particular embodiments, it is to be understood that the invention is not limited to the particular embodiments disclosed, nor is the division of aspects, which is for convenience only as the features in such aspects may not be combined to benefit. The invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims (12)

1. An electroplating lead structure of a PCIE golden finger is characterized in that the golden finger comprises a ground network golden finger (11) and a non-ground network golden finger (12) which are arranged on a PCB board, and the ground network golden finger (11) is connected with a ground hole (13) which is positioned on the first side of the ground network golden finger; the electroplating lead structure comprises:

a first plating bus (31) and a first plating branch line (32) provided on the PCB;

the first electroplating bus (31) connects all the ground holes (13) on the first side of the golden finger together and extends out of a second side edge and/or a third side edge of the PCB, wherein the second side edge and the third side edge are two opposite side edges of the PCB;

the first plating branch (32) connects one or more of the non-ground network gold fingers (12) to the first plating bus (31).

2. The structure according to claim 1, characterized in that, in case of plating completion, a truncation structure for truncating the connection of the non-ground network gold finger (11) and the first plating bus (31) is provided on the first plating branch (32) at a position close to the non-ground network gold finger (12).

3. A structure according to claim 2, characterized in that the intercepting structure comprises a hole (33) structure.

4. The structure of claim 1, further comprising:

the first plating bus (31) is formed as a one-piece metal sheet; alternatively, the first and second electrodes may be,

the first plating bus (31) is formed as a split metal sheet including: the metal sheet comprises a middle section metal sheet erected between adjacent ground holes (13), a second side metal sheet extending out of the second side edge of the PCB from one or more ground holes (13) on the first side of the golden finger, and/or a third side metal sheet extending out of the third side edge of the PCB from one or more ground holes (13) on the first side of the golden finger.

5. The structure of claim 1,

the first plating branch (32) includes: leads extending in a first direction from the non-ground network gold finger (12) and connected to the first plating bus (31).

6. The fabric of claim 1, wherein the PCIE gold finger comprises: a PCIE GEN5 gold finger and/or a PCIE GEN6 gold finger.

7. An electroplating lead structure of a PCIE golden finger is characterized in that the golden finger comprises a ground network golden finger (11) and a non-ground network golden finger (12) which are arranged on a PCB board, and the ground network golden finger (11) is connected with a ground hole (13) which is positioned on the first side of the ground network golden finger; the electroplating lead structure comprises:

a second plating bus (51) and a second plating branch line (52) provided on the PCB; wherein, the first and the second end of the pipe are connected with each other,

the second plating bus (51) comprises at least: a second side plating bus extending from the one or more ground holes (13) of the first side of the gold finger out of a second side edge of the PCB board, and/or a third side plating bus extending from the one or more ground holes (13) of the first side of the gold finger out of a third side edge of the PCB board, wherein the second side edge and the third side edge are opposite sides of the PCB board; and the number of the first and second groups,

the second plating branch (52) connects the non-ground network goldfinger (12) to a ground via adjacent thereto to electrically connect the non-ground network goldfinger (12) to the second side plating bus and/or the third side plating bus.

8. The structure of claim 7, wherein a intercepting structure for intercepting the electrical connection of the non-ground network gold finger (12) and the second plating bus (51) is provided on the second plating branch (52) at a position close to the non-ground network gold finger (12) in case of completion of plating.

9. The structure according to claim 8, characterized in that the intercepting structure is a hole (53) structure.

10. The structure of claim 7,

the second plating branch (52) comprising: a curved lead from the non-terrestrial network goldfinger (12) to a first adjacent terrestrial hole adjacent thereto and/or a curved lead from the non-terrestrial network goldfinger (12) to a second adjacent terrestrial hole adjacent thereto;

the first adjacent ground hole is close to the first side edge of the PCB board relative to the non-ground net golden finger (12), and the second adjacent ground hole is close to the second side edge of the PCB board relative to the non-ground net golden finger (12).

11. The fabric of claim 7, wherein the PCIE gold finger comprises: a PCIE GEN5 gold finger and/or a PCIE GEN6 gold finger.

12. A PCIE golden finger, comprising:

the lead structure of any one of claims 1-6 or claims 7-11.

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