CN217690067U

CN217690067U - Low-power consumption SoC chip with improve structure

Info

Publication number: CN217690067U
Application number: CN202221564044.3U
Authority: CN
Inventors: 郭小龙; 吴海阳; 王保根
Original assignee: Jiangsu Jinyidaneng Technology Co ltd
Current assignee: Jiangsu Jinyidaneng Technology Co ltd
Priority date: 2022-06-21
Filing date: 2022-06-21
Publication date: 2022-10-28
Anticipated expiration: 2032-06-21

Abstract

The utility model discloses a low-power consumption SoC chip with improved structure, which comprises a signal input voltage source circuit, wherein the signal input voltage source circuit is sequentially connected with a power-down protection circuit, a control logic circuit, a clock gating circuit, a low-power consumption control circuit and a Flash memory; the signal input voltage source circuit is in signal connection with the clock gating circuit, and the low-power consumption control circuit is in signal connection with the control logic circuit. By improving the internal circuit structure of the chip and adding a low-power-consumption power-down protection circuit, a control circuit and the like, the integral power consumption of the chip can be reduced while the internal information, data processing and computing capabilities of the chip are ensured; the chip power supply voltage power failure detection method can judge when the chip power supply voltage is in power failure, so that the chip is switched to a low-power-consumption working mode immediately after the chip is in power failure, the working current of the chip is reduced, and the power failure retention time of internal data is prolonged.

Description

Low-power consumption SoC chip with improve structure

Technical Field

The utility model relates to a SoC chip technical field particularly, relates to a low-power consumption SoC chip with improve structure.

Background

The SOC chip, as a chip of an integrated circuit, has become the most important product development method for the industry due to its advantages of low development cost, short development period, etc. In the design of the current SOC chip, in order to increase the operation speed of the processor in the SOC chip, a memory outside the chip has been gradually integrated into the chip, that is, the existing SOC chip usually includes a processor, a built-in memory, a logic controller/analog controller, and so on, where the built-in memory may adopt a RAM/ROM memory, and may also adopt a Flash program memory (which may be referred to as a Flash memory for short), and due to the difference of the specific structure and the control logic, the control of the Flash memory is much more complicated than the RAM/ROM memory, and the complicated control also easily causes greater power consumption, which affects the overall working efficiency of the SOC chip. In the past, chip designs all have general design requirements such as low power consumption. If the designed chip has lower power consumption, the chip can gain absolute advantage in the similar chip market. Therefore, low power design is an important factor in the whole chip design process.

In the prior art, a chip often provides a plurality of operation modes to control the operation current, such as a standby mode, a shutdown mode, and the like. Although these operation modes can reduce the operation current of the chip in the period of time from 1.8V to 0.7V, in practical applications, the user often does not know when the power supply is suddenly powered down, and may power down in the normal operation mode or in the shutdown mode, and therefore, there is a certain uncertainty about the sudden power down of the power supply. When the power supply is powered off in a normal working mode, the power consumption current of the chip is usually large at the moment, and the power consumption current is hundreds of microamperes or even milliamperes, so that the residual electric quantity of the battery or the electric quantity stored in the capacitor is rapidly discharged, and certain loss is formed. Therefore, a certain power failure protection structure needs to be added to the chip circuit to avoid the damage of power failure and power failure.

However, since the protection circuit needs to detect the value of the power supply voltage constantly, the circuit still needs to be in a working state after the chip normally works, and in a chip with low power consumption, the whole under-voltage protection circuit needs to consume a very low quiescent current. Therefore, the conventional under-voltage protection circuit is not suitable for being applied to a low-power chip.

An effective solution to the problems in the related art has not been proposed yet.

SUMMERY OF THE UTILITY MODEL

To the problem in the correlation technique, the utility model provides a low-power consumption SoC chip with improve structure to overcome the above-mentioned technical problem that current correlation technique exists.

Therefore, the utility model discloses a specific technical scheme as follows:

a low-power consumption SoC chip with an improved structure comprises a signal input voltage source circuit, wherein the signal input voltage source circuit is sequentially connected with a power-down protection circuit, a control logic circuit, a clock gating circuit, a low-power consumption control circuit and a Flash memory; the signal input voltage source circuit is in signal connection with the clock gating circuit, and the low-power consumption control circuit is in signal connection with the control logic circuit.

Further, the power-down protection circuit comprises a diode D1, a diode D2, a resistor R1, a triode Q1 and a voltage monitoring chip U1;

the power input end is respectively connected with the anode of the diode D1 and the input end of the voltage monitoring chip U1, the cathode of the diode D1 is respectively connected with the cathode of the diode D2 and one end of the resistor R1, the anode of the diode D2 is grounded, the RESET end of the voltage monitoring chip U1 is connected with the base electrode of the triode Q1, the other end of the resistor R1 is connected with the collector of the triode Q1 and serves as the output end, and the emitter of the triode Q1 is grounded.

Further, the model of the voltage monitoring chip U1 is a voltage monitoring chip IMP809.

Further, the low power consumption control circuit comprises a resistor R2, a resistor R3, a resistor R4, a resistor R5, a bidirectional thyristor TR1, a diode D3 and a triode Q2;

wherein, the bidirectional triode thyristor TR1 positive pole with resistance R3's one end is connected and is regarded as low-power consumption control circuit's input, the bidirectional triode thyristor TR1 gate pole with resistance R2 one end is connected and to control logic circuit input feedback signal, the bidirectional triode thyristor TR1 negative pole with the resistance R2 other end and resistance R4's one end is connected, the resistance R4 other end with the resistance R3 other end connect and respectively with diode D3 positive pole triode Q2 collecting electrode is connected, diode D3 negative pole ground connection, triode Q2 base ground connection, triode Q2 projecting pole with resistance R5 one end is connected, the resistance R5 other end is regarded as low-power consumption control circuit's output.

Further, the low power consumption control circuit is configured to perform sector erasure or chip erasure on the Flash memory according to the clock input of the clock gating circuit, and immediately feed back an erasure completion signal to the control logic circuit after the operation is completed.

Furthermore, the signal input voltage source circuit inputs a clock signal to the clock gating circuit, and the control logic circuit inputs a clock gating signal to the clock gating circuit.

The beneficial effects of the utility model are that: by improving the internal circuit structure of the chip and adding a low-power-consumption power-down protection circuit, a control circuit and the like, the integral power consumption of the chip can be reduced while the internal information, data processing and computing capabilities of the chip are ensured; the chip can judge when the power supply voltage of the chip is powered down, so that the chip is switched to a low-power-consumption working mode immediately after the power supply voltage of the chip is powered down, and the working current of the chip is reduced, thereby prolonging the power-down retention time of internal data, solving the problem that the internal memory has short data retention time under certain conditions due to uncertain power-down time in the prior art, and effectively reducing the power consumption loss caused by the instant increase of the chip current due to false triggering; meanwhile, a low-power-consumption control circuit is added, and the integrated control circuit has the functional advantages of low cost, simple circuit, easy integration and small size, and has lower standby power consumption, low working energy consumption and stronger practicability and universality.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a low power consumption SoC chip with an improved structure according to an embodiment of the present invention;

fig. 2 is a schematic circuit diagram of a power down protection circuit in a low power SoC chip with an improved structure according to an embodiment of the present invention;

fig. 3 is a schematic circuit diagram of a low power consumption control circuit in a low power consumption SoC chip with an improved structure according to an embodiment of the present invention.

In the figure:

1. a signal input voltage source circuit; 2. a power down protection circuit; 3. a control logic circuit; 4. a clock gating circuit; 5. a low power consumption control circuit; 6. a Flash memory.

Detailed Description

For further explanation of the embodiments, the drawings are provided as part of the disclosure and serve primarily to illustrate the embodiments and, together with the description, to explain the principles of operation of the embodiments, and to provide further explanation of the invention and advantages thereof, it will be understood by those skilled in the art that various other embodiments and advantages of the invention are possible, and that elements in the drawings are not to scale and that like reference numerals are generally used to designate like elements.

According to the utility model discloses an embodiment provides a low-power consumption SoC chip with improve structure.

Referring now to the drawings and the detailed description, as shown in fig. 1-3, according to the embodiment of the present invention, the SoC chip with improved structure comprises a signal input voltage source circuit 1, wherein the signal input voltage source circuit 1 is sequentially connected with a power down protection circuit 2, a control logic circuit 3, a clock gating circuit 4, a low power consumption control circuit 5 and a Flash memory 6; the signal input voltage source circuit 1 and the clock gating circuit 4 are in signal connection, and the low-power consumption control circuit 5 and the control logic circuit 3 are in signal connection.

In one embodiment, as shown in fig. 2, the power down protection circuit 2 includes a diode D1, a diode D2, a resistor R1, a triode Q1, and a voltage monitoring chip U1;

In one embodiment, the voltage monitoring chip U1 is of a type of the voltage monitoring chip IMP809.

As shown in fig. 2, the key device of the power-down protection circuit 2 is a voltage monitoring chip IMP809, and the main characteristic is its open-drain output characteristic and S0T23 encapsulation, and has high-precision voltage detection, and based on many advantages unique to IMP809, the invention is far superior to the traditional implementation scheme, and usually includes a voltage reference comparator, a logic gate circuit and other parts, and has the characteristics of simple structure, few elements, small volume, low cost, high reliability and the like, and the working current is provided for VCC, and no backup battery is used to provide extra current, so that the working time of the backup battery is greatly prolonged. When the power supply voltage is higher than the detection voltage Vt, the output presents a high resistance state, normal read/write memory operation is allowed, when the power supply voltage is lower than the Vt (such as power-on/power-off processes), the IMP809 outputs active ground, a chip selection/enable signal from an external memory is clamped at a low level, the read/write operation of the memory is forbidden, the integrity of the content of the memory is ensured, and the memory is in a standby mode with low power consumption. Two low dropout diodes, such as two IN4148 or one BAT54C, are used to switch between VCC and a backup battery, which can disable the charging of the battery after power-up from Vcc, and on the other hand, can enable the battery to operate at a lower voltage, making full use of the battery's capacity.

In one embodiment, as shown in fig. 3, the low power consumption control circuit 5 includes a resistor R2, a resistor R3, a resistor R4, a resistor R5, a triac TR1, a diode D3, and a transistor Q2;

wherein, the bidirectional thyristor TR1 positive pole with resistance R3's one end is connected and is regarded as low-power consumption control circuit 5's input, the bidirectional thyristor TR1 gate pole with resistance R2 one end is connected and to control logic circuit 3 input feedback signal, the bidirectional thyristor TR1 negative pole with the resistance R2 other end and resistance R4's one end is connected, the resistance R4 other end with the resistance R3 other end connect and respectively with diode D3 positive pole triode Q2 collecting electrode is connected, diode D3 negative pole ground connection, triode Q2 base ground connection, triode Q2 projecting pole with resistance R5 one end is connected, the resistance R5 other end is regarded as low-power consumption control circuit 5's output.

In one embodiment, the low power consumption control circuit 5 is configured to perform sector erasure or chip erasure on the Flash memory 6 according to the clock input of the clock gating circuit 4, and immediately feed back an erasure completion signal to the control logic circuit 3 after the operation is completed.

In one embodiment, the signal input voltage source circuit 1 inputs a clock signal to the clock gating circuit 4, and the control logic circuit 3 inputs a clock gating signal to the clock gating circuit 4.

In summary, with the aid of the technical solution of the present invention, by improving the internal circuit structure of the chip, and adding the power down protection circuit and the control circuit with low power consumption, the power consumption of the whole chip can be reduced while the internal information, data processing and computing capabilities of the chip are ensured; the chip can judge when the power supply voltage of the chip is powered down, so that the chip is switched to a low-power-consumption working mode immediately after the power supply voltage of the chip is powered down, and the working current of the chip is reduced, thereby prolonging the power-down retention time of internal data, solving the problem that the internal memory has short data retention time under certain conditions due to uncertain power-down time in the prior art, and effectively reducing the power consumption loss caused by the instant increase of the chip current due to false triggering; meanwhile, a low-power-consumption control circuit is added, and the integrated LED lamp has the functional advantages of low cost, simple circuit, easiness in integration and small size, and is lower in standby power consumption, low in working energy consumption and higher in practicability and universality.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "disposed," "connected," "fixed," "screwed" and the like are to be construed broadly, e.g., as meaning fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through an intermediate medium, and may be connected through the inside of two elements or in an interaction relationship between two elements, unless otherwise specifically defined, and the specific meaning of the above terms in the present invention will be understood by those skilled in the art according to specific situations.

The above description is only for the preferred embodiment of the present invention, and should not be taken as limiting the invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A low power consumption SoC chip with an improved structure, comprising a signal input voltage source circuit (1), characterized in that:

the signal input voltage source circuit (1) is sequentially connected with a power-down protection circuit (2), a control logic circuit (3), a clock gating circuit (4), a low-power-consumption control circuit (5) and a Flash memory (6);

the signal input voltage source circuit (1) is in signal connection with the clock gating circuit (4), and the low-power consumption control circuit (5) is in signal connection with the control logic circuit (3).

2. The low-power-consumption SoC chip with the improved structure is characterized in that the power-down protection circuit (2) comprises a diode D1, a diode D2, a resistor R1, a triode Q1 and a voltage monitoring chip U1;

3. The improved low-power consumption SoC chip is characterized in that the voltage monitoring chip U1 is of the type of a voltage monitoring chip IMP809 according to claim 2.

4. The SoC chip with improved structure of claim 1, wherein said low power consumption control circuit (5) comprises a resistor R2, a resistor R3, a resistor R4, a resistor R5, a triac TR1, a diode D3 and a transistor Q2;

wherein, the bidirectional thyristor TR1 positive pole with resistance R3's one end is connected and is regarded as the input of low-power consumption control circuit (5), the bidirectional thyristor TR1 gate pole with resistance R2 one end is connected and to control logic circuit (3) input feedback signal, the bidirectional thyristor TR1 negative pole with the resistance R2 other end and resistance R4's one end is connected, the resistance R4 other end with the resistance R3 other end connect and respectively with diode D3 positive pole triode Q2 collecting electrode is connected, diode D3 negative pole ground connection, triode Q2 base ground connection, triode Q2 projecting pole with resistance R5 one end is connected, the resistance R5 other end is regarded as the output of low-power consumption control circuit (5).

5. The SoC chip with improved structure, according to claim 4, characterized in that said low power consumption control circuit (5) is configured to perform sector erasure or slice erasure on said Flash memory (6) according to the clock input of said clock gating circuit (4), and immediately feed back an erasure completion signal to said control logic circuit (3) after the operation is completed.

6. A low power consumption SoC chip with improved structure, according to claim 1 or 5, characterized by that, the signal input voltage source circuit (1) inputs clock signal to the clock gating circuit (4), the control logic circuit (3) inputs clock gating signal to the clock gating circuit (4).