CN217563658U - Chip and communication system - Google Patents
Chip and communication system Download PDFInfo
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- CN217563658U CN217563658U CN202221230131.5U CN202221230131U CN217563658U CN 217563658 U CN217563658 U CN 217563658U CN 202221230131 U CN202221230131 U CN 202221230131U CN 217563658 U CN217563658 U CN 217563658U
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Abstract
The utility model relates to a chip, a serial communication port, include: a first active circuit including at least two input/output ports and coupled to the first pad and the second pad, respectively, to receive a power supply signal from another chip; a first resistor and a second resistor connected in series between the two input/output ports; a second active circuit coupled between a junction of the first and second resistances and ground potential; wherein the chip receives a power supply signal from another chip only through the first and second pads. The utility model discloses still relate to a chip, a serial communication port, include: n first active circuits, a group of first bonding pads and second bonding pads corresponding to each active circuit, and N groups of first resistors and second resistors; the chip receives a power supply signal from another chip only through N sets of the first and second pads. The utility model discloses still relate to the communication system including aforementioned any kind of chip.
Description
Technical Field
The present invention relates to an integrated circuit, and more particularly to a chip and a communication system.
Background
The chip is usually designed with a dedicated power interface, and an external power supply supplies power to the chip through the dedicated power interface. However, in some application environments, the chip cannot obtain proper power supply from the outside, and other methods for supplying power are needed. For example, in some broadband high-speed communication chip applications, the high-speed communication chip includes multiple groups of high-speed communication interfaces, the power consumption consumed by the high-speed communication chip is large, and the dedicated power interface cannot provide the power consumption required by the high-speed communication chip, so that other methods are needed to supply power to the chip to provide the power consumption required by the chip.
Fig. 1 is a schematic diagram of a communication system for supplying power to a chip via an external power supply. The system may include a chip 101 and a chip 102, both of which are, for example, wideband high-speed communication chips, which may be coupled by high-frequency wideband transmission lines 1007 and 1008. The system shown in fig. 1 also includes an external power supply 1001 for powering the chip 101 and an external power supply 1002 for powering the chip 102. If any one external power supply cannot provide the power consumption required by the operation of the corresponding chip, the two chips cannot normally operate in the power supply mode.
SUMMERY OF THE UTILITY MODEL
To the technical problem who exists among the prior art, the utility model provides a chip, a serial communication port, include: a first active circuit including at least two input/output ports and coupled to the first pad and the second pad, respectively, to receive a power supply signal from another chip; a first resistor and a second resistor connected in series between the two input/output ports; a second active circuit coupled between a connection of the first and second resistances and ground potential; wherein the chip receives a power supply signal from another chip only through the first and second pads.
In particular, the circuit is characterized by further comprising a first capacitor which is coupled between a connection point of the first resistor and the second resistor and the ground potential.
In particular, the first resistor and the second resistor have the same resistance.
The utility model also provides a chip, its characterized in that, including N first active circuit, wherein each said first active circuit includes at least two input/output ports, each said two input/output ports of group couple to the first pad and the second pad in each group respectively, in order to receive the power supply signal from another chip; n sets of series resistors, wherein each set of series resistors comprises a first resistor and a second resistor connected in series between the two input/output ports of the corresponding first active circuit, wherein the connection points of the first and second resistors of each set are electrically connected to each other; a second active circuit coupled between a junction of each set of the first and second resistances and ground potential; and the chip receives a power supply signal from another chip only through N groups of the first bonding pads and the second bonding pads, wherein N is an integer greater than or equal to 2.
In particular, the circuit is characterized by further comprising a first capacitor which is coupled between a connection point of each set of the first resistor and the second resistor and the ground potential.
In particular, the first resistor and the second resistor in each of the N groups of series resistors have the same resistance.
The utility model also provides a communication system, a serial communication port, include: a first chip as described above; and the second chip comprises a third resistor and a fourth resistor, one ends of the third resistor and the fourth resistor receive power supply signals from an external power supply, and the other ends of the third resistor and the fourth resistor are respectively coupled to the third bonding pad and the fourth bonding pad so as to be coupled with the first bonding pad and the second bonding pad through transmission lines and supply power to the first chip.
In particular, the circuit further comprises a second capacitor, which is coupled between a connection point of the first resistor and the second resistor and a ground potential, outside the first chip.
The utility model also provides a communication system, a serial communication port, include: a first chip as described above; the second chip comprises N groups of third resistors and fourth resistors, one end of each group of the third resistors and the fourth resistors receives a power supply signal from an external power supply, the other end of each group of the third resistors and the fourth resistors is respectively coupled to N groups of bonding pads, each group of the bonding pads respectively comprises a third bonding pad and a fourth bonding pad, and each group of the third bonding pads and the fourth bonding pads is coupled with the first bonding pads and the second bonding pads in the corresponding group through transmission lines and supplies power to the first chip; wherein N is an integer greater than or equal to 2.
In particular, it is characterized in that it further comprises, outside said first chip, a second capacitor coupled between the junction of each set of said first and second resistors and ground potential.
The utility model provides an interface power supply chip and communication system can't provide the required consumption of chip work at the external power source of chip, perhaps under the unable condition that obtains suitable external power source power supply of other chips, makes the chip still can be through the communication interface of self by other chip power supplies, maintains normal work.
Drawings
Preferred embodiments of the present invention will be described in further detail below with reference to the attached drawings, wherein:
FIG. 1 is a schematic diagram of a communication system for powering a chip via an external power supply;
fig. 2 is a schematic diagram of a system for supplying power to a chip through a communication interface according to an embodiment of the present invention; and
fig. 3 is a schematic diagram of a cascaded system for supplying power to a chip through a communication interface according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the different views. The various specific embodiments of the present invention are described in sufficient detail below to enable those skilled in the art, having the benefit of the teachings and teachings herein, to practice the invention. It is to be understood that other embodiments may be utilized and structural, logical, or electrical changes may be made to the embodiments of the present invention.
Fig. 2 is a schematic diagram of a system for supplying power to a chip through a communication interface according to an embodiment of the present invention. According to one embodiment, the system may include chip 201 and chip 202, both of which may be broadband high-speed communication chips, which may be coupled by high-frequency broadband transmission lines 2007 and 2008.
According to one embodiment, for example, chip 202 may be powered by external power supply 2002, where external power supply 2002 has a voltage V DD_Terminal . Chip 202 may include resistors R3 and R4, one end of R3 and R4 may be coupled to external power supply 2002, and the other end may be coupled to respective transmission lines 2007 and 2008 through input/output (I/O) pads 2005 and 2006, respectively. According to one embodiment, the values of the resistors R3 and R4 may match and conform to the communication protocol of the communication system, e.g., the values of R3 and R4 may be the same.
According to an embodiment, the chip 201 is a powered chip, and the chip 201 may include an input/output interface active circuit 203 implementing a signal transmission function of the communication system, and resistors R1 and R2 coupled in series to two input/output terminals OU1 and OU2 of the input/output interface active circuit 203. Meanwhile, two input/output terminals OU1 and OU2 of the input/output interface active circuit 203 are connected to transmission lines 2007 and 2008 through I/ O pads 2003 and 2004, respectively, so as to communicate with the chip 202.
According to one embodiment, chip 201 further includes active circuitry 204, i.e., active circuitry in chip 201 that performs functions other than communication system signaling, where active circuitry 204 is coupled between common mode voltage point Q of chip 201 and ground. The voltage of the common mode voltage point Q of the chip 201 is V Common The common mode voltage point Q may be a connection point between the resistors R1 and R2.
According to one embodiment, in order to ensure the stability of the voltage of the common mode voltage point Q on the chip 201, the common mode voltage point Q needs to be connected with a decoupling capacitor.
According to one embodiment, chip 201 may further include a capacitor C2 coupled between common mode voltage point Q and ground.
According to an embodiment, a capacitor C1 coupled between the common mode voltage point Q and the ground may be further included outside the chip 201.
According to various embodiments, the common mode voltage point Q of the chip 201 may be coupled to only C1 or C2, or to both C1 and C2. According to one embodiment, the values of C1 and C2 may be the same and both are greater than 100 picofarads.
According to one embodiment, the values of resistors R1 and R2 may match and conform to the communication protocol of the communication system, e.g., the values of R1 and R2 may be the same.
According to one embodiment, current I provided by external power supply 2002 of chip 202 flows through resistors R3 and R4 and transmission lines 2007 and 2008 in chip 202 in sequence to chip 201. After the supply current I enters the chip 201, the supply current I is divided into two parts: one part directly supplies power to the input/output interface active circuit 203; the other part flows through the resistors R1 and R2 to the common mode voltage point Q of the chip 201, and then flows from the common mode voltage point Q to the active circuit 204 to supply power to the active circuit 204. In a sense, the common mode voltage point Q is equivalent to the "supply" of the active circuit 204. Voltage V at common mode voltage point Q Common Is the external supply voltage V of the chip 202 DD_Terminal Minus the voltage drop across resistor R3 in chip 202, and minus the voltage drop across resistor R1 in chip 201.
According to one embodiment, as shown in fig. 2, in a communication system including chip 201 and chip 202, high-speed signal channel 205 may include input/output interface active circuitry 203, resistors R1 and R2, and I/ O pads 2003 and 2004 in chip 201, resistors R3 and R4 and I/ O pads 2005 and 2006 in chip 202, and transmission lines 2007 and 2008 between chips 201 and 202.
Fig. 3 is a schematic diagram of a cascaded system for supplying power to a chip through a communication interface according to an embodiment of the present invention. According to one embodiment, the system may include chip 301 and chip 302, both of which may be wideband high-speed communication chips, which may be coupled via N sets of high frequency wideband transmission lines each including 3007-1 and 3008-1 or 3007-N and 3008-N. N may be an integer of 2 or more.
According to one embodiment, for example, chip 302 may be powered by an external power supply 3002, external power supply 3002 having a voltage V DD_Terminal . According to one embodiment, chip 301 is a powered chip.
According to one embodiment, as shown in FIG. 3, in a communication system including chip 301 and chip 302, high-speed signal path 305-1 may include input/output interface active circuitry 303-1, resistors R1-1 and R2-1, and I/O pads 3003-1 and 3004-1 in chip 301, resistors R3-1 and R4-1 and I/O pads 3005-1 and 3006-1 in chip 302, and transmission lines 3007-1 and 3008-1 between chips 301 and 302. According to one embodiment, the high speed signal path 305-1 of FIG. 3 may be identical in structure and connection to the high speed signal path 205 of FIG. 2.
According to one embodiment, as shown in FIG. 3, in a communication system including a chip 301 and a chip 302, another N-1 high-speed signal paths 305-2 to 305-N may be further included, and the structure and connection manner of the N-1 high-speed signal paths and the high-speed signal path 305-1 may be the same.
According to one embodiment, one end of the N sets of resistors R3-1 and R4-1 through R3-N and R4-N in the chip 302 may be coupled to an external power source 3002.
According to an embodiment, chip 301 further comprises an active circuit 304, i.e. an active circuit in chip 301 that performs other functions than the function of signal transmission of the communication system, active circuit 304 being coupled between common mode voltage point Q and ground potential of chip 301. The voltage of the common mode voltage point Q of the chip 301 is V Common The common mode voltage point Q may be the connection point between each of the N sets of resistors R1-1 and R2-1 through R1-N and R2-N.
According to one embodiment, in order to ensure the stability of the voltage of the common mode voltage point Q on the chip 301, the common mode voltage point Q needs to be connected with a decoupling capacitor.
According to one embodiment, chip 301 may further include a capacitor C2 coupled between common mode voltage point Q and ground.
According to an embodiment, a capacitor C1 coupled between the common mode voltage point Q and the ground may also be included outside the chip 301.
According to various embodiments, the common mode voltage point Q of chip 301 may be coupled to only C1 or C2, or to both C1 and C2. According to one embodiment, the values of C1 and C2 may be the same and both are greater than 100 picofarads.
According to one embodiment, current I provided by external power source 3002 of chip 302 flows sequentially through N sets of resistors R3-1 and R4-1 through R3-N and R4-N and N sets of transmission lines 3007-1 and 3008-1 through 3007-N and 3008-N in chip 302 to chip 301. After the supply current I enters the chip 301, the supply current I is divided into two parts: one part directly supplies power to the N input/output interface active circuits 303-1 to 303-N; the other part flows through N groups of resistors R1-1 and R2-1 to R1-N and R2-N to a common mode voltage point Q of the chip 301, and then flows to the active circuit 304 from the common mode voltage point Q to supply power to the active circuit 304. In a sense, the common mode voltage point Q is equivalent to the "supply" of the active circuit 304. Voltage V at common mode voltage point Q Common External supply voltage V for chip 302 DD_Terminal Minus the voltage drop across resistor R3-1 in chip 302 and minus the voltage drop across resistor R1-1 in chip 301.
The above embodiments are provided only for the purpose of illustration, and are not intended to limit the present invention, and those skilled in the relevant art can make various changes and modifications without departing from the scope of the present invention, and therefore, all equivalent technical solutions should also belong to the scope of the present invention.
Claims (10)
1. A chip, comprising:
a first active circuit including at least two input/output ports and coupled to the first pad and the second pad, respectively, to receive a power supply signal from another chip;
a first resistor and a second resistor connected in series between the two input/output ports;
a second active circuit coupled between a junction of the first and second resistances and ground potential;
wherein the chip receives a power supply signal from another chip only through the first and second pads.
2. The chip of claim 1, further comprising a first capacitor coupled between a junction of the first and second resistors and ground potential.
3. The chip of claim 1, wherein the first resistor and the second resistor have the same resistance.
4. A chip is characterized by comprising
N first active circuits, wherein each of the first active circuits includes at least two input/output ports, each of the two input/output ports being respectively coupled to the first pad and the second pad in each group to receive a power supply signal from another chip;
n sets of series resistors, wherein each set of series resistors comprises a first resistor and a second resistor connected in series between the two input/output ports of the corresponding first active circuit, wherein the connection points of the first and second resistors of each set are electrically connected to each other;
a second active circuit coupled between a junction of each set of the first and second resistances and ground potential;
and the chip receives a power supply signal from another chip only through N groups of the first bonding pads and the second bonding pads, wherein N is an integer greater than or equal to 2.
5. The chip of claim 4, further comprising a first capacitor coupled between a junction of each set of the first and second resistors and ground potential.
6. The chip of claim 4, wherein the first and second resistors of each of the N sets of series resistors are the same value.
7. A communication system, comprising
A first chip comprising the chip of any one of claims 1-3;
and the second chip comprises a third resistor and a fourth resistor, one end of each of the third resistor and the fourth resistor receives a power supply signal from an external power supply, and the other end of each of the third resistor and the fourth resistor is respectively coupled to the third bonding pad and the fourth bonding pad so as to be coupled with the first bonding pad and the second bonding pad of the first chip through a transmission line and supply power to the first chip.
8. The communication system of claim 7, further comprising a second capacitor external to the first chip coupled between a junction of the first and second resistors and ground potential.
9. A communication system, comprising
A first chip comprising the chip of any one of claims 4-6;
the second chip comprises N groups of third resistors and fourth resistors, one end of each group of the third resistors and the fourth resistors receives a power supply signal from an external power supply, the other end of each group of the third resistors and the fourth resistors is respectively coupled to N groups of bonding pads, each group of the N groups of the bonding pads respectively comprises a third bonding pad and a fourth bonding pad, and each group of the third bonding pads and the fourth bonding pads is coupled with the first bonding pads and the second bonding pads in the corresponding group of the first chip through transmission lines and supplies power to the first chip;
wherein N is an integer greater than or equal to 2.
10. The communication system of claim 9, further comprising a second capacitance coupled between a junction of each set of the first and second resistances and ground, external to the first chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221230131.5U CN217563658U (en) | 2022-05-18 | 2022-05-18 | Chip and communication system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221230131.5U CN217563658U (en) | 2022-05-18 | 2022-05-18 | Chip and communication system |
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| Publication Number | Publication Date |
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| CN217563658U true CN217563658U (en) | 2022-10-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202221230131.5U Active CN217563658U (en) | 2022-05-18 | 2022-05-18 | Chip and communication system |
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| CN (1) | CN217563658U (en) |
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- 2022-05-18 CN CN202221230131.5U patent/CN217563658U/en active Active
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