CN117276259A - Communication chip comprising laminated power domain structure - Google Patents

Communication chip comprising laminated power domain structure Download PDF

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Publication number
CN117276259A
CN117276259A CN202210653365.9A CN202210653365A CN117276259A CN 117276259 A CN117276259 A CN 117276259A CN 202210653365 A CN202210653365 A CN 202210653365A CN 117276259 A CN117276259 A CN 117276259A
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China
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amplifier
chip
coupled
node
resistor
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洪芃力
李旋
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Suzhou Hanchen Technology Co ltd
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Suzhou Hanchen Technology Co ltd
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Priority to CN202210653365.9A priority Critical patent/CN117276259A/en
Publication of CN117276259A publication Critical patent/CN117276259A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Amplifiers (AREA)

Abstract

The application relates to a chip comprising a first active circuit, a second active circuit and a first control circuit, wherein the first active circuit receives an input signal, amplifies and outputs the input signal; the first active circuit includes a third amplifier having two output terminals coupled to the first and second pads of the chip, respectively, to output signals, a power terminal thereof receiving a power signal from the outside, and a ground terminal thereof coupled to the first node; the second amplifier, two output ends are coupled to two input ends of the third amplifier respectively, its power end receives the power signal from the outside, its ground is grounded; the input end of the first amplifier receives the input signal, the two output ends of the first amplifier are respectively coupled to the two input ends of the second amplifier, the power supply end of the first amplifier is coupled to the first node, and the ground is grounded; the second amplifier converts the level between the first amplifier and the third amplifier; the chip also comprises a first resistor and a second resistor which are connected in series between two output ends of the third amplifier, and a second node which is connected with the first resistor and the second resistor receives a power supply signal from the outside.

Description

Communication chip comprising laminated power domain structure
Technical Field
The present application relates to an integrated circuit chip, and in particular to a communication chip including a stacked power domain structure.
Background
With the increase of the demand of high-speed data transmission service, how to make the broadband high-speed communication chip have better low-power consumption performance is a problem to be solved.
Fig. 1 is a schematic diagram of a conventional high-speed data transmission system. The system shown in fig. 1 includes a high-speed transmitting chip 101 and a high-speed receiving chip 102, which may be electrically connected by, for example, a high-speed differential transmission line. The high-speed transmitting chip 101 may include a core active circuit 1003 that assumes a signal transmitting function and a remaining active circuit 1004 that assumes functions other than signal transmission; wherein the core active circuit 1003 may include three serially cascaded amplifiers: differential amplifier B1, differential amplifier B2, and CML differential amplifier B3.
The system shown in fig. 1 may also include an external power supply 1001 for powering the high-speed transmit chip 101, at a voltage V DDH The method comprises the steps of carrying out a first treatment on the surface of the And an external power supply 1002 for supplying power to the high-speed receiving chip 102, the voltage being V DD_Terminal . The core active circuit 1003 and the remaining active circuits 1004 are each coupled between the external power supply 1001 and ground potential.
Specifically, in the core active circuit 1003, two input terminals of the amplifier B1 receive an input signal that needs to be received by the chip 101, two output terminals of the amplifier B1 are coupled to two input terminals of the amplifier B2, two output terminals of the amplifier B2 are coupled to two input terminals of the amplifier B3, and two output terminals of the amplifier B3 are coupled to transmission lines through pads, respectively, to transmit signals to the chip 102. Meanwhile, the power terminals of the amplifiers B1, B2, and B3 are coupled to the external power supply 1001, and the ground terminals are all receiving the ground potential. In this case, the sum of the power consumption of the chip 101 and the current flowing through the amplifiers B1, B2, and B3 is equal to V DDH Is related to the product of (a). If the chip 101 includes more serial cascade amplifiers, the power consumption of the chip 101 will be increased along with the increase of the number of the amplifiers, especially when the working current required by the amplifiers is larger, the consumed power consumption will be larger, and a series of problems such as excessive power consumption of the chip, easy heating and damage will be brought about, so how to reduce the power consumption of the high-speed communication chip is a problem to be solved.
Disclosure of Invention
To the technical problem that exists among the prior art, this application provides a communication chip including range upon range of power domain structure, includes: a first active circuit configured to receive an input signal, and amplify and output the input signal; the first active circuit comprises at least a first amplifier, a second amplifier and a third amplifier which are coupled with each other, wherein two output ends of the third amplifier are respectively coupled to a first bonding pad and a second bonding pad of the chip so as to output signals, a power end of the third amplifier is configured to receive power signals from the outside, and a ground end of the third amplifier is coupled to a first node; the two output ends of the second amplifier are respectively coupled to the two input ends of the third amplifier, the power supply end of the second amplifier is configured to receive a power supply signal from the outside, and the ground end of the second amplifier is connected to the ground potential; the input end of the first amplifier receives the input signal, two output ends are respectively coupled to the two input ends of the second amplifier, the power end of the first amplifier is coupled to the first node, and the ground end of the first amplifier receives the ground potential; the second amplifier is configured to convert a level between the first amplifier and the third amplifier; the chip further includes a first resistor and a second resistor connected in series between two output terminals of the third amplifier, and a second node connecting the first resistor and the second resistor is configured to receive a power signal from the outside.
In particular, the chip as described above further comprises a push-pull low dropout linear regulator having an input coupled to said second node and an output coupled to said first node.
In particular, the chip as described above further comprises a first decoupling capacitor coupled between said second node and ground potential.
In particular, the first resistor and the second resistor have the same resistance value.
In particular, the chip as described above, wherein at least one of the first amplifier, the second amplifier and the third amplifier comprises N serially cascaded sub-amplifiers, N being an integer greater than 1, wherein the power supply terminals of the N sub-amplifiers are coupled to each other and the ground terminals are coupled to each other.
In particular, the chip as described above further comprises a second active circuit coupled between said second node and ground potential.
The application also proposes a communication system comprising: a first chip as described above; and a second chip including a third resistor and a fourth resistor, one ends of the third resistor and the fourth resistor being configured to receive a power signal from the outside, and the other ends being coupled to the third pad and the fourth pad, respectively, to receive a signal transmitted from the first chip through a transmission line.
In particular, the communication system as described above further comprises a second decoupling capacitor located outside the first chip and the second chip coupled between the second node and ground potential.
In particular, the communication system as described above, wherein the power signal received by the first chip is provided by the second chip.
Drawings
Preferred embodiments of the present application will be described in further detail below with reference to the attached drawing figures, wherein:
FIG. 1 is a schematic diagram of a prior art high-speed data transmission system;
FIG. 2 is a schematic diagram of a high-speed data transmission system employing a communication chip including a stacked power domain structure in accordance with one embodiment of the present application;
FIG. 3 is a schematic diagram of a high-speed data transmission system employing a communication chip including a stacked power domain structure in accordance with one embodiment of the present application; and
fig. 4 is a schematic diagram of a high-speed data transmission system architecture employing interface powering and a chip including a stacked power domain architecture according to one embodiment of the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the application may be practiced. In the drawings, like reference numerals describe substantially similar components throughout the different views. Various specific embodiments of the present application are described in sufficient detail below to enable those skilled in the art to practice the teachings of the present application. It is to be understood that other embodiments may be utilized or structural, logical, or electrical changes may be made to the embodiments of the present application.
Fig. 2 is a schematic diagram of a high-speed data transmission system employing a communication chip including a stacked power domain structure according to one embodiment of the present application. The system shown in fig. 2 may include a high-speed transmit chip 201 and a high-speed receive chip 202, which may be coupled to each other by, for example, a high-speed differential transmission line. The system shown in fig. 2 may also include an external power supply 2001 and an external power supply 2002;2001 is configured to supply power to the high-speed transmitting chip 201, which has a voltage of V DDH The method comprises the steps of carrying out a first treatment on the surface of the 2002 is configured to power the high-speed receiving chip 202 at a voltage V DD_Terminal 。
According to one embodiment, the high-speed transmit chip 201 may include a core active circuit 2003 that implements signal transmission functions, and a remaining active circuit 2004 that implements functions other than signal transmission.
According to one embodiment, core active circuit 2003 may include amplifiers A1, A2, and A3. According to one embodiment, A1 and A2 may be differential amplifiers and A3 may be CML differential amplifiers.
Specifically, according to one embodiment, the power supply terminal of the amplifier A3 may be coupled to the external power supply 2001, the ground terminal may be coupled to the junction 2007, and the voltage value at 2007 is V DDL . The external power supply 2001 is configured to supply an operating current to A3, the operating current flowing in from the A3 power supply terminal and flowing out from the A3 ground terminal. The two output ends of A3 are respectively coupled with the transmission line through the bonding pads.
According to one embodiment, the power supply terminal of amplifier A1 is coupled to node 2007 and the ground terminal is at ground potential. The two outputs of A1 are coupled to the two inputs of amplifier A2, respectively. The current flowing from the ground of amplifier A3 flows through node 2007 to provide an operating current for A1. The two inputs of A1 receive input signals that need to be received by chip 201.
According to one embodiment, the power supply terminal of amplifier A2 is coupled to an external power supply 2001 and the ground terminal receives ground potential. The two outputs of A2 are coupled to the two inputs of amplifier A3, respectively. A2 is configured to amplify the level of the output signal of the amplifier A1 from the ground potential to V in addition to the system transmission signal amplification function DDL Interval transition to V DDL To V DDH Is input to the amplifier A3.
According to one embodiment, high-speed transmit chip 201 may also include resistors R1 and R2 connected in series, coupled between the two outputs of amplifier A3. The connection node between R1 and R2 is coupled to an external power supply 2001.
According to one embodiment, the remaining active circuitry 2004 is coupled between an external power supply 2001 and ground potential, 2001 also being configured to provide operating current to 2004.
According to one embodiment, high-speed receive chip 202 may include resistors R3 and R4. One ends of R3 and R4 are coupled with an external power supply 2002, and the other ends are respectively coupled with a transmission line through a bonding pad.
According to one embodiment, the resistors R1, R2, R3, and R4 are differential matched resistors of the high-speed data transmission system shown in fig. 2, and the resistance satisfies r1=r2=r3=r4. According to one embodiment, the resistance may be 50 ohms.
The connection of the amplifiers A1, A2, A3 in the core active circuit 2003 in the system shown in fig. 2 implements a stacked power domain architecture, where A3 and A1 are stacked and connected, and the operating current required for A1 is mainly provided by the current flowing from the ground terminal of A3. That is, the power supply domain of VDDH to GND is divided into two stacked sub power supply domains (the sub power supply domain of VDDH to VDDL and the sub power supply domain of VDDL to GND).
According to one embodiment, the operating currents of the amplifiers A1 and A3 may be made approximately comparable by design. However, in practical situations, the working currents of A1 and A3 have random mismatch, and it is difficult to achieve that the working currents are completely equal to each other. At this time, the power consumption of the chip 201 is no longer equal to the sum of the operating currents of A1 and A3 and V DDH Is related to the product of A1 and A3, but to the larger of the operating currents of A1 and A3And V is respectively with DDH And the product correlation of (c) significantly reduces the power consumption of the core active circuit 2003 and even the entire chip.
According to one embodiment, core active circuit 2003 may also include Push-Pull LDO 2005. The LDO 2005 is coupled between the external power supply 2001 and the junction 2007 and is configured to match unequal portions of the operating currents of the amplifiers A3 and A1. Specific: when the A3 operating current is greater than the A1 operating current, LDO 2005 sinks current from node 2007; when the A3 operating current is less than the A1 operating current, LDO 2005 outputs current to node 2007. Thereby acting to stabilize the DC voltage V at the junction 2007 DDL Is effective in (1).
According to one embodiment, the system shown in fig. 2 may further comprise an off-chip decoupling capacitor C1 coupled between the external power supply 2001 and ground potential.
According to one embodiment, the high-speed transmit chip 201 in the system shown in fig. 2 may also include a decoupling capacitor C2 coupled between the external power supply 2001 and ground potential.
According to one embodiment, the system shown in FIG. 2 may include either C1 or C2 or both C1 and C2.
According to one embodiment, the values of C1 and C2 may be the same or different and are both greater than 100 picofarads.
Fig. 3 is a schematic diagram of a high-speed data transmission system employing a communication chip including a stacked power domain structure according to one embodiment of the present application. The system shown in fig. 3 may include a high-speed transmit chip 301 and a high-speed receive chip 302, which may be coupled to each other by, for example, a high-speed differential transmission line. The system shown in fig. 3 may also include an external power supply 3001 and an external power supply 3002;3001 is configured to supply power to the high-speed transmitting chip 301, which has a voltage V DDH The method comprises the steps of carrying out a first treatment on the surface of the 3002 is configured to supply power to the high-speed receiving chip 302, which has a voltage V DD_Terminal 。
According to one embodiment, the high-speed transmit chip 301 may include a core active circuit 3003 that implements signal transmission functionality, and the remaining active circuits 3004 that implement functionality other than signal transmission.
According to one implementationFor example, the core active circuit 3003 may include three amplifier groups A1 composed of a plurality of serially cascaded amplifiers 1 ～A1 X 、A2 1 ～A2 Y And A3 1 ～A3 Z . According to one embodiment, X, Y, Z is an integer greater than 1. According to one embodiment, the values of X, Y, Z may be the same or different. According to one embodiment, A1 1 ～A1 X And A2 1 ～A2 Y May be a differential amplifier group, A3 1 ～A3 Z May be a CML differential amplifier bank.
Specifically, the amplifier group A3 1 ～A3 Z All power terminals of (1) can be coupled with an external power supply 3001, all ground terminals can be coupled with a node 3007, and the voltage value at 3007 is V DDL . The external power supply 3001 is configured to supply power to A3 1 ～A3 Z Providing an operating current from A3 1 ～A3 Z The power supply end flows in from A3 1 ～A3 Z And the ground end flows out. A3A 3 1 Is coupled to the transmission line via a pad, respectively.
According to one embodiment, the amplifier bank A1 1 ～A1 X Is coupled to node 3007, and all ground terminals are connected to ground potential. A1A 1 1 Is coupled to the two output terminals of the amplifier A2 Y Is provided. Slave amplifier group A3 1 ～A3 Z The current flowing from the ground terminal flows through node 3007 as A1 1 ～A1 X An operating current is provided. A1A 1 1 Is to receive an input signal that requires the chip 302 to receive.
According to one embodiment, the amplifier bank A2 1 ～A2 Y Is coupled to the external power supply 3001, and all the ground terminals are connected to ground potential. A2A 2 1 Is coupled to the two output terminals of the amplifier A3 Z Is provided. A2A 2 1 ～A2 Y In addition to implementing the system transmission signal amplifying function, the amplifier A1 is also configured to X The level of the output signal being from ground to V DDL Interval transition to V DDL To V DDH Is input to the amplifier A3 1 。
According to one embodiment, the high-speed transmit chip 301 may further include resistors R1 and R2 connected in series, coupled to the amplifier A3 1 Between the two outputs of (a). The connection node between R1 and R2 is coupled to an external power supply 3001.
According to one embodiment, the remaining active circuitry 3004 is coupled between an external power supply 3001 and ground potential, with 3001 also configured to provide operating current to 3004.
According to one embodiment, the high-speed receive chip 302 may include resistors R3 and R4. One ends of R3 and R4 are coupled to the external power supply 3002, and the other ends are coupled to the transmission lines through pads, respectively.
According to one embodiment, the resistors R1, R2, R3, and R4 are differential matching resistors of the high-speed data transmission system shown in fig. 3, and the resistance satisfies r1=r2=r3=r4. According to one embodiment, the resistance may be 50 ohms.
Amplifier bank A1 in core active circuit 3003 in the system shown in fig. 3 1 ～A1 X 、A2 1 ～A2 Y And A3 1 ～A3 Z Realizes a laminated power domain structure by the connection mode of A3 1 ～A3 Z And A1 1 ～A1 X Laminated connection, A1 1 ～A1 X The required working current is mainly composed of A3 1 ～A3 Z The current flowing out of the ground is provided.
According to one embodiment, the amplifier group A1 may be designed to 1 ～A1 X And A3 1 ～A3 Z Is approximately equivalent to the operating current of (c). In actual cases, however, A1 1 ～A1 X And A3 1 ～A3 Z Random mismatch exists in the working currents of the two, and the two are difficult to be completely equal. At this time, the power consumption of the chip 301 is no longer equal to the sum of the operating currents of the X+Z amplifiers and V DDH But rather to the larger of the sum of the operating currents of the X or Z amplifiers in the two sets of amplifiers, and V DDH The power consumption of the core active circuitry 3003 and thus of the whole chip is significantly reduced.
According to one embodiment, the core active circuit 3003 may also include push-pull low dropout linear voltage regulatorA Push-Pull LDO 3005. The LDO 3005 is coupled between the external power supply 3001 and the node 3007 and configured to match the amplifier bank A3 1 ～A3 Z And A1 1 ～A1 X Unequal portions of the operating current of (a). Specific: when A3 is 1 ～A3 Z The working current is greater than A1 1 ～A1 X During operation, LDO 3005 sinks current from 3007; when A3 is 1 ～A3 Z The working current is less than A1 1 ～A1 X In the operation current, LDO 3005 outputs a current to 3007. Thereby stabilizing the DC voltage V at 3007 DDL Is effective in (1).
According to one embodiment, the system shown in FIG. 3 may also include an off-chip decoupling capacitor C1 coupled between the external power supply 3001 and ground.
According to one embodiment, the high speed transmit chip 301 in the system shown in fig. 3 may also include a decoupling capacitor C2 coupled between the external power supply 3001 and ground potential.
According to one embodiment, the system shown in FIG. 3 may include either C1 or C2 or both C1 and C2.
According to one embodiment, the values of C1 and C2 may be the same or different and are both greater than 100 picofarads.
Fig. 4 is a schematic diagram of a high-speed data transmission system architecture employing interface powering and a chip including a stacked power domain architecture according to one embodiment of the present application. The system shown in fig. 4 may include a high-speed transmitting chip 401 and a high-speed receiving chip 402, which may be coupled to each other by, for example, a high-speed differential transmission line. The system of FIG. 4 may also include an external power source 4002 configured to provide power to the high-speed receiving chip 402 at a voltage V DD_Terminal . Unlike the system shown in fig. 2 or 3, the system shown in fig. 4 does not include an external power supply for supplying power to the high-speed transmitting chip 401, but power is supplied to the high-speed transmitting chip 401 from the high-speed receiving chip 402 through the high-speed transmission interface of the chip.
According to one embodiment, the high-speed transmission chip 401 may include a core active circuit 4003 that implements a signal transmission function, and the remaining active circuits 4004 that implement functions other than signal transmission.
According to one embodiment, the core active circuit 4003 may comprise amplifiers A1, A2, and A3. According to one embodiment, A1 and A2 may be differential amplifiers and A3 may be CML differential amplifiers.
According to one embodiment, the high speed transmit chip 401 may also include resistors R1 and R2 connected in series, coupled between the two outputs of the amplifier A3. The connection node between R1 and R2 is coupled with an equivalent high-speed receiving chip power supply node 4006, and the voltage value at 4006 is V 1H 。
According to one embodiment, the two output terminals of the amplifier A3 are coupled to the transmission line through pads, respectively, while being coupled to both ends of the resistors R1 and R2 connected in series; the ground of A3 is coupled with the node 4007, and the voltage value at 4007 is V 1L . Chip 402 provides an operating current for A3, which flows in from both outputs of A3 and out from the ground of A3.
According to one embodiment, the power supply terminal of amplifier A1 is coupled to node 4007 and the ground terminal is at ground potential. The two outputs of A1 are coupled to the two inputs of amplifier A2, respectively. The current from the ground of amplifier A3 flows through node 4007 to provide an operating current for A1. The two inputs of A1 receive input signals that need to be received by chip 401.
According to one embodiment, the power supply terminal of amplifier A2 is coupled to power supply node 4006 and the ground terminal receives ground potential. The two outputs of A2 are coupled to the two inputs of amplifier A3, respectively. A2 is configured to amplify the level of the output signal of the amplifier A1 from the ground potential to V in addition to the system transmission signal amplification function 1L Interval transition to V 1L To V 1H Is input to the amplifier A3.
According to one embodiment, the remaining active circuit 4004 is coupled between the power supply node 4006 and ground potential.
According to one embodiment, high-speed receive chip 402 may include resistors R3 and R4. One ends of R3 and R4 are coupled to the external power source 4002, and the other ends are coupled to the transmission line through pads, respectively.
According to one embodiment, the resistors R1, R2, R3, and R4 are differential matching resistors of the high-speed data transmission system shown in fig. 4, and the resistance satisfies r1=r2=r3=r4. According to one embodiment, the resistance may be 50 ohms.
In the system shown in fig. 4, according to one embodiment, an operating current I1 supplied from an external power source 4002 to a high-speed receiving chip 402 flows through resistors R3 and R4, flows through a transmission line to a high-speed transmitting chip 401, and supplies a required operating current to A3 through two output terminals of an amplifier A3. The working current flows into A3 from two output ends of A3 and then flows out from the ground end of A3; the current flowing from ground A3 again continues to provide the desired operating current for amplifier A1, at which point node 4007 corresponds to the "power" terminal of A1.
In the system shown in fig. 4, according to one embodiment, an operating current I1 supplied from an external power source 4002 to a high-speed receiving chip 402 flows through resistors R3 and R4, through a transmission line to a high-speed transmitting chip 401, and then flows through resistors R1 and R2 to a power supply node 4006, and flows into the power supply terminal of an amplifier A2 and the remaining active circuits 4004, respectively, to supply the operating currents required for A2 and 4004. At this time 4006 corresponds to the "power" terminals of A2 and 4004, the voltage value V at 4006 1H Voltage value V equal to external power source 4002 DD_Terminal The voltage drop across resistor R3 and the voltage drop across resistor R1 are subtracted. Thus the greater the power consumption of the high-speed transmitting chip 401, V 1H The lower the level is in order to make V 1H Still meeting the operational requirements of the high-speed transmit chip 401, the power consumption of the chip 401 must be tightly controlled.
The connection of the amplifiers A1, A2, A3 in the core active circuit 4003 in the system shown in fig. 4 realizes a stacked power domain structure, and the operation current required by A1 is mainly provided by the current flowing out of the ground terminal of A3 by stacking A3 and A1.
According to one embodiment, the operating currents of the amplifiers A1 and A3 may be made approximately comparable by design. However, in practical situations, the working currents of A1 and A3 have random mismatch, and it is difficult to achieve that the working currents are completely equal to each other. At this time, the power consumption of the chip 401 is no longer equal to the sum of the operating currents of A1 and A3 and V 1H Is related to the product of A1 and A3, but the larger of the operating currents of A1 and A3 is related to V 1H Is related to the product of the chip, the work of the core active circuit 4003 and even the whole chip is obviously reducedConsumption is reduced.
Thus, according to one embodiment, the core active circuit 4003 may further comprise a Push-Pull low dropout linear regulator (Push-Pull LDO) 4005. The LDO 4005 is coupled between the power supply node 4006 and the node 4007 and is configured to match unequal portions of the operating currents of A3 and A1. Specific: when the A3 operating current is greater than the A1 operating current, LDO 4005 sinks current from 4007; when the A3 operating current is less than the A1 operating current, LDO 4005 outputs current to 4007. Thereby stabilizing the direct current voltage V at 4007 1L Is effective in (1).
According to one embodiment, the system shown in fig. 4 may further include an off-chip decoupling capacitor C1 coupled between the power supply node 4006 and ground potential.
According to one embodiment, the high speed transmit chip 401 in the system of fig. 4 may also include a decoupling capacitor C2 coupled between the power supply node 4006 and ground potential.
According to one embodiment, the system shown in FIG. 4 may include either C1 or C2 or both C1 and C2.
According to one embodiment, the values of C1 and C2 may be the same or different and are both greater than 100 picofarads.
According to one embodiment, the amplifiers A1, A2 and A3 in the system of FIG. 4 may be replaced by three amplifier groups A1 consisting of a plurality of serially cascaded amplifiers, respectively 1 ～A1 X 、A2 1 ～A2 Y And A3 1 ～A3 Z . According to one embodiment, A1 1 ～A1 X And A2 1 ～A2 Y May be a differential amplifier group, A3 1 ～A3 Z May be a CML differential amplifier bank. The connection and operation of the system are similar to those of the system shown in fig. 4.
The above embodiments are provided for illustrating the present application and are not intended to limit the present application, and various changes and modifications can be made by one skilled in the relevant art without departing from the scope of the present application, therefore, all equivalent technical solutions shall fall within the scope of the present disclosure.

Claims (9)

1. A chip, comprising:
a first active circuit configured to receive an input signal, and amplify and output the input signal; the first active circuit includes at least a first amplifier, a second amplifier, and a third amplifier coupled to each other, wherein,
two output ends of the third amplifier are respectively coupled to a first bonding pad and a second bonding pad of the chip to output signals, a power supply end of the third amplifier is configured to receive power supply signals from the outside, and a ground end of the third amplifier is coupled to a first node;
the two output ends of the second amplifier are respectively coupled to the two input ends of the third amplifier, the power supply end of the second amplifier is configured to receive a power supply signal from the outside, and the ground end of the second amplifier is connected to the ground potential;
the input end of the first amplifier receives the input signal, two output ends are respectively coupled to the two input ends of the second amplifier, the power end of the first amplifier is coupled to the first node, and the ground end of the first amplifier receives the ground potential;
the second amplifier is configured to convert a level between the first amplifier and the third amplifier;
the chip further includes a first resistor and a second resistor connected in series between two output terminals of the third amplifier, and a second node connecting the first resistor and the second resistor is configured to receive a power signal from the outside.
2. The chip of claim 1, further comprising a push-pull low dropout linear regulator having an input coupled to the second node and an output coupled to the first node.
3. The chip of claim 1, further comprising a first decoupling capacitor coupled between the second node and ground potential.
4. The chip of claim 1, wherein the first and second resistances are the same.
5. The chip of any of claims 1-4, wherein at least one of the first, second, and third amplifiers comprises N serially cascaded sub-amplifiers, N being an integer greater than 1, wherein power supply terminals of the N sub-amplifiers are coupled to each other and ground terminals are coupled to each other.
6. A chip as claimed in any one of claims 1 to 4, further comprising a second active circuit coupled between the second node and ground potential.
7. A communication system, comprising:
a first chip as claimed in any one of claims 1 to 6;
and a second chip including a third resistor and a fourth resistor, one ends of the third resistor and the fourth resistor being configured to receive a power signal from the outside, and the other ends being coupled to the third pad and the fourth pad, respectively, to receive a signal transmitted from the first chip through a transmission line.
8. The communication system of claim 7, further comprising a second decoupling capacitor located off-chip of the first and second chips coupled between the second node and ground potential.
9. The communication system of claim 7, wherein the power signal received by the first chip is provided thereto by the second chip.
CN202210653365.9A 2022-06-09 2022-06-09 Communication chip comprising laminated power domain structure Pending CN117276259A (en)

Priority Applications (1)

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CN202210653365.9A CN117276259A (en) 2022-06-09 2022-06-09 Communication chip comprising laminated power domain structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210653365.9A CN117276259A (en) 2022-06-09 2022-06-09 Communication chip comprising laminated power domain structure

Publications (1)

Publication Number Publication Date
CN117276259A true CN117276259A (en) 2023-12-22

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210653365.9A Pending CN117276259A (en) 2022-06-09 2022-06-09 Communication chip comprising laminated power domain structure

Country Status (1)

Country Link
CN (1) CN117276259A (en)

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