CN217470384U - Asymmetric PCB core board of roughness and PCB are range upon range of - Google Patents

Abstract

The embodiment of the utility model provides an asymmetric PCB core of roughness and PCB are range upon range of, wherein, the PCB core includes: the signal transmission layer, the first medium layer and the signal reference layer; the dielectric layer is positioned between the signal transmission layer and the signal reference layer; the surface roughness of the signal transmission layer is smaller than that of the signal reference layer; the PCB stack-up includes TOP layer, BOTTOM layer, second dielectric layer and two or more than two the utility model discloses the PCB core that the arbitrary embodiment provided, through above-mentioned scheme, can satisfy the roughness requirement of signal to core signal transmission layer surface; and when the requirement of transmitting high-frequency signals is met, the surface roughness of the signal reference layer is reduced, so that the processing process flow of the copper foil of the signal reference layer is reduced, the production cost of the core plate is reduced, the requirement of the roughness of the copper foil is continuously improved along with the continuous improvement of the signal speed, and the cost advantage is more and more obvious.

Description

Asymmetric PCB core board of roughness and PCB are range upon range of

Technical Field

The embodiment of the utility model provides a relate to the PCB field, especially relate to an asymmetric PCB core of roughness and PCB are range upon range of.

Background

Pcb (printed Circuit board), which is called printed Circuit board in chinese, is an important electronic component, is a support for electronic components, and is a carrier for electrical interconnection of electronic components. It is called a "printed" circuit board because it is made using electronic printing. At present, a PCB plate supplier mainly provides CORE boards (CORE) with the same roughness on both sides, and when hardware equipment manufacturers such as downstream IT, communication, medical treatment and the like design and develop multilayer PCBs, the CORE boards (CORE) with the same roughness on both sides are also adopted to design PCB stacking. At present, with the increasing of signal rate, due to the influence of skin effect on signal quality, a core board with smaller surface roughness needs to be selected when the PCB is designed and laminated; the core board with smaller surface roughness has more complex processing flow process requirements of the copper foil and higher cost; and under the condition that the number of layers of the PCB is large, the number of required core plates is large, so that the overall cost of the PCB is increased due to the fact that the surface roughness of the copper foil is improved.

SUMMERY OF THE UTILITY MODEL

In view of this, the utility model provides an asymmetric PCB core of roughness and PCB range upon range of to solve the transmission signal quality that exists among the prior art poor and the too high problem of cost.

In order to solve the above problem, the embodiment of the utility model provides an adopt following technical scheme:

in a first aspect, the utility model provides an asymmetric core of roughness, include: the signal transmission layer, the first medium layer and the signal reference layer; the first medium layer is positioned between the signal transmission layer and the signal reference layer; the surface roughness of the signal transmission layer is smaller than that of the signal reference layer.

In the above the utility model discloses an in asymmetric PCB core of roughness, signal transmission layer and signal reference layer are the copper foil of different grade type.

In THE above-described PCB core having asymmetric surface roughness according to THE present invention, THE type of THE copper foil is preferably one of THE types of THE same, RTF2/RTF3, HVLP1 or UHVLP.

In the above PCB core with asymmetric surface roughness of the present invention, the first dielectric layer is a prepreg; the prepreg comprises glass fibers and epoxy resin, and the signal transmission layer and the glass fibers as well as the glass fibers and the signal reference layer are adhered through the epoxy resin.

In a second aspect, the present invention further provides a PCB stackup, which is characterized by comprising: TOP layer, BOTTOM layer, second dielectric layer and two or more if the utility model discloses the asymmetric PCB core board of roughness in the first aspect.

Above-mentioned the utility model discloses an in PCB is range upon range of, TOP layer and BOTTOM layer are the copper foil and make.

In the aforesaid the utility model discloses an in PCB is range upon range of, TOP layer with between the PCB core the BOTTOM layer with between the PCB core, all set up between each PCB core the second dielectric layer.

In the above configuration, the second dielectric layer is a prepreg.

Compared with the prior art, the beneficial effects of the utility model are that:

1. by the scheme, the requirement of signals on the roughness of the surface of the signal transmission layer of the core board can be met;

2. the requirement for the surface roughness of the signal reference layer is reduced while high-frequency signal transmission is met, so that the processing process flow of the copper foil of the signal reference layer is reduced, the production cost of the core plate is reduced, the requirement for the roughness of the copper foil is continuously improved along with the continuous improvement of the signal speed, and the cost advantage is more and more obvious.

Drawings

Fig. 1 is a schematic structural diagram of a PCB core with asymmetric surface roughness according to an embodiment of the present invention;

fig. 2 is a diagram of a signal simulation result in an embodiment of the present invention;

fig. 3 is a diagram of a signal simulation result in an embodiment of the present invention;

fig. 4 is a diagram of a signal simulation result in an embodiment of the present invention;

fig. 5 is a schematic structural diagram of a PCB stack in an embodiment of the present invention.

The PCB comprises a signal transmission layer 1, a signal transmission layer 2, a first dielectric layer 3, a signal reference layer 100, a TOP layer 200, a BOTTOM layer 300, a second dielectric layer 400, a PCB CORE board 401, CORE1, 402, CORE2, 403, CORE3, 404, CORE4, 405, CORE5, 406 and CORE 6.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

As shown in fig. 1, an embodiment of the present invention provides an asymmetric surface roughness PCB core, including: a signal transmission layer 1, a first medium layer 2 and a signal reference layer 3; the first medium layer 2 is positioned between the signal transmission layer 1 and the signal reference layer 3; the surface roughness of the signal transmission layer 1 is smaller than the surface roughness of the signal reference layer 3.

With the upgrading of technology and the increasing of signal transmission rate, the skin effect of signals is more and more obvious, and therefore, the surface roughness of the copper foil is required to be higher and higher. At present, the roughness of copper foils on two sides of a core board provided by a board factory is consistent, but the smaller the surface roughness of the core board, the more complex the processing flow process requirement of the copper foils is, and the higher the cost is. Therefore, the utility model provides an asymmetric PCB core of roughness reduces signal reference layer roughness requirement when satisfying transmission high frequency signal to reduce signal reference layer copper foil processing technology flow, reduce core manufacturing cost.

The signal transmission layer 1 and the signal reference layer 3 are different types of copper foils. In practical implementation, the copper foil roughness and the suggested application fields can be divided into the following fields:

copper foil type	Roughness (um)	Field of application
			HTE	≤10	PCIE2.0, PCIE1.0, etc. (Signal Rate lower than 8 gbps)
RTF	≤5	PCIE3.0、10G/25G Switch
			RTF2/RTF3	≤2.1	PCIE4.0/PCIE5.0、100G Switch
HVLP	≤1.5	PCIE4.0/PCIE5.0、100G Switch
			HVLP1	≤1	PCIE5.0、400G Switch
UHVLP	≤0.8	PCIE6.0、800G Switch

Furthermore, because the technology is constantly advanced, in the utility model discloses in, the selection of copper foil type is not restricted to above-mentioned type, for example the copper foil of types such as RTF4 of latest research and development production all can be regarded as signal transmission layer or signal reference layer in the utility model, only need under the circumstances of guaranteeing signal transmission quality requirement, satisfy as the surface roughness of the copper foil of signal transmission layer 1 be less than as the surface roughness of the copper foil of signal reference layer 3 can.

Preferably, the dielectric layer 2 is a prepreg. The prepreg comprises glass fibers and epoxy resin, and the signal transmission layer 1 and the glass fibers as well as the glass fibers and the signal reference layer 3 are adhered through the epoxy resin.

The embodiment of the utility model provides an in, can compare PCB core signal transmission layer 1, the influence of 3 roughness on signal transmission on signal reference layer from signal emulation angle.

The first condition is as follows: assuming that both the signal transmission layer and the signal reference layer of the PCB core board are ideal copper foils (roughness is 0), signal simulation is performed on the ideal copper foils to obtain signal trace simulation insertion loss, and as a result, as shown in fig. 2, it can be seen that 8GHZ insertion loss is 5.01dB, and 16GHZ insertion loss is 7.82 dB.

Case two: assuming that the signal transmission layer and the signal reference layer of the PCB core board are both RTF2 copper foils, performing signal simulation on the RTF2 copper foils to obtain signal trace simulation insertion loss, and as a result, as shown in fig. 3, it can be seen that 8GHZ insertion loss is 5.99dB, and 16GHZ insertion loss is 9.87 dB. Compared with the result in the first case, the 8GHZ insertion loss difference is 0.98dB, the 16GHZ insertion loss difference is 2.05dB, and the difference is obvious in a high-frequency section, namely the surface roughness of the copper foil has a large influence on high-frequency signals.

Case three: if the signal transmission layer of the PCB core is RTF2 copper foil and the signal reference layer is ideal copper foil (roughness is 0), signal simulation is performed on the ideal copper foil to obtain signal trace simulation insertion loss, and as shown in fig. 4, it can be seen that 8GHZ insertion loss is 5.98dB and 16GHZ insertion loss is 9.83 dB. It can be seen that the difference between the two frequency point insertion losses and the result in the second case is not large, that is, the surface roughness of the signal reference layer has little influence on the signal transmission of the PCB core board.

Therefore, the requirement on the surface roughness of the signal reference layer can be reduced under the condition of meeting the requirement of transmitting high-frequency signals, and the copper foil with higher roughness is selected as the signal reference layer, so that the processing process flow of the copper foil of the signal reference layer is reduced, and the production cost of the core board is reduced.

Fig. 5 is a schematic structural diagram of a PCB stack provided in an embodiment of the present invention, as shown in fig. 5, an embodiment of the present invention further provides a PCB stack, including: TOP layer 100, BOTTOM layer 200, resin layer 300, and two or more PCB core 400 with asymmetric surface roughness provided by any of the embodiments of the present invention.

Wherein, the TOP layer 100 and the BOTTOM layer 200 are both made of copper foil.

The second dielectric layers 300 are arranged between the TOP layer 100 and the PCB core 400, between the BOTTOM layer 200 and the PCB core 400, and between the PCB cores 400. The second dielectric layer 300 is a prepreg.

The preferred PCB lamination provided by one embodiment of the present invention is a 14-layer structure, wherein ART01 is a TOP layer 100 made of a copper foil; ART14 is a BOTTOM layer 200 made of a sheet of copper foil; PREPREG is the second dielectric layer 300; the rest are different types of PCB core boards; the ART layer shown in the figure is a signal transmission layer, and the GND or PWR layer is a signal reference layer or is used for realizing power supply circulation and GND return. Preferably, the PCB core includes: CORE 1401, said CORE1 including GND02 and ART 03; CORE 2402, wherein the CORE2 comprises GND04 and ART 05; CORE 3403, wherein the CORE3 comprises GND06 and PWR 07; CORE 4404, wherein the CORE4 comprises PWR08 and GND 09; CORE 5405, wherein the CORE5 comprises ART10 and GND 11; CORE 6406, said CORE6 includes ART12 and GND 13.

Wherein, the embodiment of the utility model provides a PCB range upon range of copper foil type can show as following table with the range upon range of copper foil type contrast of conventionality:

	the embodiment of the utility model provides a range upon range of copper foil type of PCB	Conventional PCB laminated copper foil type
			ART01	HTE	HTE
GND02	HTE	RTF2
			ART03	RTF2	RTF2
GND04	HTE	RTF2
			ART05	RTF2	RTF2
GND06	HTE	RTF2
			PWR07	HTE	RTF2
PWR08	HTE	RTF2
			GND09	HTE	RTF2
ART10	RTF2	RTF2
			GND11	HTE	RTF2
ART12	RTF2	RTF2
			GND13	HTE	RTF2
ART14	HTE	HTE

It can be seen that the embodiment of the utility model provides a PCB is range upon range of under the condition that satisfies transmission high frequency signal, has reduced signal reference layer surface roughness requirement, selects the copper foil that roughness is bigger as the signal reference layer to reduce signal reference layer copper foil processing technology flow, reduce core manufacturing cost, when the number of piles that PCB is range upon range of is more, the cost advantage will be more obvious.

It should be noted that the foregoing is only a preferred embodiment of the present invention and the technical principles applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail with reference to the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the scope of the present invention.

Claims (8)

1. A PCB core having asymmetric surface roughness, comprising: the signal transmission layer, the first medium layer and the signal reference layer; the first medium layer is positioned between the signal transmission layer and the signal reference layer; the surface roughness of the signal transmission layer is smaller than that of the signal reference layer.

2. The PCB core with asymmetric surface roughness of claim 1, wherein the signal transmission layer and the signal reference layer are different types of copper foils.

3. THE PCB core with asymmetric surface roughness of claim 2, wherein THE copper foil is of one of THE type of he, RTF2/RTF3, HVLP1 or UHVLP.

4. The PCB core board with asymmetric surface roughness as claimed in claim 1, wherein the first dielectric layer is a prepreg; the prepreg comprises glass fibers and epoxy resin, and the signal transmission layer and the glass fibers as well as the glass fibers and the signal reference layer are adhered through the epoxy resin.

5. A PCB stack-up, comprising: a TOP layer, a BOTTOM layer, a second dielectric layer, and two or more PCB core boards with asymmetric surface roughness as claimed in claims 1-4.

6. The PCB laminate of claim 5, wherein the TOP layer and BOTTOM layer are each made of copper foil.

7. The PCB stack-up of claim 5, wherein the second dielectric layers are disposed between the TOP layer and the PCB core, between the BOTTOM layer and the PCB core, and between each PCB core.

8. The PCB stack-up of claim 7, wherein the second dielectric layer is a prepreg.

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